From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by mx.groups.io with SMTP id smtpd.web10.28253.1599592126641631140 for ; Tue, 08 Sep 2020 12:08:47 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=UOjhHh/h; spf=pass (domain: nuviainc.com, ip: 209.85.128.68, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f68.google.com with SMTP id k18so52540wmj.5 for ; Tue, 08 Sep 2020 12:08:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=tYwHvorBA42mp9DM7Jh+n3mYSv3OwGaxp/j1jzEeWQs=; b=UOjhHh/hYNhS/W7KQxeF2YO7x2m/0F50yLMU1TSfPYAwiJf3hBKO2KMYH0JV2WcKKO e2N0FwukA7TD34P/7aQcvbk4ApztOb2st4VLt0fyXAUg15Yfgkvhl/fvuv59AR914IEO dBEE8NYZYLgd+ZqKx8aYyM7+Ur2lGSr6ANf/nLwo9KgZ5T2dunliGCsJQkwXe8NM4lV3 B9bfqz38KGsSL+TvzCuGyfwhzGeKGFjxvFyEaD/5UQ55uDM6C8e6m+6CnaOd6oJRilnq M6U6Xf2RrwTqnKqYxpyNo5A5PnXNZT/rNd+nNlkOpnTgLeuCPzFM2HFNZ9ydlqQG/ORu KTYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=tYwHvorBA42mp9DM7Jh+n3mYSv3OwGaxp/j1jzEeWQs=; b=nuKR/5jZZ8NoQq7foHg0leXH3+qFd8GY2ioRSy0DD69/5qIkltRFTEuO0kvjpo0Gjg oVTL2yZFDjsoyvNqy3v8Q3dw2e1rNaebc9dZ7J6bKX2rH0Oz8URBIZZrRpA6ZpLxBMlR ZPwF9mBA8M8AoSmpOwIPxBHmaAo5JIyOyTClvKUICWhCyWOJaiNV9a9hr+icaMhcImH+ rlBchgCgM81J+akK3w3rkRW4ugZs5DElASg4WIDxPUoSDU+mZteDkR42gwyUBQ5u3ABQ 0IQ3re56QCVvF/LYa46lMVAFe5rkdbr64sW2rkS2Q73YoWB4Qe938aRH2WY5ZZ6Y0Uov SFYQ== X-Gm-Message-State: AOAM5306/NEg2hYFTbvI+hinvglDD0QlsReHiSY7CC8Z6FPa7fHwdJl/ Z7/f/LBieWPD6UDVoWmMAhWqtQ== X-Google-Smtp-Source: ABdhPJzMI4fJL6O5wL/PrGnlXOl736IwvevtiboGi8KZ5+ZYP0rz4ZXm77B3Zgoo0xcX3QWFzp6vgA== X-Received: by 2002:a7b:ca56:: with SMTP id m22mr558309wml.12.1599592125106; Tue, 08 Sep 2020 12:08:45 -0700 (PDT) Return-Path: Received: from vanye ([2001:470:1f09:12f0:b26e:bfff:fea9:f1b8]) by smtp.gmail.com with ESMTPSA id m13sm477585wrr.74.2020.09.08.12.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2020 12:08:44 -0700 (PDT) Date: Tue, 8 Sep 2020 20:08:37 +0100 From: "Leif Lindholm" To: Tanmay Jagdale Cc: graeme@nuviainc.com, devel@edk2.groups.io, shashi.mallela@linaro.org Subject: Re: [PATCH edk2-platforms 1/1] SbsaQemu: AcpiDxe: Read MPIDR from device tree Message-ID: <20200908190837.GC5623@vanye> References: <20200901182938.76281-1-tanmay.jagdale@linaro.org> MIME-Version: 1.0 In-Reply-To: <20200901182938.76281-1-tanmay.jagdale@linaro.org> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Sep 01, 2020 at 23:59:38 +0530, Tanmay Jagdale wrote: > The Qemu device tree for Sbsa platform now contains MPIDR value > for every CPU in the form of "reg" property under every CPU's > node. Hence, add a function that provides support to read this > value from the device tree. > > Signed-off-by: Tanmay Jagdale Thanks, Tanmay. Reviewed-by: Leif Lindholm Pushed as 8c5c22e667f8. > --- > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 35 ++++++++++++++++++- > 1 file changed, 34 insertions(+), 1 deletion(-) > > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > index 47a9bd1d423a..fb7c1835c3d7 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > @@ -22,6 +22,9 @@ > #include > #include > > +STATIC INT32 FdtFirstCpuOffset; > +STATIC INT32 FdtCpuNodeSize; > + > /* > * A function that walks through the Device Tree created > * by Qemu and counts the number of CPUs present in it. > @@ -56,12 +59,14 @@ CountCpusFromFdt ( > // The count of these subnodes corresponds to the number of > // CPUs created by Qemu. > Prev = fdt_first_subnode (DeviceTreeBase, CpuNode); > + FdtFirstCpuOffset = Prev; > while (1) { > CpuCount++; > Node = fdt_next_subnode (DeviceTreeBase, Prev); > if (Node < 0) { > break; > } > + FdtCpuNodeSize = Node - Prev; > Prev = Node; > } > > @@ -69,6 +74,34 @@ CountCpusFromFdt ( > ASSERT_RETURN_ERROR (PcdStatus); > } > > +/* > + * Get MPIDR from device tree passed by Qemu > + */ > +STATIC > +UINT64 > +GetMpidr ( > + IN UINTN CpuId > + ) > +{ > + VOID *DeviceTreeBase; > + CONST UINT64 *RegVal; > + INT32 Len; > + > + DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); > + ASSERT (DeviceTreeBase != NULL); > + > + RegVal = fdt_getprop (DeviceTreeBase, > + FdtFirstCpuOffset + (CpuId * FdtCpuNodeSize), > + "reg", > + &Len); > + if (!RegVal) { > + DEBUG ((DEBUG_ERROR, "Couldn't find reg property for CPU:%d\n", CpuId)); > + return 0; > + } > + > + return (fdt64_to_cpu (ReadUnaligned64 (RegVal))); > +} > + > /* > * A Function to Compute the ACPI Table Checksum > */ > @@ -173,7 +206,7 @@ AddMadtTable ( > CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE)); > GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New; > GiccPtr->AcpiProcessorUid = NumCores; > - GiccPtr->MPIDR = NumCores; > + GiccPtr->MPIDR = GetMpidr (NumCores); > New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE); > } > > -- > 2.28.0 >