From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.9310.1600322327913376748 for ; Wed, 16 Sep 2020 22:58:47 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: aaron.li@intel.com) IronPort-SDR: l6KHZbY/SA9aAaZQadk3wGKOf2XVGL9C2lDI1N5zwhGq1S7rIHcQkhf3xj5teclkP/vOIoMSCM do9EKiUUrRxg== X-IronPort-AV: E=McAfee;i="6000,8403,9746"; a="157036735" X-IronPort-AV: E=Sophos;i="5.76,435,1592895600"; d="scan'208";a="157036735" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2020 22:58:47 -0700 IronPort-SDR: 7rx2dHeX47Ip5O1IuO5M7bmPZa+CU1un9BlvzqVHwsJrU9FXyZ2I/UzOsRii2W5oS/wa9m1Ojf yJG1iFANe3SQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,435,1592895600"; d="scan'208";a="483611255" Received: from sh1gapp1015.ccr.corp.intel.com ([10.239.189.85]) by orsmga005.jf.intel.com with ESMTP; 16 Sep 2020 22:58:45 -0700 From: "Aaron Li" To: devel@edk2.groups.io Cc: Bob Feng , Liming Gao Subject: [PATCH v1 1/1] Tools/FitGen: Fix microcode alignment support Date: Thu, 17 Sep 2020 13:58:27 +0800 Message-Id: <20200917055827.11088-1-aaron.li@intel.com> X-Mailer: git-send-email 2.23.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2971 This patch is to fix a issue that "-A" option would only support 2^n Byte alignment of microcode. Signed-off-by: Aaron Li Cc: Bob Feng Cc: Liming Gao --- Silicon/Intel/Tools/FitGen/FitGen.c | 2 +- Silicon/Intel/Tools/FitGen/FitGen.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c b/Silicon/Intel/Tools/FitG= en/FitGen.c index c4006e69c822..4caaf70ee018 100644 --- a/Silicon/Intel/Tools/FitGen/FitGen.c +++ b/Silicon/Intel/Tools/FitGen/FitGen.c @@ -1176,7 +1176,7 @@ Returns: // MCU might be put at 2KB alignment, if so, we need to ad= just the size as 2KB alignment.=0D //=0D if (gFitTableContext.MicrocodeIsAligned) {=0D - MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32) + (= gFitTableContext.MicrocodeAlignValue - 1)) & ~(gFitTableContext.MicrocodeAl= ignValue - 1);=0D + MicrocodeSize =3D ROUNDUP (*(UINT32 *)(MicrocodeBuffer += 32), gFitTableContext.MicrocodeAlignValue);=0D } else {=0D MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32));=0D }=0D diff --git a/Silicon/Intel/Tools/FitGen/FitGen.h b/Silicon/Intel/Tools/FitG= en/FitGen.h index abad2d8799c8..435fc26209da 100644 --- a/Silicon/Intel/Tools/FitGen/FitGen.h +++ b/Silicon/Intel/Tools/FitGen/FitGen.h @@ -31,7 +31,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // Utility version information=0D //=0D #define UTILITY_MAJOR_VERSION 0=0D -#define UTILITY_MINOR_VERSION 62=0D +#define UTILITY_MINOR_VERSION 63=0D #define UTILITY_DATE __DATE__=0D =0D //=0D @@ -45,4 +45,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent (ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((A= lignment) - 1))=0D ;=0D =0D +#define ROUNDUP(Size, Alignment) (((Size) + (Alignment) - 1) / (Alignment)= * (Alignment))=0D +=0D #endif=0D --=20 2.23.0.windows.1