From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from EUR04-VI1-obe.outbound.protection.outlook.com (EUR04-VI1-obe.outbound.protection.outlook.com [40.107.8.70]) by mx.groups.io with SMTP id smtpd.web10.9593.1602064485451932316 for ; Wed, 07 Oct 2020 02:54:46 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=Ri8/yB7e; spf=pass (domain: arm.com, ip: 40.107.8.70, mailfrom: sami.mujawar@arm.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3ZqQoYzqNEbUZ480EUHPq9JWR0eKKtXhzEr/mv/7CUM=; b=Ri8/yB7eIEA0U/+/h22/bdhWp1xyYDCjH1zldPnTx7R+WlTLG/baqpwEHcRCwRs2qikACs6TKFVderpWqquabSGNcoCAThgFwwNuEZurjKV7PhLHDBZsRtOhGwoGZneNqFzK75G8mjDGMTJ7QUlh2/UXZSaJmJHdUUwCrE47Iik= Received: from DB6PR07CA0168.eurprd07.prod.outlook.com (2603:10a6:6:43::22) by DBBPR08MB4267.eurprd08.prod.outlook.com (2603:10a6:10:cb::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3433.38; Wed, 7 Oct 2020 09:54:36 +0000 Received: from DB5EUR03FT046.eop-EUR03.prod.protection.outlook.com (2603:10a6:6:43:cafe::c4) by DB6PR07CA0168.outlook.office365.com (2603:10a6:6:43::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.11 via Frontend Transport; Wed, 7 Oct 2020 09:54:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; edk2.groups.io; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;edk2.groups.io; dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DB5EUR03FT046.mail.protection.outlook.com (10.152.21.230) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3433.34 via Frontend Transport; Wed, 7 Oct 2020 09:54:36 +0000 Received: ("Tessian outbound 7161e0c2a082:v64"); Wed, 07 Oct 2020 09:54:36 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 8052a334cbd0b565 X-CR-MTA-TID: 64aa7808 Received: from a43b534f4f66.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 0D3E4DBA-6361-4449-BAE7-2FFE259C3A4D.1; Wed, 07 Oct 2020 09:54:22 +0000 Received: from EUR04-DB3-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id a43b534f4f66.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Wed, 07 Oct 2020 09:54:22 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lPtITpDj6SWUsH8ZEVwgxAMn1rD3vvPqPjCo00UenlQuYyop4WU4Dg6qnp4yyBh0jjX8Rk4Gw+w875HzTPjnyB2wEzT0AZgF3bu5fHMkoH2iQj7hz7P1f9DUDjlJ6PhrwSjHmajmrfoSA58SprousXvN1zinlK4yg9CaCL8zIYRlu+TWc+c8zcCPuuuImiKb2FaixIijDjQ3gqNBHPBmiNrWLH3BdV52uqQ4riujhFD+b9DKzcgnexQWU/ZbjiGtCsJO0wVJzeLYCIH/N8SpFjf2MX+TlnVxc/x0VhVamSZ3UWhsWGRSruZBgX+ecErLV828zoykW2LH40VXM+RnHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3ZqQoYzqNEbUZ480EUHPq9JWR0eKKtXhzEr/mv/7CUM=; b=OpkNkAy47shQ/Jr6emsgW9uVm/KJVzbUaS3r/4cpm13xNgvY3LgOYg8LJO/4uRlq+tZeDl0c7X4y/Q+WJhWkPq0NFWloi+jIBAvZjJI5zyC0WuI48UdXW17PdEu2PWQ+zSkpbZ+KRpGYpDYZXMURuAW8aSRcLSwKUoSGIG7ghMVMHOYkSugZd7CsxtF/eg3n317JzJEKi+FwblTWli0eN82a1snNc6SvuNDbTplJf7QeWfOMBVJyeW7QK+7+nhxH8GaI5v8U/8TFxdi5SitDWSGwJ/+GxGcoa4RvhLtcrO+4SAtPd+3Ygv3Pf2wPfNYMcYzGjvkgY4yJYRjqyEaEwA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=edk2.groups.io smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3ZqQoYzqNEbUZ480EUHPq9JWR0eKKtXhzEr/mv/7CUM=; b=Ri8/yB7eIEA0U/+/h22/bdhWp1xyYDCjH1zldPnTx7R+WlTLG/baqpwEHcRCwRs2qikACs6TKFVderpWqquabSGNcoCAThgFwwNuEZurjKV7PhLHDBZsRtOhGwoGZneNqFzK75G8mjDGMTJ7QUlh2/UXZSaJmJHdUUwCrE47Iik= Received: from AM6PR04CA0016.eurprd04.prod.outlook.com (2603:10a6:20b:92::29) by VE1PR08MB5696.eurprd08.prod.outlook.com (2603:10a6:800:1ae::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3433.37; Wed, 7 Oct 2020 09:54:20 +0000 Received: from AM5EUR03FT055.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:92:cafe::28) by AM6PR04CA0016.outlook.office365.com (2603:10a6:20b:92::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3455.22 via Frontend Transport; Wed, 7 Oct 2020 09:54:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; edk2.groups.io; dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; Received: from nebula.arm.com (40.67.248.234) by AM5EUR03FT055.mail.protection.outlook.com (10.152.17.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3433.34 via Frontend Transport; Wed, 7 Oct 2020 09:54:19 +0000 Received: from AZ-NEU-EX01.Emea.Arm.com (10.251.26.4) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2044.4; Wed, 7 Oct 2020 09:54:17 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX01.Emea.Arm.com (10.251.26.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1779.2; Wed, 7 Oct 2020 09:54:17 +0000 Received: from E107187.Arm.com (10.57.12.2) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2044.4 via Frontend Transport; Wed, 7 Oct 2020 09:54:15 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , , , Subject: [PATCH v1 1/2] MdePkg/IndustryStandard: AEST Table definition Date: Wed, 7 Oct 2020 10:54:13 +0100 Message-ID: <20201007095414.16552-2-sami.mujawar@arm.com> X-Mailer: git-send-email 2.11.0.windows.3 In-Reply-To: <20201007095414.16552-1-sami.mujawar@arm.com> References: <20201007095414.16552-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e0bc7ea4-71d2-4752-5e72-08d86aa70021 X-MS-TrafficTypeDiagnostic: VE1PR08MB5696:|DBBPR08MB4267: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:8882;OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: xT2rEz9DbXrR7Rh8Z5HliyCrupPjWybQqbO6CtEUfOJOgDmZbQa1DOH6VhHRhuRp7YKUuu8qF0dRmYWywCJhlNwIEj81iekLcb1tNylMCmj84XLEVmhv/CRFIix+fpnD58f3DQUUv8C/BwJL8GfJgx3iJwuZeZ3xNp4TUs8+KlNmOce60EoJZwcZjaAdDcRPJeenEgG611c3WWejgry5Ivf4x2PzjHoSjLrWqIf3CydlUIlcpCRluceXmF0ujMAd+e0WYMLyJSstE+Frlpv1GJXH1NcsdQ6N+5GqvZbYbAQ84i7py+M9ndmbLNzQ+qbZeV24sHYIysA+7RNR9UrgKHFjjOeHxXKsQlEUfEJPEh/sAF3bJEIBDUW7kn/G85wXYMFQ/dlHAqk/Yt902nGPPUizt3l6M7XwogPZHvKJUTTQlfxPnv2UZupotFxkgm8Bn/4Rx36jKBlJFJOoGo8TH3ytDJfeE0u/czboscQKOl0= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(346002)(136003)(396003)(39850400004)(376002)(46966005)(47076004)(81166007)(2616005)(83080400001)(19627235002)(44832011)(8676002)(478600001)(2906002)(8936002)(86362001)(83380400001)(36756003)(356005)(7696005)(4326008)(5660300002)(54906003)(426003)(70586007)(316002)(186003)(26005)(82310400003)(70206006)(6916009)(82740400003)(30864003)(336012)(1076003);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB5696 Return-Path: Sami.Mujawar@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5EUR03FT046.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 7e86081f-e136-4088-a470-08d86aa6f604 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uqqEdFWKwDzMZHMS0WRvR+8k5Akf4v2ePq3eJu0DvztycI2NQjDn8Bv6zFxpZfbQEl56Z2VJOQNaA6ox3cE2OJbsCuloCu8RUx+0xH7xgWsDnR1lpDgsAaY3y65nF1ofRuAIt0f0NWi15ro6Ydvv1TvJOZpiS3AbPE4kzzlIHl/6ysDVW/EfeVZdIaHxeoKNr3Uxn7mkRK6xBQ7rT1t7wSGaHYh8YF+flh9CXE1vC6oeJJNsItb2ITCssHEQCFwbxOn/YzqP5lLh1gV3bn+rwhb5piGkc6ccz6McgVp0HfjvaODpy9Ahz76rPIS43UCt6PJH4ZybYjsK9V009AvyKjgY3tLnYlOUV6aO9TGP/CkYN2wexWTW6KDNFhX5s2H3Bz84z4GSPtGboxGRS0ZmSXc57HW+bk4M2/W51kPf8wVLlBELRI07uAmSortZNWtNwEz3bpW1Iv5lavNGSa590/tRoDlK/a7ohofhkDdnQsM= X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(4636009)(39850400004)(396003)(376002)(346002)(136003)(46966005)(86362001)(30864003)(4326008)(316002)(83080400001)(81166007)(82310400003)(44832011)(1076003)(186003)(2616005)(19627235002)(54906003)(478600001)(26005)(83380400001)(336012)(426003)(7696005)(2906002)(8676002)(47076004)(36756003)(82740400003)(70586007)(5660300002)(6916009)(70206006)(8936002);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2020 09:54:36.7114 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0bc7ea4-71d2-4752-5e72-08d86aa70021 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT046.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB4267 Content-Type: text/plain From: Marc Moisson-Franckhauser Add definition for the Arm Error Source Table (AEST) described in the ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document, dated 28 September 2020. (https://developer.arm.com/documentation/den0085/0101/) Signed-off-by: Marc Moisson-Franckhauser Signed-off-by: Sami Mujawar --- MdePkg/Include/IndustryStandard/Acpi63.h | 7 +- MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h | 366 ++++++++++++++++++++ 2 files changed, 372 insertions(+), 1 deletion(-) diff --git a/MdePkg/Include/IndustryStandard/Acpi63.h b/MdePkg/Include/IndustryStandard/Acpi63.h index b281b30155e90eba5169dc39bde9a3379e3b7005..238cbb19618e025685b748aff18f5706a12f999a 100644 --- a/MdePkg/Include/IndustryStandard/Acpi63.h +++ b/MdePkg/Include/IndustryStandard/Acpi63.h @@ -2,7 +2,7 @@ ACPI 6.3 definitions from the ACPI Specification Revision 6.3 Jan, 2019. Copyright (c) 2017, Intel Corporation. All rights reserved.
- Copyright (c) 2019 - 2020, ARM Ltd. All rights reserved.
+ Copyright (c) 2019 - 2020, Arm Ltd. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -2646,6 +2646,11 @@ typedef struct { #define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') /// +/// "AEST" Arm Error Source Table +/// +#define EFI_ACPI_6_3_ARM_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('A', 'E', 'S', 'T') + +/// /// "APIC" Multiple APIC Description Table /// #define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'I', 'C') diff --git a/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h b/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h new file mode 100644 index 0000000000000000000000000000000000000000..9bd7db5a358e24b7149132feace6de0d7e5d3d74 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h @@ -0,0 +1,366 @@ +/** @file + Arm Error Source Table as described in the + 'ACPI for the Armv8 RAS Extensions 1.1' Specification. + + Copyright (c) 2020 Arm Limited. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Reference(s): + - ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document, + dated 28 September 2020. + (https://developer.arm.com/documentation/den0085/0101/) + + @par Glossary + - Ref : Reference + - Id : Identifier +**/ + +#ifndef ARM_ERROR_SOURCE_TABLE_H_ +#define ARM_ERROR_SOURCE_TABLE_H_ + +#define EFI_ACPI_ARM_ERROR_SOURCE_TABLE_REVISION 1 + +#pragma pack(1) + +/** + Arm Error Source Table definition. +*/ +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_ARM_ERROR_SOURCE_TABLE; + +/** + AEST Node structure. +*/ +typedef struct { + /** Node type: + 0x00 - Processor error node + 0x01 - Memory error node + 0x02 - SMMU error node + 0x03 - Vendor-defined error node + 0x04 - GIC error node + */ + UINT8 Type; + + /// Length of structure in bytes. + UINT16 Length; + + /// Reserved - Must be zero. + UINT8 Reserved; + + /// Offset from the start of the node to node-specific data. + UINT32 DataOffset; + + /// Offset from the start of the node to the node interface structure. + UINT32 InterfaceOffset; + + /// Offset from the start of the node to node interrupt array. + UINT32 InterruptArrayOffset; + + /// Number of entries in the interrupt array. + UINT32 InterruptArrayCount; + + // Generic node data + + /// The timestamp frequency of the counter in Hz. + UINT64 TimestampRate; + + /// Reserved - Must be zero. + UINT64 Reserved1; + + /// The rate in Hz at which the Error Generation Counter decrements. + UINT64 ErrorInjectionCountdownRate; +} EFI_ACPI_AEST_NODE_STRUCT; + +// AEST Node type definitions +#define EFI_ACPI_AEST_NODE_TYPE_PROCESSOR 0x0 +#define EFI_ACPI_AEST_NODE_TYPE_MEMORY 0x1 +#define EFI_ACPI_AEST_NODE_TYPE_SMMU 0x2 +#define EFI_ACPI_AEST_NODE_TYPE_VENDOR_DEFINED 0x3 +#define EFI_ACPI_AEST_NODE_TYPE_GIC 0x4 + +/** + AEST Node Interface structure. +*/ +typedef struct { + /** Interface type: + 0x0 - System register (SR) + 0x1 - Memory mapped (MMIO) + */ + UINT8 Type; + + /// Reserved - Must be zero. + UINT8 Reserved[3]; + + /// AEST node interface flags. + UINT32 Flags; + + /// Base address of error group that contains the error node. + UINT64 BaseAddress; + + /** Zero-based index of the first standard error record that + belongs to this node. + */ + UINT32 StartErrorRecordIndex; + + /** Number of error records in this node including both + implemented and unimplemented records. + */ + UINT32 NumberErrorRecords; + + /** A bitmap indicating the error records within this + node that are implemented in the current system. + */ + UINT64 ErrorRecordImplemented; + + /** A bitmap indicating the error records within this node that + support error status reporting through the ERRGSR register. + */ + UINT64 ErrorRecordStatusReportingSupported; + + /** A bitmap indicating the addressing mode used by each error + record within this node to populate the ERR_ADDR register. + */ + UINT64 AddressingMode; +} EFI_ACPI_AEST_INTERFACE_STRUCT; + +// AEST Interface node type definitions. +#define EFI_ACPI_AEST_INTERFACE_TYPE_SR 0x0 +#define EFI_ACPI_AEST_INTERFACE_TYPE_MMIO 0x1 + +// AEST node interface flag definitions. +#define EFI_ACPI_AEST_INTERFACE_FLAG_PRIVATE 0 +#define EFI_ACPI_AEST_INTERFACE_FLAG_SHARED BIT0 +#define EFI_ACPI_AEST_INTERFACE_FLAG_CLEAR_MISCX BIT1 + +/** + AEST Node Interrupt structure. +*/ +typedef struct { + /** Interrupt type: + 0x0 - Fault Handling Interrupt + 0x1 - Error Recovery Interrupt + */ + UINT8 InterruptType; + + /// Reserved - Must be zero. + UINT8 Reserved[2]; + + /** Interrupt flags + Bits [31:1]: Must be zero. + Bit 0: + 0b - Interrupt is edge-triggered + 1b - Interrupt is level-triggered + */ + UINT8 InterruptFlags; + + /// GSIV of interrupt, if interrupt is an SPI or a PPI. + UINT32 InterruptGsiv; + + /** If MSI is supported, then this field must be set to the + Identifier field of the IORT ITS Group node. + */ + UINT8 ItsGroupRefId; + + /// Reserved - must be zero. + UINT8 Reserved1[3]; +} EFI_ACPI_AEST_INTERRUPT_STRUCT; + +// AEST Interrupt node - interrupt type defintions. +#define EFI_ACPI_AEST_INTERRUPT_TYPE_FAULT_HANDLING 0x0 +#define EFI_ACPI_AEST_INTERRUPT_TYPE_ERROR_RECOVERY 0x1 + +// AEST Interrupt node - interrupt flag defintions. +#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_EDGE 0 +#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_LEVEL BIT0 + +/** + Cache Processor Resource structure. +*/ +typedef struct { + /// Reference to the cache structure in the PPTT table. + UINT32 CacheRefId; + + /// Reserved + UINT32 Reserved; +} EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT; + +/** + TLB Processor Resource structure. +*/ +typedef struct { + /// TLB level from perspective of current processor. + UINT32 TlbRefId; + + /// Reserved + UINT32 Reserved; +} EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT; + +/** + Processor Generic Resource structure. +*/ +typedef struct { + /// Vendor-defined supplementary data. + UINT32 Data; +} EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT; + +/** + AEST Processor Resource union. +*/ +typedef union { + /// Processor Cache resource. + EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT Cache; + + /// Processor TLB resource. + EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT Tlb; + + /// Processor Generic resource. + EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT Generic; +} EFI_ACPI_AEST_PROCESSOR_RESOURCE; + +/** + AEST Processor structure. +*/ +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// Processor ID of node. + UINT32 AcpiProcessorId; + + /** Resource type of the processor node. + 0x0 - Cache + 0x1 - TLB + 0x2 - Generic + */ + UINT8 ResourceType; + + /// Reserved - must be zero. + UINT8 Reserved; + + /// Processor structure flags. + UINT8 Flags; + + /// Processor structure revision. + UINT8 Revision; + + /** Processor affinity descriptor for the resource that this + error node pertains to. + */ + UINT64 ProcessorAffinityLevelIndicator; + + /// Processor resource + EFI_ACPI_AEST_PROCESSOR_RESOURCE Resource; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_PROCESSOR_STRUCT; + +// AEST Processor resource type definitions. +#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_CACHE 0x0 +#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_TLB 0x1 +#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_GENERIC 0x2 + +// AEST Processor flag definitions. +#define EFI_ACPI_AEST_PROCESSOR_FLAG_GLOBAL BIT0 +#define EFI_ACPI_AEST_PROCESSOR_FLAG_SHARED BIT1 + +/** + Memory Controller structure. +*/ +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// SRAT proximity domain. + UINT32 ProximityDomain; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_MEMORY_CONTROLLER_STRUCT; + +/** + SMMU structure. +*/ +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// Reference to the IORT table node that describes this SMMU. + UINT32 SmmuRefId; + + /** Reference to the IORT table node that is associated with the + sub-component within this SMMU. + */ + UINT32 SubComponentRefId; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_SMMU_STRUCT; + +/** + Vendor-Defined structure. +*/ +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// ACPI HID of the component. + UINT32 HardwareId; + + /// The ACPI Unique identifier of the component. + UINT32 UniqueId; + + /// Vendor-specific data, for example to identify this error source. + UINT8 VendorData[16]; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_VENDOR_DEFINED_STRUCT; + +/** + GIC structure. +*/ +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /** Type of GIC interface that is associated with this error node. + 0x0 - GIC CPU (GICC) + 0x1 - GIC Distributor (GICD) + 0x2 - GIC Resistributor (GICR) + 0x3 - GIC ITS (GITS) + */ + UINT32 InterfaceType; + + /// Identifier for the interface instance. + UINT32 GicInterfaceRefId; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_GIC_STRUCT; + +// AEST GIC interface type definitions. +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICC 0x0 +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICD 0x1 +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICR 0x2 +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GITS 0x3 + +#pragma pack() + +#endif // ARM_ERROR_SOURCE_TABLE_H_ -- 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'