From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ot1-f97.google.com (mail-ot1-f97.google.com [209.85.210.97]) by mx.groups.io with SMTP id smtpd.web11.7587.1602146834146103748 for ; Thu, 08 Oct 2020 01:47:14 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@broadcom.com header.s=google header.b=VrnlZxP+; spf=permerror, err=parse error for token &{10 18 %{i}._ip.%{h}._ehlo.%{d}._spf.vali.email}: invalid domain name (domain: broadcom.com, ip: 209.85.210.97, mailfrom: rajesh.ravi@broadcom.com) Received: by mail-ot1-f97.google.com with SMTP id f10so4814118otb.6 for ; Thu, 08 Oct 2020 01:47:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A4koLwz2HmBBIrsKOBWpLwOyDS/1u5BrjF14tGbbPcM=; b=VrnlZxP+WUlYsi2Dld+aYVNsxC4xqIrOY/JrYowNNna8KQQb0XbVRiPzm0YNZHkBeI uw+6WnAFpMomEvsb0eCobgiqpxoV0sOoRcseBcqt331yYxO+mCx+KmxVfgkpxs2u1eGb h6H8TfsDigpB53TYDRT7K8bR0EIyo2rYmSiJY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A4koLwz2HmBBIrsKOBWpLwOyDS/1u5BrjF14tGbbPcM=; b=j1CG2OpvFm5eECOb/vw04cEH9FDfK9ebuoDB/JiCD24BGDIJzCfUQw1wjsqHkgVCUJ BN2oxcXR9/sBQMHAeQ+usYpUHm2DFztpBkDqz9JYTfACrS7v1a9cLEcpUucs01jTK924 tllFabSZ38Vsltzhg+jyCPrmf+2w/mm6p+ATvnS691GDuiT0Qj063WQHrbmu8LGqcsty xoQM1X8XgRgkt4Fo4FnFJHS7Gh68Ttu2nirMBXQris4AZUGfR0vg2z2PyZ92gu7V1iOl ZCthR82qfIw7rheHBjZk8Vmnu/4DXQ5LVm7OYVNXobT4OeTDF74d2F8p2aQaQbAfzT72 kCTA== X-Gm-Message-State: AOAM5330i/cqIJnJZO7pUN/Pcnc2NEpbgqy+jqvbr8RX9gwSvQdP2EoC +bfdNmBqYPdFXztMDvbQN8IqawGjKhlnzuBvvuDRevqJx6U0Ncmasar08QY4lBP5viapSsf8G2R 1Yccswmx14OEPd0JL28DR+1xM9s0dGeEcR/ePIIi09gpdB8LF+kzl7tsHnWHPI/BtgDMMheD9yA Ik6gYPri4k4A== X-Google-Smtp-Source: ABdhPJzu+sKUwrhxWesn9vpsnbtklEM061J/vyviqXjEx7Ac/2GICMeUD4mg8KOTUx5SP+Y2jLiq9X3A+aPp X-Received: by 2002:a9d:6959:: with SMTP id p25mr4116520oto.96.1602146833099; Thu, 08 Oct 2020 01:47:13 -0700 (PDT) Return-Path: Received: from rbuild18.dhcp.broadcom.net ([192.19.234.250]) by smtp-relay.gmail.com with ESMTPS id r19sm681361ooj.9.2020.10.08.01.47.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Oct 2020 01:47:13 -0700 (PDT) X-Relaying-Domain: broadcom.com From: rajesh.ravi@broadcom.com To: devel@edk2.groups.io Cc: Rajesh Ravi , Leif Lindholm , Ard Biesheuvel Subject: [PATCH v1 1/1] ArmPkg/GenericWatchdogDxe: Add rev 1 support to ARM Generic Watchdog driver Date: Thu, 8 Oct 2020 14:16:36 +0530 Message-Id: <20201008084636.14782-2-rajesh.ravi@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201008084636.14782-1-rajesh.ravi@broadcom.com> References: <20201008084636.14782-1-rajesh.ravi@broadcom.com> From: Rajesh Ravi Add SBSA watchdog rev 1 support to ARM Generic Watchdog driver. Signed-off-by: Rajesh Ravi Cc: Leif Lindholm Cc: Ard Biesheuvel --- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h | 8 ++- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 53 ++++++++++++++++++-- 2 files changed, 56 insertions(+), 5 deletions(-) diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h index c64bc5c4627d..ed74bcf95021 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h @@ -13,12 +13,18 @@ // Control Frame: #define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000) -#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008) +#define GENERIC_WDOG_OFFSET_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008) +#define GENERIC_WDOG_OFFSET_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x00C) #define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010) #define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014) +#define GENERIC_WDOG_IIDR_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0xFCC) // Values of bit 0 of the Control/Status Register #define GENERIC_WDOG_ENABLED 1 #define GENERIC_WDOG_DISABLED 0 +#define GENERIC_WDOG_ARCH_REV_OFFSET 16 +#define GENERIC_WDOG_ARCH_REV_MASK 0xF +#define SBSA_WDOG_WOR_WIDTH 48 +#define MAX_OFFSET_REG_VAL (((UINT64)1 << 48) - 1) #endif // __GENERIC_WATCHDOG_H__ diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c index f79cc9170f8a..7ef9b1ff08ab 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c @@ -35,16 +35,53 @@ STATIC UINTN mTimerFrequencyHz = 0; It is therefore stored here. 0 means the timer is not running. */ STATIC UINT64 mNumTimerTicks = 0; +STATIC UINT32 mWatchDogRev = 0; + +STATIC UINT64 mWatchdogMaxOffsetVal = MAX_UINT32; + STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol; STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify; +STATIC +inline +UINT32 +WatchdogReadRevisionRegister ( + VOID + ) +{ + return MmioRead32 (GENERIC_WDOG_IIDR_REG); +} + +STATIC +inline +UINT32 +WatchdogGetRevision ( + VOID + ) +{ + UINT32 IidrRegVal; + + IidrRegVal = WatchdogReadRevisionRegister(); + + return ((IidrRegVal >> GENERIC_WDOG_ARCH_REV_OFFSET) & GENERIC_WDOG_ARCH_REV_MASK); +} + STATIC VOID WatchdogWriteOffsetRegister ( - UINT32 Value + UINT64 Value ) { - MmioWrite32 (GENERIC_WDOG_OFFSET_REG, Value); + if(Value >> SBSA_WDOG_WOR_WIDTH) { + return; + } + + MmioWrite32 (GENERIC_WDOG_OFFSET_REG_LOW, ((UINT32)Value & MAX_UINT32)); + if (mWatchDogRev) { + MmioWrite32 (GENERIC_WDOG_OFFSET_REG_HIGH, (Value >> 32) & MAX_UINT32); + } else { + MmioWrite32 (GENERIC_WDOG_OFFSET_REG_HIGH, 0); + } } STATIC @@ -207,12 +244,12 @@ WatchdogSetTimerPeriod ( /* If the number of required ticks is greater than the max the watchdog's offset register (WOR) can hold, we need to manually compute and set the compare register (WCV) */ - if (mNumTimerTicks > MAX_UINT32) { + if (mNumTimerTicks > mWatchdogMaxOffsetVal) { /* We need to enable the watchdog *before* writing to the compare register, because enabling the watchdog causes an "explicit refresh", which clobbers the compare register (WCV). In order to make sure this doesn't trigger an interrupt, set the offset to max. */ - WatchdogWriteOffsetRegister (MAX_UINT32); + WatchdogWriteOffsetRegister (MAX_OFFSET_REG_VAL); WatchdogEnable (); SystemCount = ArmGenericTimerGetSystemCount (); WatchdogWriteCompareRegister (SystemCount + mNumTimerTicks); @@ -319,6 +356,14 @@ GenericWatchdogEntry ( mTimerFrequencyHz = ArmGenericTimerGetTimerFreq (); ASSERT (mTimerFrequencyHz != 0); + mWatchDogRev = WatchdogGetRevision(); + + if (mWatchDogRev) { + mWatchdogMaxOffsetVal = MAX_OFFSET_REG_VAL; + } else { + mWatchdogMaxOffsetVal = MAX_UINT32; + } + // Install interrupt handler Status = mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol, FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), -- 2.17.1