public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: "Leif Lindholm" <leif@nuviainc.com>
To: Meenakshi Aggarwal <meenakshi.aggarwal@oss.nxp.com>
Cc: ard.biesheuvel@arm.com, michael.d.kinney@intel.com,
	devel@edk2.groups.io, v.sethi@nxp.com,
	Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Subject: Re: [edk2-platforms v2 1/6] Silicon/NXP: Add GPIO Library support.
Date: Thu, 8 Oct 2020 13:10:32 +0100	[thread overview]
Message-ID: <20201008121032.GX5623@vanye> (raw)
In-Reply-To: <1602087041-8009-2-git-send-email-meenakshi.aggarwal@oss.nxp.com>

On Wed, Oct 07, 2020 at 21:40:36 +0530, Meenakshi Aggarwal wrote:
> General-purpose I/O (GPIO) module is integrated on chip.
> 
> In general, the GPIO module supports up to 32 general-purpose
> I/O ports. Each port can be configured as an input or as an
> output. However, some implementations may restrict specific ports to
> input-only, output-only, or reserved (unimplemented).
> 
> Co-authored-by: Pramod Kumar <pramod.kumar_1@nxp.com>
> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>

Reviewed-by: Leif Lindholm <leif@nuviainc.com>

> ---
>  Silicon/NXP/Library/GpioLib/GpioLib.inf |  39 ++++++
>  Silicon/NXP/Include/Library/GpioLib.h   | 110 ++++++++++++++++
>  Silicon/NXP/Library/GpioLib/GpioLib.c   | 219 ++++++++++++++++++++++++++++++++
>  3 files changed, 368 insertions(+)
>  create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.inf
>  create mode 100644 Silicon/NXP/Include/Library/GpioLib.h
>  create mode 100644 Silicon/NXP/Library/GpioLib/GpioLib.c
> 
> diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.inf b/Silicon/NXP/Library/GpioLib/GpioLib.inf
> new file mode 100644
> index 000000000000..0c11a5f00a12
> --- /dev/null
> +++ b/Silicon/NXP/Library/GpioLib/GpioLib.inf
> @@ -0,0 +1,39 @@
> +/** @file
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +[Defines]
> +  INF_VERSION                    = 0x0001001A
> +  BASE_NAME                      = GpioLib
> +  FILE_GUID                      = addec2b8-d2e0-43c0-a277-41a8d42f3f4f
> +  MODULE_TYPE                    = BASE
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = GpioLib
> +
> +[Sources.common]
> +  GpioLib.c
> +
> +[LibraryClasses]
> +  ArmLib
> +  BaseLib
> +  BaseMemoryLib
> +  IoAccessLib
> +  IoLib
> +
> +[Packages]
> +  ArmPlatformPkg/ArmPlatformPkg.dec
> +  EmbeddedPkg/EmbeddedPkg.dec
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  Silicon/NXP/NxpQoriqLs.dec
> +
> +[Pcd]
> +  gNxpQoriqLsTokenSpaceGuid.PcdNumGpioController
> +  gNxpQoriqLsTokenSpaceGuid.PcdGpioModuleBaseAddress
> +  gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerOffset
> +
> +[FeaturePcd]
> +  gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian
> diff --git a/Silicon/NXP/Include/Library/GpioLib.h b/Silicon/NXP/Include/Library/GpioLib.h
> new file mode 100644
> index 000000000000..0345aa66de7e
> --- /dev/null
> +++ b/Silicon/NXP/Include/Library/GpioLib.h
> @@ -0,0 +1,110 @@
> +/** @file
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef GPIO_H__
> +#define GPIO_H__
> +
> +#include <Uefi.h>
> +
> +/* enum for GPIO number */
> +typedef enum _GPIO_BLOCK {
> +  GPIO1,
> +  GPIO2,
> +  GPIO3,
> +  GPIO4,
> +  GPIO_MAX
> +} GPIO_BLOCK;
> +
> +/* enum for GPIO direction */
> +typedef enum _GPIO_DIRECTION {
> +  INPUT,
> +  OUTPUT
> +} GPIO_DIRECTION;
> +
> +/* enum for GPIO state */
> +typedef enum _GPIO_STATE {
> +  LOW,
> +  HIGH
> +} GPIO_VAL;
> +
> +/**
> +   GpioSetDiriection: Set GPIO direction as INPUT or OUTPUT
> +
> +   @param[in] Id  GPIO controller number
> +   @param[in] Bit GPIO number
> +   @param[in] Dir GPIO Direction as INPUT or OUTPUT
> +
> +   @retval EFI_SUCCESS
> + **/
> +EFI_STATUS
> +GpioSetDirection (
> +  IN  UINT8    Id,
> +  IN  UINT32   Bit,
> +  IN  BOOLEAN  Dir
> +  );
> +
> +/**
> +   GpioGetDirection:  Retrieve GPIO direction
> +
> +   @param[in] Id  GPIO controller number
> +   @param[in] Bit GPIO number
> +
> +   @retval GPIO Direction as INPUT or OUTPUT
> + **/
> +UINT32
> +GpioGetDirection (
> +  IN  UINT8    Id,
> +  IN  UINT32   Bit
> +  );
> +
> + /**
> +   GpioGetData:  Retrieve GPIO Value
> +
> +   @param[in] Id  GPIO controller number
> +   @param[in] Bit GPIO number
> +
> +   @retval GPIO value  as HIGH or LOW
> + **/
> +UINT32
> +GpioGetData (
> +  IN  UINT8    Id,
> +  IN  UINT32   Bit
> +  );
> +
> +/**
> +   GpioSetData:  Set GPIO data Value
> +
> +   @param[in] Id  GPIO controller number
> +   @param[in] Bit GPIO number
> +   @param[in] Data GPIO data value to set
> +
> +   @retval GPIO value  as HIGH or LOW
> + **/
> +EFI_STATUS
> +GpioSetData (
> +  IN  UINT8    Id,
> +  IN  UINT32   Bit,
> +  IN  BOOLEAN  Data
> +  );
> +
> +/**
> +   GpioSetOpenDrain:  Set GPIO as Open drain
> +
> +   @param[in] Id  GPIO controller number
> +   @param[in] Bit GPIO number
> +   @param[in] OpenDrain Set as open drain
> +
> +   @retval EFI_SUCCESS
> + **/
> +EFI_STATUS
> +GpioSetOpenDrain (
> +  IN  UINT8    Id,
> +  IN  UINT32   Bit,
> +  IN  BOOLEAN  OpenDrain
> +  );
> +
> +#endif
> diff --git a/Silicon/NXP/Library/GpioLib/GpioLib.c b/Silicon/NXP/Library/GpioLib/GpioLib.c
> new file mode 100644
> index 000000000000..9dd48b812a82
> --- /dev/null
> +++ b/Silicon/NXP/Library/GpioLib/GpioLib.c
> @@ -0,0 +1,219 @@
> +/** @file
> +
> + GPIO controller Library inmplements the functions
> + which will be used by other library/drivers to
> + get/set GPIO pin direction and get/set data on
> + GPIO pins.
> +
> + Copyright 2020 NXP
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Library/GpioLib.h>
> +#include <Library/IoAccessLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +
> +STATIC MMIO_OPERATIONS *mGpioOps;
> +
> +/**
> +   Structure for GPIO Regsters
> +
> +   GpDir   GPIO direction register
> +   GpOdr   GPIO open drain register
> +   GpData  GPIO data register
> +   GpIer   GPIO interrupt event register
> +   GpImr   GPIO interrupt mask register
> +   GpIcr   GPIO interrupt control register
> +
> + **/
> +typedef struct GpioRegs {
> +  UINT32 GpDir;
> +  UINT32 GpOdr;
> +  UINT32 GpData;
> +  UINT32 GpIer;
> +  UINT32 GpImr;
> +  UINT32 GpIcr;
> +} GPIO_REGS;
> +
> +/**
> +   GetBaseAddr GPIO controller Base Address
> +
> +   @param[in] Id  GPIO controller number
> +
> +   @retval GPIO controller Base Address, if found
> +   @retval NULL, if not a valid controller number
> +
> + **/
> +STATIC
> +VOID *
> +GetBaseAddr (
> +  IN  UINT8  Id
> +  )
> +{
> +
> +  UINTN      GpioBaseAddr;
> +  UINTN      MaxGpioController;
> +
> +  mGpioOps = GetMmioOperations (FeaturePcdGet (PcdGpioControllerBigEndian));
> +
> +  MaxGpioController = PcdGet32 (PcdNumGpioController);
> +
> +  if (Id < MaxGpioController) {
> +    GpioBaseAddr = PcdGet64 (PcdGpioModuleBaseAddress) +
> +                     (Id * PcdGet64 (PcdGpioControllerOffset));
> +    return (VOID *)GpioBaseAddr;
> +  } else {
> +    DEBUG((DEBUG_ERROR, "Invalid Gpio Controller Id %d, Allowed Ids are %d-%d",
> +      Id, GPIO1, MaxGpioController));
> +      return NULL;
> +  }
> +}
> +
> +/**
> +   GpioSetDirection: Set GPIO direction as INPUT or OUTPUT
> +
> +   @param[in] Id  GPIO controller number
> +   @param[in] Bit GPIO number
> +   @param[in] Dir GPIO Direction as INPUT or OUTPUT
> +
> +   @retval EFI_SUCCESS
> + **/
> +EFI_STATUS
> +GpioSetDirection (
> +  IN  UINT8    Id,
> +  IN  UINT32   Bit,
> +  IN  BOOLEAN  Dir
> +  )
> +{
> +  GPIO_REGS    *Regs;
> +  UINT32       DirectionBitMask;
> +
> +  Regs = GetBaseAddr (Id);
> +  DirectionBitMask = 1 << Bit;
> +
> +  if (Dir) {
> +    mGpioOps->Or32 ((UINTN)&Regs->GpDir, DirectionBitMask);
> +  }
> +  else {
> +    mGpioOps->And32 ((UINTN)&Regs->GpDir, ~DirectionBitMask);
> +  }
> +
> +  return EFI_SUCCESS;
> +}
> +
> +/**
> +   GpioGetDiriection:  Retrieve GPIO direction
> +
> +   @param[in] Id  GPIO controller number
> +   @param[in] Bit GPIO number
> +
> +   @retval GPIO Direction as INPUT or OUTPUT
> + **/
> +UINT32
> +GpioGetDirection (
> +  IN  UINT8    Id,
> +  IN  UINT32   Bit
> +  )
> +{
> +  GPIO_REGS    *Regs;
> +  UINT32       Value;
> +  UINT32       DirectionBitMask;
> +
> +  Regs = GetBaseAddr (Id);
> +  DirectionBitMask = 1 << Bit;
> +
> +  Value = mGpioOps->Read32 ((UINTN)&Regs->GpDir);
> +
> +  return (Value & DirectionBitMask);
> +}
> +
> +/**
> +   GpioGetData:  Retrieve GPIO Value
> +
> +   @param[in] Id  GPIO controller number
> +   @param[in] Bit GPIO number
> +
> +   @retval GPIO value  as HIGH or LOW
> + **/
> +UINT32
> +GpioGetData (
> +  IN  UINT8    Id,
> +  IN  UINT32   Bit
> +  )
> +{
> +  GPIO_REGS    *Regs;
> +  UINT32       Value;
> +  UINT32       DataBitMask;
> +
> +  Regs = (VOID *)GetBaseAddr (Id);
> +  DataBitMask = 1 << Bit;
> +
> +  Value = mGpioOps->Read32 ((UINTN)&Regs->GpData);
> +
> +  return (Value & DataBitMask);
> +}
> +
> +/**
> +   GpioSetData:  Set GPIO data Value
> +
> +   @param[in] Id  GPIO controller number
> +   @param[in] Bit GPIO number
> +   @param[in] Data GPIO data value to set
> +
> +   @retval GPIO value  as HIGH or LOW
> + **/
> +EFI_STATUS
> +GpioSetData (
> +  IN  UINT8    Id,
> +  IN  UINT32   Bit,
> +  IN  BOOLEAN  Data
> +  )
> +{
> +  GPIO_REGS    *Regs;
> +  UINT32       DataBitMask;
> +
> +  Regs = GetBaseAddr (Id);
> +  DataBitMask = 1 << Bit;
> +
> +  if (Data) {
> +    mGpioOps->Or32 ((UINTN)&Regs->GpData, DataBitMask);
> +  } else {
> +    mGpioOps->And32 ((UINTN)&Regs->GpData, ~DataBitMask);
> +  }
> +
> +  return EFI_SUCCESS;
> +}
> +
> +/**
> +   GpioSetOpenDrain:  Set GPIO as Open drain
> +
> +   @param[in] Id  GPIO controller number
> +   @param[in] Bit GPIO number
> +   @param[in] OpenDrain Set as open drain
> +
> +   @retval EFI_SUCCESS
> + **/
> +EFI_STATUS
> +GpioSetOpenDrain (
> +  IN  UINT8    Id,
> +  IN  UINT32   Bit,
> +  IN  BOOLEAN  OpenDrain
> +  )
> +{
> +  GPIO_REGS    *Regs;
> +  UINT32       OpenDrainBitMask;
> +
> +  Regs = GetBaseAddr (Id);
> +  OpenDrainBitMask = 1 << Bit;
> +
> +  if (OpenDrain) {
> +    mGpioOps->Or32 ((UINTN)&Regs->GpOdr, OpenDrainBitMask);
> +  } else {
> +    mGpioOps->And32 ((UINTN)&Regs->GpOdr, ~OpenDrainBitMask);
> +  }
> +
> +  return EFI_SUCCESS;
> +}
> -- 
> 1.9.1
> 

  reply	other threads:[~2020-10-08 12:10 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-15 16:28 [edk2-platforms 0/4] Enable USB support on LS1046aFrwy board Meenakshi Aggarwal
2020-09-15 16:29 ` [edk2-platforms 1/4] Silicon/NXP: Add GPIO driver support Meenakshi Aggarwal
2020-09-25 11:12   ` Leif Lindholm
2020-09-15 16:29 ` [edk2-platforms 2/4] Platform/NXP/LS1046aFrwyPkg: GPIO mux changes for USB Meenakshi Aggarwal
2020-09-25 11:17   ` Leif Lindholm
2020-09-15 16:29 ` [edk2-platforms 3/4] Silicon/NXP: Implement USB Errata Meenakshi Aggarwal
2020-09-25 11:47   ` Leif Lindholm
2020-09-15 16:29 ` [edk2-platforms 4/4] LS1046aFrwy: Enable USB support for LS1046AFRWY board Meenakshi Aggarwal
2020-09-25 11:47   ` Leif Lindholm
2020-10-07 16:10 ` [edk2-platforms v2 0/6] Enable USB support on LS1046aFrwy board Meenakshi Aggarwal
2020-10-07 16:10   ` [edk2-platforms v2 1/6] Silicon/NXP: Add GPIO Library support Meenakshi Aggarwal
2020-10-08 12:10     ` Leif Lindholm [this message]
2020-10-07 16:10   ` [edk2-platforms v2 2/6] Platform/NXP/LS1046aFrwyPkg: MUX changes for USB Meenakshi Aggarwal
2020-10-08 12:13     ` Leif Lindholm
2020-10-07 16:10   ` [edk2-platforms v2 3/6] Silicon/NXP: Add SCFG support for Chassis2 Meenakshi Aggarwal
2020-10-08 12:15     ` Leif Lindholm
2020-10-07 16:10   ` [edk2-platforms v2 4/6] Silicon/NXP: Implement USB Errata Workarounds Meenakshi Aggarwal
2020-10-08 12:18     ` Leif Lindholm
2020-10-07 16:10   ` [edk2-platforms v2 5/6] Silicon/NXP/LS1046A: Apply USB errata workarounds Meenakshi Aggarwal
2020-10-08 12:05     ` Leif Lindholm
2020-10-07 16:10   ` [edk2-platforms v2 6/6] LS1046aFrwy: Enable USB support for LS1046AFRWY board Meenakshi Aggarwal
2020-10-09 15:19     ` [edk2-platforms v3 0/6] Enable USB support on LS1046aFrwy board Meenakshi Aggarwal
2020-10-09 15:19       ` [edk2-platforms v3 4/6] Silicon/NXP: Implement USB Errata Workarounds Meenakshi Aggarwal
2020-10-09 15:19       ` [edk2-platforms v3 5/6] Silicon/NXP/LS1046A: Apply USB errata workarounds Meenakshi Aggarwal
2020-10-09 16:02         ` Leif Lindholm
2020-10-09 15:19       ` [edk2-platforms v3 6/6] LS1046aFrwy: Enable USB support for LS1046AFRWY board Meenakshi Aggarwal
2020-10-09 16:04       ` [edk2-platforms v3 0/6] Enable USB support on LS1046aFrwy board Leif Lindholm
2020-10-08 12:20   ` [edk2-platforms v2 " Leif Lindholm

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201008121032.GX5623@vanye \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox