From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) by mx.groups.io with SMTP id smtpd.web10.10773.1602159356698528004 for ; Thu, 08 Oct 2020 05:15:57 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=aakPhfh0; spf=pass (domain: nuviainc.com, ip: 209.85.221.45, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f45.google.com with SMTP id i1so225097wro.1 for ; Thu, 08 Oct 2020 05:15:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=GJVNSiAT00YXqd5BxBWrZCYcbRtXmZDfc5vJgD2M7TI=; b=aakPhfh0zWCrohgFcSuPSe25hWo+8L9bs45Bj6IdxcmCY4eDefgpRqMnj47QABtlBo MLYUWD8Z3Dllo/VYXOErdvwNMfaH/bBhmSXGk9VRGeLEsyokf9IVF1i1AMKRBOLl968Y 8H2kCKhmEQq0E6lGgD0JUjU4IgT6fR2G2RWU8rEKo/3+8XT/kKaP00j1bv7I/BUcnffs YL0koYLpgVGfO9gIv873/dJQJlPia8vMOh444f4a87qBFdbg2ohMNqf6oq03neQOSRPK YSMcNKlWoR7luEDATl5TiAAnVHQSqGf6FDTv1K4nudnm+ROjGZFT5QFcs9r6+ZG8BxVJ C0oQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=GJVNSiAT00YXqd5BxBWrZCYcbRtXmZDfc5vJgD2M7TI=; b=BuSstSiAh8DUB0yMUme1jd5EIC6zMXC4ybuBIuv+2a6sZvanpccc2v2R5KzWrlMrk5 mFSMAWijMZF20KPkuw0jxqtoxWr14VTKf8/xorFkxqaDBaDry11qwFebyOMEkgg8DCpT 8hO+g2L+Sj7xmk0+y8ys7A3R7jMG5mstb6VdHOYHLauNY97bIQMkUIwclrACbmqjbpNA t9YXMUd6txCxtInp3Ij6vMVG687f2M6v85iTD4gMxCx7IxM+gGy05ZSIMdi4hm4CCImZ 0vNPQaFjGfvaOT6OvPjHK4XZnlML8WDjh17ygjHqXaarogXSi1AM89X9RxQftGr20TzH uqBw== X-Gm-Message-State: AOAM532Dy0HCXYnerytrPUPwtbgl0Ez75rwZNopuE7kI/PKnqH3HM1Wl Sc4c+v/7n3/rV6P2U1C80HgvMepLUnHruP+N X-Google-Smtp-Source: ABdhPJyt7Jp+Bkvnhh27dfAu3kmuK4axHa5vTfQHGzOHBpfd+wmjWkSyFhnjAXFKE83Z6RZ8hOguIg== X-Received: by 2002:a5d:43c6:: with SMTP id v6mr729946wrr.20.1602159355024; Thu, 08 Oct 2020 05:15:55 -0700 (PDT) Return-Path: Received: from vanye (cpc92302-cmbg19-2-0-cust304.5-4.cable.virginm.net. [82.1.209.49]) by smtp.gmail.com with ESMTPSA id j14sm7315548wrr.66.2020.10.08.05.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Oct 2020 05:15:54 -0700 (PDT) Date: Thu, 8 Oct 2020 13:15:47 +0100 From: "Leif Lindholm" To: Meenakshi Aggarwal Cc: ard.biesheuvel@arm.com, michael.d.kinney@intel.com, devel@edk2.groups.io, v.sethi@nxp.com, Meenakshi Aggarwal Subject: Re: [edk2-platforms v2 3/6] Silicon/NXP: Add SCFG support for Chassis2 Message-ID: <20201008121547.GZ5623@vanye> References: <1600187343-18732-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> <1602087041-8009-1-git-send-email-meenakshi.aggarwal@oss.nxp.com> <1602087041-8009-4-git-send-email-meenakshi.aggarwal@oss.nxp.com> MIME-Version: 1.0 In-Reply-To: <1602087041-8009-4-git-send-email-meenakshi.aggarwal@oss.nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Oct 07, 2020 at 21:40:38 +0530, Meenakshi Aggarwal wrote: > Add support for SCFG (Supplemental Configuration Unit) > register space and helper functions to R/W SCFG registers > > Signed-off-by: Meenakshi Aggarwal Reviewed-by: Leif Lindholm > --- > Silicon/NXP/NxpQoriqLs.dec | 1 + > Silicon/NXP/Chassis2/Include/Chassis.h | 108 +++++++++++++++++++++ > Silicon/NXP/Include/Library/ChassisLib.h | 42 ++++++++ > .../NXP/Chassis2/Library/ChassisLib/ChassisLib.c | 63 ++++++++++++ > 4 files changed, 214 insertions(+) > > diff --git a/Silicon/NXP/NxpQoriqLs.dec b/Silicon/NXP/NxpQoriqLs.dec > index 3a568c0437e7..90dce69fd472 100644 > --- a/Silicon/NXP/NxpQoriqLs.dec > +++ b/Silicon/NXP/NxpQoriqLs.dec > @@ -30,6 +30,7 @@ [PcdsFeatureFlag] > gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian|FALSE|BOOLEAN|0x00000317 > gNxpQoriqLsTokenSpaceGuid.PcdSataErratumA009185|FALSE|BOOLEAN|0x00000318 > gNxpQoriqLsTokenSpaceGuid.PcdGpioControllerBigEndian|FALSE|BOOLEAN|0x00000319 > + gNxpQoriqLsTokenSpaceGuid.PcdScfgBigEndian|FALSE|BOOLEAN|0x00000320 > > [PcdsFixedAtBuild.common] > # Pcds for PCI Express > diff --git a/Silicon/NXP/Chassis2/Include/Chassis.h b/Silicon/NXP/Chassis2/Include/Chassis.h > index 7e8bf224884b..6dfce425a0b0 100644 > --- a/Silicon/NXP/Chassis2/Include/Chassis.h > +++ b/Silicon/NXP/Chassis2/Include/Chassis.h > @@ -11,6 +11,7 @@ > #include > > #define NXP_LAYERSCAPE_CHASSIS2_DCFG_ADDRESS 0x1EE0000 > +#define NXP_LAYERSCAPE_CHASSIS2_SCFG_ADDRESS 0x1570000 > > #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE) > #define SVR_MAJOR(svr) (((svr) >> 4) & 0xf) > @@ -45,4 +46,111 @@ typedef struct { > } NXP_LAYERSCAPE_CHASSIS2_DEVICE_CONFIG; > #pragma pack() > > +/* Supplemental Configuration Unit (SCFG) */ > +typedef struct { > + UINT8 Res000[0x070-0x000]; > + UINT32 Usb1Prm1Cr; > + UINT32 Usb1Prm2Cr; > + UINT32 Usb1Prm3Cr; > + UINT32 Usb2Prm1Cr; > + UINT32 Usb2Prm2Cr; > + UINT32 Usb2Prm3Cr; > + UINT32 Usb3Prm1Cr; > + UINT32 Usb3Prm2Cr; > + UINT32 Usb3Prm3Cr; > + UINT8 Res094[0x100-0x094]; > + UINT32 Usb2Icid; > + UINT32 Usb3Icid; > + UINT8 Res108[0x114-0x108]; > + UINT32 DmaIcid; > + UINT32 SataIcid; > + UINT32 Usb1Icid; > + UINT32 QeIcid; > + UINT32 SdhcIcid; > + UINT32 EdmaIcid; > + UINT32 EtrIcid; > + UINT32 Core0SftRst; > + UINT32 Core1SftRst; > + UINT32 Core2SftRst; > + UINT32 Core3SftRst; > + UINT8 Res140[0x158-0x140]; > + UINT32 AltCBar; > + UINT32 QspiCfg; > + UINT8 Res160[0x180-0x160]; > + UINT32 DmaMcr; > + UINT8 Res184[0x188-0x184]; > + UINT32 GicAlign; > + UINT32 DebugIcid; > + UINT8 Res190[0x1a4-0x190]; > + UINT32 SnpCnfgCr; > +#define SCFG_SNPCNFGCR_SECRDSNP BIT31 > +#define SCFG_SNPCNFGCR_SECWRSNP BIT30 > +#define SCFG_SNPCNFGCR_SATARDSNP BIT23 > +#define SCFG_SNPCNFGCR_SATAWRSNP BIT22 > +#define SCFG_SNPCNFGCR_USB1RDSNP BIT21 > +#define SCFG_SNPCNFGCR_USB1WRSNP BIT20 > +#define SCFG_SNPCNFGCR_USB2RDSNP BIT15 > +#define SCFG_SNPCNFGCR_USB2WRSNP BIT16 > +#define SCFG_SNPCNFGCR_USB3RDSNP BIT13 > +#define SCFG_SNPCNFGCR_USB3WRSNP BIT14 > + UINT8 Res1a8[0x1ac-0x1a8]; > + UINT32 IntpCr; > + UINT8 Res1b0[0x204-0x1b0]; > + UINT32 CoreSrEnCr; > + UINT8 Res208[0x220-0x208]; > + UINT32 RvBar00; > + UINT32 RvBar01; > + UINT32 RvBar10; > + UINT32 RvBar11; > + UINT32 RvBar20; > + UINT32 RvBar21; > + UINT32 RvBar30; > + UINT32 RvBar31; > + UINT32 LpmCsr; > + UINT8 Res244[0x400-0x244]; > + UINT32 QspIdQScr; > + UINT32 EcgTxcMcr; > + UINT32 SdhcIoVSelCr; > + UINT32 RcwPMuxCr0; > + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS > + Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT > + Setting RCW PinMux Register bits 25-27 to select USB3_DRVVBUS > + Setting RCW PinMux Register bits 29-31 to select USB3_DRVVBUS > + **/ > +#define SCFG_RCWPMUXCRO_SELCR_USB 0x3333 > + /**Setting RCW PinMux Register bits 17-19 to select USB2_DRVVBUS > + Setting RCW PinMux Register bits 21-23 to select USB2_PWRFAULT > + Setting RCW PinMux Register bits 25-27 to select IIC4_SCL > + Setting RCW PinMux Register bits 29-31 to select IIC4_SDA > + **/ > +#define SCFG_RCWPMUXCRO_NOT_SELCR_USB 0x3300 > + UINT32 UsbDrvVBusSelCr; > +#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000 > +#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001 > +#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000003 > + UINT32 UsbPwrFaultSelCr; > +#define SCFG_USBPWRFAULT_INACTIVE 0x00000000 > +#define SCFG_USBPWRFAULT_SHARED 0x00000001 > +#define SCFG_USBPWRFAULT_DEDICATED 0x00000002 > +#define SCFG_USBPWRFAULT_USB3_SHIFT 4 > +#define SCFG_USBPWRFAULT_USB2_SHIFT 2 > +#define SCFG_USBPWRFAULT_USB1_SHIFT 0 > + UINT32 UsbRefclkSelcr1; > + UINT32 UsbRefclkSelcr2; > + UINT32 UsbRefclkSelcr3; > + UINT8 Res424[0x600-0x424]; > + UINT32 ScratchRw[4]; > + UINT8 Res610[0x680-0x610]; > + UINT32 CoreBCr; > + UINT8 Res684[0x1000-0x684]; > + UINT32 Pex1MsiIr; > + UINT32 Pex1MsiR; > + UINT8 Res1008[0x2000-0x1008]; > + UINT32 Pex2; > + UINT32 Pex2MsiR; > + UINT8 Res2008[0x3000-0x2008]; > + UINT32 Pex3MsiIr; > + UINT32 Pex3MsiR; > +} NXP_LAYERSCAPE_CHASSIS2_SUPPLEMENTAL_CONFIG; > + > #endif // CHASSIS_H__ > diff --git a/Silicon/NXP/Include/Library/ChassisLib.h b/Silicon/NXP/Include/Library/ChassisLib.h > index 89992a4b6fd5..a038d8e5ce31 100644 > --- a/Silicon/NXP/Include/Library/ChassisLib.h > +++ b/Silicon/NXP/Include/Library/ChassisLib.h > @@ -13,6 +13,48 @@ > #include > > /** > + Or Scfg register > + > + @param Address The MMIO register to read. > + > + @return The value read. > +**/ > +UINT32 > +EFIAPI > +ScfgOr32 ( > + IN UINTN Address, > + IN UINT32 Value > + ); > + > +/** > + Read Scfg register > + > + @param Address The MMIO register to read. > + > + @return The value read. > +**/ > +UINT32 > +EFIAPI > +ScfgRead32 ( > + IN UINTN Address > + ); > + > +/** > + Write Scfg register > + > + @param Address The MMIO register to write. > + @param Value The value to write to the MMIO register. > + > + @return Value. > +**/ > +UINT32 > +EFIAPI > +ScfgWrite32 ( > + IN UINTN Address, > + IN UINT32 Value > + ); > + > +/** > Read Dcfg register > > @param Address The MMIO register to read. > diff --git a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c > index 91b19f832f00..e6410a53f480 100644 > --- a/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c > +++ b/Silicon/NXP/Chassis2/Library/ChassisLib/ChassisLib.c > @@ -15,6 +15,69 @@ > #include > > /** > + Or Scfg register > + > + @param Address The MMIO register to read. > + > + @return The value read. > +**/ > +UINT32 > +EFIAPI > +ScfgOr32 ( > + IN UINTN Address, > + IN UINT32 Value > + ) > +{ > + MMIO_OPERATIONS *ScfgOps; > + > + ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian)); > + > + return ScfgOps->Or32 (Address, Value); > +} > + > +/** > + Read Scfg register > + > + @param Address The MMIO register to read. > + > + @return The value read. > +**/ > +UINT32 > +EFIAPI > +ScfgRead32 ( > + IN UINTN Address > + ) > +{ > + MMIO_OPERATIONS *ScfgOps; > + > + ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian)); > + > + return ScfgOps->Read32 (Address); > +} > + > +/** > + Write Scfg register > + > + @param Address The MMIO register to write. > + @param Value The value to write to the MMIO register. > + > + @return Value. > +**/ > +UINT32 > +EFIAPI > +ScfgWrite32 ( > + IN UINTN Address, > + IN UINT32 Value > + ) > +{ > + MMIO_OPERATIONS *ScfgOps; > + > + ScfgOps = GetMmioOperations (FeaturePcdGet (PcdScfgBigEndian)); > + > + return ScfgOps->Write32 (Address, Value); > +} > + > +/** > Read Dcfg register > > @param Address The MMIO register to read. > -- > 1.9.1 >