From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f228.google.com (mail-pf1-f228.google.com [209.85.210.228]) by mx.groups.io with SMTP id smtpd.web12.14034.1602168996975445529 for ; Thu, 08 Oct 2020 07:56:37 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@broadcom.com header.s=google header.b=C1ci9GCk; spf=permerror, err=parse error for token &{10 18 %{i}._ip.%{h}._ehlo.%{d}._spf.vali.email}: invalid domain name (domain: broadcom.com, ip: 209.85.210.228, mailfrom: rajesh.ravi@broadcom.com) Received: by mail-pf1-f228.google.com with SMTP id g10so4207449pfc.8 for ; Thu, 08 Oct 2020 07:56:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A4koLwz2HmBBIrsKOBWpLwOyDS/1u5BrjF14tGbbPcM=; b=C1ci9GCkRSjT0J8PrtYVPrKTN6FAI16+n1xUuqZgqftiLvBUM8J3LvEuKm6JqOCfPG lhk5/EvVIYzCXyTgBPmnWgvQuOZLAKz3lTf+nhjg62NBADd2vOfSmXIdawpknebG59NY ep3z+ujpvw8cL1XmzitVUr6WMtkOxRNypKfKo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A4koLwz2HmBBIrsKOBWpLwOyDS/1u5BrjF14tGbbPcM=; b=jLrra46ZtyBchbFw+AN3Qrx38kYiufWX1ojVyFCO4LYJziaSFlmFYPeVCQUsABpH87 LzfnhQVz5iFipmeFuNvFogYNx0lvrjJSQOTn6VgRwXi3bGR5BGvMS2wSc/bM9WV2nPnV ZewOe1EN99XciWWJC8oHXbszGLSk5Z+LHv77SNp+VsizLTnYLCQ+cpaHkofvRa2+mg6o F7oQflXSgkRshF2xCLlprUjgtgbLQwxy7A3K3fpaPrdiXMsSjzKzn1cWb80fMTuDqMCx Ko4Nr7iFJMC4qKTlGqMa6blbztfu0JsWfScBNK2t20+gtCZIskXZP/fBzMjMng5Ec2/J sl2g== X-Gm-Message-State: AOAM533uUxfIgaTVDvCCbvqU5Ta3e++sZ1zRcUlW2W5vN8sOxIfm+JtZ tlDZRJQLVHHxaisKxnbLKD111j5g4viF4vtUiQ+tw9IuBKCXKNor/+b7rsM/BV7au4vRNOLKYKD G8bKPXkGiHVmfLk9LFpjvDiJZXBGH5DP36RdQGXHx6GukbgMquP00n6uo1aBUFhxwpEcQm7nrAM rRx25Q65HTBw== X-Google-Smtp-Source: ABdhPJxQBG/DMDPGhx/OBIHsUQ4R7irb5e8/5gdoRk3LIVPNCpO82PoBaPjNYiEX93fIhz07Swj+Kfco2ZTq X-Received: by 2002:a17:90a:6a4f:: with SMTP id d15mr8696875pjm.80.1602168996063; Thu, 08 Oct 2020 07:56:36 -0700 (PDT) Return-Path: Received: from rbuild18.dhcp.broadcom.net ([192.19.234.250]) by smtp-relay.gmail.com with ESMTPS id bb23sm439479pjb.5.2020.10.08.07.56.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Oct 2020 07:56:36 -0700 (PDT) X-Relaying-Domain: broadcom.com From: "rajesh.ravi@broadcom.com" To: devel@edk2.groups.io Cc: Rajesh Ravi , Leif Lindholm , Ard Biesheuvel Subject: [PATCH v1 1/1] ArmPkg/GenericWatchdogDxe: Add rev 1 support to ARM Generic Watchdog driver Date: Thu, 8 Oct 2020 20:26:08 +0530 Message-Id: <20201008145608.15737-2-rajesh.ravi@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201008145608.15737-1-rajesh.ravi@broadcom.com> References: <20201008145608.15737-1-rajesh.ravi@broadcom.com> From: Rajesh Ravi Add SBSA watchdog rev 1 support to ARM Generic Watchdog driver. Signed-off-by: Rajesh Ravi Cc: Leif Lindholm Cc: Ard Biesheuvel --- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h | 8 ++- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 53 ++++++++++++++++++-- 2 files changed, 56 insertions(+), 5 deletions(-) diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h index c64bc5c4627d..ed74bcf95021 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h @@ -13,12 +13,18 @@ // Control Frame: #define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000) -#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008) +#define GENERIC_WDOG_OFFSET_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008) +#define GENERIC_WDOG_OFFSET_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x00C) #define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010) #define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014) +#define GENERIC_WDOG_IIDR_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0xFCC) // Values of bit 0 of the Control/Status Register #define GENERIC_WDOG_ENABLED 1 #define GENERIC_WDOG_DISABLED 0 +#define GENERIC_WDOG_ARCH_REV_OFFSET 16 +#define GENERIC_WDOG_ARCH_REV_MASK 0xF +#define SBSA_WDOG_WOR_WIDTH 48 +#define MAX_OFFSET_REG_VAL (((UINT64)1 << 48) - 1) #endif // __GENERIC_WATCHDOG_H__ diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c index f79cc9170f8a..7ef9b1ff08ab 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c @@ -35,16 +35,53 @@ STATIC UINTN mTimerFrequencyHz = 0; It is therefore stored here. 0 means the timer is not running. */ STATIC UINT64 mNumTimerTicks = 0; +STATIC UINT32 mWatchDogRev = 0; + +STATIC UINT64 mWatchdogMaxOffsetVal = MAX_UINT32; + STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol; STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify; +STATIC +inline +UINT32 +WatchdogReadRevisionRegister ( + VOID + ) +{ + return MmioRead32 (GENERIC_WDOG_IIDR_REG); +} + +STATIC +inline +UINT32 +WatchdogGetRevision ( + VOID + ) +{ + UINT32 IidrRegVal; + + IidrRegVal = WatchdogReadRevisionRegister(); + + return ((IidrRegVal >> GENERIC_WDOG_ARCH_REV_OFFSET) & GENERIC_WDOG_ARCH_REV_MASK); +} + STATIC VOID WatchdogWriteOffsetRegister ( - UINT32 Value + UINT64 Value ) { - MmioWrite32 (GENERIC_WDOG_OFFSET_REG, Value); + if(Value >> SBSA_WDOG_WOR_WIDTH) { + return; + } + + MmioWrite32 (GENERIC_WDOG_OFFSET_REG_LOW, ((UINT32)Value & MAX_UINT32)); + if (mWatchDogRev) { + MmioWrite32 (GENERIC_WDOG_OFFSET_REG_HIGH, (Value >> 32) & MAX_UINT32); + } else { + MmioWrite32 (GENERIC_WDOG_OFFSET_REG_HIGH, 0); + } } STATIC @@ -207,12 +244,12 @@ WatchdogSetTimerPeriod ( /* If the number of required ticks is greater than the max the watchdog's offset register (WOR) can hold, we need to manually compute and set the compare register (WCV) */ - if (mNumTimerTicks > MAX_UINT32) { + if (mNumTimerTicks > mWatchdogMaxOffsetVal) { /* We need to enable the watchdog *before* writing to the compare register, because enabling the watchdog causes an "explicit refresh", which clobbers the compare register (WCV). In order to make sure this doesn't trigger an interrupt, set the offset to max. */ - WatchdogWriteOffsetRegister (MAX_UINT32); + WatchdogWriteOffsetRegister (MAX_OFFSET_REG_VAL); WatchdogEnable (); SystemCount = ArmGenericTimerGetSystemCount (); WatchdogWriteCompareRegister (SystemCount + mNumTimerTicks); @@ -319,6 +356,14 @@ GenericWatchdogEntry ( mTimerFrequencyHz = ArmGenericTimerGetTimerFreq (); ASSERT (mTimerFrequencyHz != 0); + mWatchDogRev = WatchdogGetRevision(); + + if (mWatchDogRev) { + mWatchdogMaxOffsetVal = MAX_OFFSET_REG_VAL; + } else { + mWatchdogMaxOffsetVal = MAX_UINT32; + } + // Install interrupt handler Status = mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol, FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum), -- 2.17.1