[PATCH v1 1/1] UefiCpuPkg: Clean up save state boundary checks and comments.

[Mark Wilson <Mark.Wilson@amd.com>]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2956

In functions ReadSaveStateRegisterByIndex and WriteSaveStateRegister:
* check width > 4 instead of >= 4 when writing upper 32 bytes.
  - This improves the code but will not affect functionality.
* Update related comments to better describe code.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Mark Wilson <Mark.Wilson@amd.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 26 ++++++++++----------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
index 661cc51f361a..4a872e400b7a 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -297,8 +297,8 @@ ReadSaveStateRegisterByIndex (
     //
     // Write return buffer
     //
-    ASSERT(CpuSaveState != NULL);
-    CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
+    ASSERT (CpuSaveState != NULL);
+    CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
   } else {
     //
     // If 64-bit mode width is zero, then the specified register can not be accessed
@@ -315,14 +315,14 @@ ReadSaveStateRegisterByIndex (
     }
 
     //
-    // Write lower 32-bits of return buffer
+    // Write at most 4 of the lower bytes of the return buffer
     //
-    CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width));
-    if (Width >= 4) {
+    CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width));
+    if (Width > 4) {
       //
-      // Write upper 32-bits of return buffer
+      // Write at most 4 of the upper bytes of the return buffer
       //
-      CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
+      CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
     }
   }
   return EFI_SUCCESS;
@@ -522,7 +522,7 @@ WriteSaveStateRegister (
     // Write SMM State register
     //
     ASSERT (CpuSaveState != NULL);
-    CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
+    CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
   } else {
     //
     // If 64-bit mode width is zero, then the specified register can not be accessed
@@ -539,14 +539,14 @@ WriteSaveStateRegister (
     }
 
     //
-    // Write lower 32-bits of SMM State register
+    // Write at most 4 of the lower bytes of SMM State register
     //
-    CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
-    if (Width >= 4) {
+    CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
+    if (Width > 4) {
       //
-      // Write upper 32-bits of SMM State register
+      // Write at most 4 of the upper bytes of SMM State register
       //
-      CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
+      CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
     }
   }
   return EFI_SUCCESS;
-- 
2.27.0.windows.1