From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.groups.io with SMTP id smtpd.web11.721.1603381821121537465 for ; Thu, 22 Oct 2020 08:50:21 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviateam.com header.s=google header.b=GXo38oU8; spf=pass (domain: nuviateam.com, ip: 209.85.221.54, mailfrom: tomas@nuviateam.com) Received: by mail-wr1-f54.google.com with SMTP id y12so3050774wrp.6 for ; Thu, 22 Oct 2020 08:50:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviateam.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9ViXqCZs0mcmyDtSYaVsOa9y8QvrnGm7/lzEuOVZa2I=; b=GXo38oU8RoCL0bl60z1no11JGXm+2SRl5kqqBNFqqOoLwyIjsb+ybdIjNnMUIz9AE8 20qRXvhQm4THPMKZB/fvg2g32kXvx0P3SSwHcHrBBzzIblZ6XAYRp+B4fAZ2EvcIMwTe RzJmqo9IfWReTymaj+lRurMb0I5Mf3a9FqabAfDBg9FtDZUJsIftdOHnvIarcbzJRjD3 amMQgvOhYpZvDnsPO+Alx1PwZyHXaGhXORjKVpg1TToStVSbkf4URH6xXe9PWIof3zJU vYjuI1gGjuaiqw+HpsP8HqpRzL3faxEt6s21M5XeO58I09os09BWdkC/+7Cg08dsavvm w0bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9ViXqCZs0mcmyDtSYaVsOa9y8QvrnGm7/lzEuOVZa2I=; b=MuYanlrvy8WnkVdWdKtI2ISvNFdO9nWLgI0IkTeOUtVJvOw+t7IVYTJdVowuSfruv9 OUxlxxLLNB3N0+4dz8zk3zq0hfSX1xFIBlNNh/tA44sgzP9micn/BrzeBYs50GGky1xk Q2C+kZQIVGj+UEqMoqyYVQuFGQaoJdWu+PulQx//0/NbnrI76VXPWgv6CdZbfSjFs+/c 4/sUmMOUufhyAgmnQ0iDAk+aX76HWOlgLeSY+Y9YGKsEnSptaH/Y5qZuFnU9tx8cfIuy tVKjCT3jZ4pv9nQIACgqo8k+99dl50RIXYdwmfWvDCtqhuj/U6+UjUcF4zf3tMCBFqjK 7Pog== X-Gm-Message-State: AOAM532n2b41mHhx6tvf6uzJthte/bpawyUYXrUMTumnmPAPYcszPL+p QTaOxk92dV31HWjI2GXwBOpsPZnOOV8VCQ54 X-Google-Smtp-Source: ABdhPJw/D68/VNluyYpAVL7zpHB/Q6BQU1N//srTqNCPpvBgTCSouhrCL2QpjIhvKLLy3wMfYi+iRw== X-Received: by 2002:adf:f2c1:: with SMTP id d1mr3632928wrp.179.1603381819492; Thu, 22 Oct 2020 08:50:19 -0700 (PDT) Return-Path: Received: from white-rabbit.sw.nuviainc.com ([2.30.51.167]) by smtp.gmail.com with ESMTPSA id 133sm4377342wmb.2.2020.10.22.08.50.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2020 08:50:19 -0700 (PDT) From: "Tomas Pilar (tpilar)" To: devel@edk2.groups.io Cc: Leif Lindholm , Ard Biesheuvel , Tanmay Jagdale Subject: [edk2-platform][PATCH 2/3] Platform,Silicon/Qemu: Define PcdPcie*Limit variables Date: Thu, 22 Oct 2020 16:50:15 +0100 Message-Id: <20201022155016.228362-3-tomas@nuviateam.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201022155016.228362-1-tomas@nuviateam.com> References: <20201022155016.228362-1-tomas@nuviateam.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The ACPI tables require not only the base and the size of various PCIe memory windows, but also the limit defined as Limit = Base + Size - 1 Given that ASL does not permit basic constant arithmetics when defining resources or passing arguements to functions, we define PCDs that hold these limits. The PCDs can then be modified individually in platform DSC files. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Tanmay Jagdale Signed-off-by: Tomas Pilar --- Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 ++++++ Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 11 +++++++++++ 2 files changed, 17 insertions(+) diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc index 0e6d738bee..49bc5033f4 100644 --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc @@ -458,15 +458,21 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE gArmTokenSpaceGuid.PcdPciBusMax|255 gArmTokenSpaceGuid.PcdPciIoBase|0x0 gArmTokenSpaceGuid.PcdPciIoSize|0x00010000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit|0x0000ffff gArmTokenSpaceGuid.PcdPciMmio32Base|0x80000000 gArmTokenSpaceGuid.PcdPciMmio32Size|0x70000000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit|0xEFFFFFFF gArmTokenSpaceGuid.PcdPciMmio64Base|0x100000000 gArmTokenSpaceGuid.PcdPciMmio64Size|0xFF00000000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit|0xFFFFFFFFFF # set PcdPciExpressBaseAddress to MAX_UINT64, which signifies that this # PCD and PcdPciDisableBusEnumeration have not been assigned yet # TODO: PcdPciExpressBaseAddress set to max_uint64 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xf0000000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF + gArmTokenSpaceGuid.PcdPciIoTranslation|0x7fff0000 gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0 gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0 diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec index e8d55a530d..476dc82f98 100644 --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec @@ -36,6 +36,17 @@ gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPlatformEhciSize|0x10000|UINT32|0x00000004 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress|0x10000000000|UINT64|0x00000005 + # PCDs complementing PCIe layout pulled into ACPI tables + # Limit = Base + Size - 1 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciIoLimit|0x0000ffff|UINT32|0x00000006 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio32Limit|0xEFFFFFFF|UINT32|0x00000007 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciMmio64Limit|0xFFFFFFFFFF|UINT64|0x00000008 + + # PCDs complementing gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + # BarLimit = BaseAddress + BarSize - 1 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000|UINT64|0x00000009 + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF|UINT64|0x00000010 + [PcdsDynamic.common] gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000100 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x00000101 -- 2.25.1