From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (EUR05-DB8-obe.outbound.protection.outlook.com [40.107.20.83]) by mx.groups.io with SMTP id smtpd.web09.4973.1604414057339849797 for ; Tue, 03 Nov 2020 06:34:18 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=jSiYKqg8; spf=pass (domain: arm.com, ip: 40.107.20.83, mailfrom: sami.mujawar@arm.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LRrKrVvwnF2l3RqCQi1viDBKVASLVs7r1iCaeFwo0MI=; b=jSiYKqg8XDNX6xJguy0eXYx985mbl6brA412HlO+RZXFFsa/v0RCCkjggDi408ap583YYM3PTN92B9hJo90lHZ9LAAYhQp/rEKNiEZR+8cdMJfqtRQZI6V4/sC6YW6ud0qbK8Ie3s44mK8LHcOwoNNTNpZHKIlAeRNe1DeZG234= Received: from AM6P195CA0069.EURP195.PROD.OUTLOOK.COM (2603:10a6:209:87::46) by AM0PR08MB3524.eurprd08.prod.outlook.com (2603:10a6:208:de::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18; Tue, 3 Nov 2020 14:34:12 +0000 Received: from AM5EUR03FT060.eop-EUR03.prod.protection.outlook.com (2603:10a6:209:87:cafe::70) by AM6P195CA0069.outlook.office365.com (2603:10a6:209:87::46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Tue, 3 Nov 2020 14:34:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; edk2.groups.io; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;edk2.groups.io; dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM5EUR03FT060.mail.protection.outlook.com (10.152.16.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3520.15 via Frontend Transport; Tue, 3 Nov 2020 14:34:12 +0000 Received: ("Tessian outbound a64c3afb6fc9:v64"); Tue, 03 Nov 2020 14:34:11 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 9696847228fdb757 X-CR-MTA-TID: 64aa7808 Received: from 0771a6701b85.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id D5C14F6F-EA68-4184-892D-539C2DBB0450.1; Tue, 03 Nov 2020 14:33:51 +0000 Received: from EUR04-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 0771a6701b85.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Tue, 03 Nov 2020 14:33:51 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=V7I8gmSVvEiVoJ8Gk7HSzs4F4E74eE5tL/FrxhCxxRC0QQRPOvXZtg0b6Gf6Ya/0KDT5dHPPIHmlXZxSIOP4jJfL8TYfdzyvpJ58FTLfEzRfzo4KK4gYQfN9uKxwHejvU0Y+latWQhPqVbPwcF8z0SvmvKdI8iqiE2chEUEG6v5Y9FaulUL2SJLN5RQgiRLjD45hTvAy061UHAHDgxdzBffLuNp8gXCbupXkA+oYbJ4F9RTkyMkNBULwgsor3IAyZcwCqHc3Hf7apqIMV1kBnU8kRefU8CgqPKpJd9eO/HU2BIyVqI/3RIaJKIPXNctyRh9ZWathVUvbKqDEY/iCMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LRrKrVvwnF2l3RqCQi1viDBKVASLVs7r1iCaeFwo0MI=; b=Edytjsq0oyjEatT2/TAy2pWm7bQKVnj3plW5FqTprMxs3HnvOmToYH2RUacDOWFvPlCHne9VB5ak8AwjzmMp8GMoaTLG7KzKKEbvJ3sDPxcJFfFIV5SW/3PY9Qi/4gp6ARyQUU+BPOxRE/p7UekuvKj8VwGozLPms+BYtNxXZtcQaQO+OiKUFMmcM5TlSFZWO916eKfKsQlXpDbQnUsTAArRg7uD+v+P9qbmCis+gRSDeYKq7zIusTDkQ0D/86g7peSg2HkPu8hHi9TwGuf9Dwgf5t0SssaTcbevMnW/e5R2XEtbTHwUXgvyOZNvWBGtj+vp1IThXYHeBcU1LDtv6A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=edk2.groups.io smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LRrKrVvwnF2l3RqCQi1viDBKVASLVs7r1iCaeFwo0MI=; b=jSiYKqg8XDNX6xJguy0eXYx985mbl6brA412HlO+RZXFFsa/v0RCCkjggDi408ap583YYM3PTN92B9hJo90lHZ9LAAYhQp/rEKNiEZR+8cdMJfqtRQZI6V4/sC6YW6ud0qbK8Ie3s44mK8LHcOwoNNTNpZHKIlAeRNe1DeZG234= Received: from MR2P264CA0094.FRAP264.PROD.OUTLOOK.COM (2603:10a6:500:32::34) by HE1PR0801MB2010.eurprd08.prod.outlook.com (2603:10a6:3:4b::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.19; Tue, 3 Nov 2020 14:33:48 +0000 Received: from VE1EUR03FT044.eop-EUR03.prod.protection.outlook.com (2603:10a6:500:32:cafe::93) by MR2P264CA0094.outlook.office365.com (2603:10a6:500:32::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.19 via Frontend Transport; Tue, 3 Nov 2020 14:33:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; edk2.groups.io; dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; Received: from nebula.arm.com (40.67.248.234) by VE1EUR03FT044.mail.protection.outlook.com (10.152.19.106) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3520.15 via Frontend Transport; Tue, 3 Nov 2020 14:33:47 +0000 Received: from AZ-NEU-EX01.Emea.Arm.com (10.251.26.4) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2044.4; Tue, 3 Nov 2020 14:32:04 +0000 Received: from AZ-NEU-EX03.Arm.com (10.251.24.31) by AZ-NEU-EX01.Emea.Arm.com (10.251.26.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1779.2; Tue, 3 Nov 2020 14:32:04 +0000 Received: from E107187.Arm.com (10.57.50.23) by mail.arm.com (10.251.24.31) with Microsoft SMTP Server id 15.1.2044.4 via Frontend Transport; Tue, 3 Nov 2020 14:32:03 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , , , , Subject: [PATCH v2-resend 1/2] MdePkg/IndustryStandard: AEST Table definition Date: Tue, 3 Nov 2020 14:32:01 +0000 Message-ID: <20201103143202.19660-2-sami.mujawar@arm.com> X-Mailer: git-send-email 2.11.0.windows.3 In-Reply-To: <20201103143202.19660-1-sami.mujawar@arm.com> References: <20201103143202.19660-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b7071de5-699e-456e-6afe-08d88005884c X-MS-TrafficTypeDiagnostic: HE1PR0801MB2010:|AM0PR08MB3524: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:8882;OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: Yy7okRTYZH1RVDiFOxhBzWs+WZd5/rdIyy8/YW4mtXriWoAYyM/t2pNPHhJIXOavAXfVQ05VujsPDtTF3SNLjUhOciZ3D2GryY3aCkMS8yiOCxlCzi+s7/YfwKgNw/tZ3cY2zlyTEg2bSSi3P7dWAmnRTOGdtYr6TC6exiGdpSworxn1zsTmjWHqG48ohlhweSs50fsZ3JWdSZK5r8wa6VJ63rHCIXrnwMPRyPQa4D6kx4JNw/+HGovlROhyKppnYqzi0XUS1KjJK4jgNgzrEyhygRkEQi9G3L8cfpZe7hHotdvO90C4oZ+F/S5tP2WCbsm75Nzw09WiQ3xX6S2w0OCnflMb7jPppMkZk5Yq8xD4gW/pLQ8SLw43yPt/AJuROJFmpPV72vfCkowLY41JXR/HRm9OV+2zlWqqThjGZQBCgjtJH1tbHKItnpK5no8VYl+8wEjzGwjtFnbLwAF0MerFFeLoy8h1T8+ncuLmNyM= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(39850400004)(136003)(346002)(376002)(396003)(46966005)(2616005)(70206006)(316002)(1076003)(966005)(30864003)(426003)(478600001)(5660300002)(186003)(26005)(7696005)(54906003)(86362001)(44832011)(70586007)(6916009)(336012)(4326008)(83380400001)(81166007)(47076004)(36756003)(356005)(82310400003)(2906002)(8676002)(82740400003)(8936002);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0801MB2010 Return-Path: Sami.Mujawar@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT060.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 13495c7e-d626-45a9-3a37-08d880057994 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4ixKWpPkgOsH9anbpxk5pg1rFCjux4dSXVd0JlK5Z1e2fjrDh0wuym1j+Hbzuebxy4TAN8s2AKWY4XAvFM2Lm8Z0e2PBO5icHA3yWyHvYd33jxDquVM9ZAy/ejjwZuzyeDPc2dQ0OIshCKxYh+a+wFbn1WeoHS6zniyAJu13YIZ0VqX2532RmLmZY3yg6/xtnbcqj7RfLf81ulmrpAGn125VUQVP0PySOP3DD1o9BiRzKc57+8Z3i4Qx0RpLyWJVrP8dj2Oa1+RJf+KTR4ONZE0U+YvzJk9Y0JXsRBDVMarGkIdzG5n22D+9I4u5Ow7Oy+Ya9Y7+RKb7sk/HEEZ7E1lZtZh6Ww7U4+p0g3M/AeqrxG42hr/PjEhwA5/th1UY+LZnou9HQFk+rLX1M7HFH8aYZ31AefxzU4g8veNy5pMJVw6dVRwT27xxajcLB8QAiOYNiHTwy16bLRWeh0q8pTJ0AWAC0vb5eaV0+a07DoE= X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(4636009)(376002)(39850400004)(396003)(346002)(136003)(46966005)(2906002)(478600001)(8676002)(4326008)(2616005)(70206006)(1076003)(8936002)(70586007)(5660300002)(30864003)(316002)(44832011)(966005)(26005)(336012)(186003)(81166007)(426003)(86362001)(6916009)(47076004)(82740400003)(36756003)(83380400001)(82310400003)(7696005)(54906003);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2020 14:34:12.2082 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b7071de5-699e-456e-6afe-08d88005884c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT060.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB3524 Content-Type: text/plain From: Marc Moisson-Franckhauser Bugzilla: 3049 (https://bugzilla.tianocore.org/show_bug.cgi?id=3049) Add definition for the Arm Error Source Table (AEST) described in the ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document, dated 28 September 2020. (https://developer.arm.com/documentation/den0085/0101/) Signed-off-by: Marc Moisson-Franckhauser Signed-off-by: Sami Mujawar Reviewed-by: Liming Gao --- Notes: v2: - AEST is not defined in ACPI 6.3 spec and should not be [Liming] added to Acpi63.h and for structure definition and its field, its comment starts with /// or //. - Moved AEST table signature to ArmErrorSourceTable.h and [SAMI] updated structure and field documenting style to match coding convention. Ref: https://edk2.groups.io/g/devel/message/66151 MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h | 357 ++++++++++++++++++++ 1 file changed, 357 insertions(+) diff --git a/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h b/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h new file mode 100644 index 0000000000000000000000000000000000000000..369b03a50b65a7f6d0012eec9898a14dcd61976d --- /dev/null +++ b/MdePkg/Include/IndustryStandard/ArmErrorSourceTable.h @@ -0,0 +1,357 @@ +/** @file + Arm Error Source Table as described in the + 'ACPI for the Armv8 RAS Extensions 1.1' Specification. + + Copyright (c) 2020 Arm Limited. + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Reference(s): + - ACPI for the Armv8 RAS Extensions 1.1 Platform Design Document, + dated 28 September 2020. + (https://developer.arm.com/documentation/den0085/0101/) + + @par Glossary + - Ref : Reference + - Id : Identifier +**/ + +#ifndef ARM_ERROR_SOURCE_TABLE_H_ +#define ARM_ERROR_SOURCE_TABLE_H_ + +/// +/// "AEST" Arm Error Source Table +/// +#define EFI_ACPI_6_3_ARM_ERROR_SOURCE_TABLE_SIGNATURE SIGNATURE_32('A', 'E', 'S', 'T') + +#define EFI_ACPI_ARM_ERROR_SOURCE_TABLE_REVISION 1 + +#pragma pack(1) + +/// +/// Arm Error Source Table definition. +/// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; +} EFI_ACPI_ARM_ERROR_SOURCE_TABLE; + +/// +/// AEST Node structure. +/// +typedef struct { + /// Node type: + /// 0x00 - Processor error node + /// 0x01 - Memory error node + /// 0x02 - SMMU error node + /// 0x03 - Vendor-defined error node + /// 0x04 - GIC error node + UINT8 Type; + + /// Length of structure in bytes. + UINT16 Length; + + /// Reserved - Must be zero. + UINT8 Reserved; + + /// Offset from the start of the node to node-specific data. + UINT32 DataOffset; + + /// Offset from the start of the node to the node interface structure. + UINT32 InterfaceOffset; + + /// Offset from the start of the node to node interrupt array. + UINT32 InterruptArrayOffset; + + /// Number of entries in the interrupt array. + UINT32 InterruptArrayCount; + + // Generic node data + + /// The timestamp frequency of the counter in Hz. + UINT64 TimestampRate; + + /// Reserved - Must be zero. + UINT64 Reserved1; + + /// The rate in Hz at which the Error Generation Counter decrements. + UINT64 ErrorInjectionCountdownRate; +} EFI_ACPI_AEST_NODE_STRUCT; + +// AEST Node type definitions +#define EFI_ACPI_AEST_NODE_TYPE_PROCESSOR 0x0 +#define EFI_ACPI_AEST_NODE_TYPE_MEMORY 0x1 +#define EFI_ACPI_AEST_NODE_TYPE_SMMU 0x2 +#define EFI_ACPI_AEST_NODE_TYPE_VENDOR_DEFINED 0x3 +#define EFI_ACPI_AEST_NODE_TYPE_GIC 0x4 + +/// +/// AEST Node Interface structure. +/// +typedef struct { + /// Interface type: + /// 0x0 - System register (SR) + /// 0x1 - Memory mapped (MMIO) + UINT8 Type; + + /// Reserved - Must be zero. + UINT8 Reserved[3]; + + /// AEST node interface flags. + UINT32 Flags; + + /// Base address of error group that contains the error node. + UINT64 BaseAddress; + + /// Zero-based index of the first standard error record that + /// belongs to this node. + UINT32 StartErrorRecordIndex; + + /// Number of error records in this node including both + /// implemented and unimplemented records. + UINT32 NumberErrorRecords; + + /// A bitmap indicating the error records within this + /// node that are implemented in the current system. + UINT64 ErrorRecordImplemented; + + /// A bitmap indicating the error records within this node that + /// support error status reporting through the ERRGSR register. + UINT64 ErrorRecordStatusReportingSupported; + + /// A bitmap indicating the addressing mode used by each error + /// record within this node to populate the ERR_ADDR register. + UINT64 AddressingMode; +} EFI_ACPI_AEST_INTERFACE_STRUCT; + +// AEST Interface node type definitions. +#define EFI_ACPI_AEST_INTERFACE_TYPE_SR 0x0 +#define EFI_ACPI_AEST_INTERFACE_TYPE_MMIO 0x1 + +// AEST node interface flag definitions. +#define EFI_ACPI_AEST_INTERFACE_FLAG_PRIVATE 0 +#define EFI_ACPI_AEST_INTERFACE_FLAG_SHARED BIT0 +#define EFI_ACPI_AEST_INTERFACE_FLAG_CLEAR_MISCX BIT1 + +/// +/// AEST Node Interrupt structure. +/// +typedef struct { + /// Interrupt type: + /// 0x0 - Fault Handling Interrupt + /// 0x1 - Error Recovery Interrupt + UINT8 InterruptType; + + /// Reserved - Must be zero. + UINT8 Reserved[2]; + + /// Interrupt flags + /// Bits [31:1]: Must be zero. + /// Bit 0: + /// 0b - Interrupt is edge-triggered + /// 1b - Interrupt is level-triggered + UINT8 InterruptFlags; + + /// GSIV of interrupt, if interrupt is an SPI or a PPI. + UINT32 InterruptGsiv; + + /// If MSI is supported, then this field must be set to the + /// Identifier field of the IORT ITS Group node. + UINT8 ItsGroupRefId; + + /// Reserved - must be zero. + UINT8 Reserved1[3]; +} EFI_ACPI_AEST_INTERRUPT_STRUCT; + +// AEST Interrupt node - interrupt type defintions. +#define EFI_ACPI_AEST_INTERRUPT_TYPE_FAULT_HANDLING 0x0 +#define EFI_ACPI_AEST_INTERRUPT_TYPE_ERROR_RECOVERY 0x1 + +// AEST Interrupt node - interrupt flag defintions. +#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_EDGE 0 +#define EFI_ACPI_AEST_INTERRUPT_FLAG_TRIGGER_TYPE_LEVEL BIT0 + +/// +/// Cache Processor Resource structure. +/// +typedef struct { + /// Reference to the cache structure in the PPTT table. + UINT32 CacheRefId; + + /// Reserved + UINT32 Reserved; +} EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT; + +/// +/// TLB Processor Resource structure. +/// +typedef struct { + /// TLB level from perspective of current processor. + UINT32 TlbRefId; + + /// Reserved + UINT32 Reserved; +} EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT; + +/// +/// Processor Generic Resource structure. +/// +typedef struct { + /// Vendor-defined supplementary data. + UINT32 Data; +} EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT; + +/// +/// AEST Processor Resource union. +/// +typedef union { + /// Processor Cache resource. + EFI_ACPI_AEST_PROCESSOR_CACHE_RESOURCE_STRUCT Cache; + + /// Processor TLB resource. + EFI_ACPI_AEST_PROCESSOR_TLB_RESOURCE_STRUCT Tlb; + + /// Processor Generic resource. + EFI_ACPI_AEST_PROCESSOR_GENERIC_RESOURCE_STRUCT Generic; +} EFI_ACPI_AEST_PROCESSOR_RESOURCE; + +/// +/// AEST Processor structure. +/// +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// Processor ID of node. + UINT32 AcpiProcessorId; + + /// Resource type of the processor node. + /// 0x0 - Cache + /// 0x1 - TLB + /// 0x2 - Generic + UINT8 ResourceType; + + /// Reserved - must be zero. + UINT8 Reserved; + + /// Processor structure flags. + UINT8 Flags; + + /// Processor structure revision. + UINT8 Revision; + + /// Processor affinity descriptor for the resource that this + /// error node pertains to. + UINT64 ProcessorAffinityLevelIndicator; + + /// Processor resource + EFI_ACPI_AEST_PROCESSOR_RESOURCE Resource; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_PROCESSOR_STRUCT; + +// AEST Processor resource type definitions. +#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_CACHE 0x0 +#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_TLB 0x1 +#define EFI_ACPI_AEST_PROCESSOR_RESOURCE_TYPE_GENERIC 0x2 + +// AEST Processor flag definitions. +#define EFI_ACPI_AEST_PROCESSOR_FLAG_GLOBAL BIT0 +#define EFI_ACPI_AEST_PROCESSOR_FLAG_SHARED BIT1 + +/// +/// Memory Controller structure. +/// +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// SRAT proximity domain. + UINT32 ProximityDomain; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_MEMORY_CONTROLLER_STRUCT; + +/// +/// SMMU structure. +/// +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// Reference to the IORT table node that describes this SMMU. + UINT32 SmmuRefId; + + /// Reference to the IORT table node that is associated with the + /// sub-component within this SMMU. + UINT32 SubComponentRefId; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_SMMU_STRUCT; + +/// +/// Vendor-Defined structure. +/// +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// ACPI HID of the component. + UINT32 HardwareId; + + /// The ACPI Unique identifier of the component. + UINT32 UniqueId; + + /// Vendor-specific data, for example to identify this error source. + UINT8 VendorData[16]; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_VENDOR_DEFINED_STRUCT; + +/// +/// GIC structure. +/// +typedef struct { + /// AEST Node header + EFI_ACPI_AEST_NODE_STRUCT NodeHeader; + + /// Type of GIC interface that is associated with this error node. + /// 0x0 - GIC CPU (GICC) + /// 0x1 - GIC Distributor (GICD) + /// 0x2 - GIC Resistributor (GICR) + /// 0x3 - GIC ITS (GITS) + UINT32 InterfaceType; + + /// Identifier for the interface instance. + UINT32 GicInterfaceRefId; + + // Node Interface + // EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + + // Node Interrupt Array + // EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterruptArray[n]; +} EFI_ACPI_AEST_GIC_STRUCT; + +// AEST GIC interface type definitions. +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICC 0x0 +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICD 0x1 +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GICR 0x2 +#define EFI_ACPI_AEST_GIC_INTERFACE_TYPE_GITS 0x3 + +#pragma pack() + +#endif // ARM_ERROR_SOURCE_TABLE_H_ -- 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'