From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mx.groups.io with SMTP id smtpd.web08.11084.1604927146653598207 for ; Mon, 09 Nov 2020 05:05:47 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: huawei.com, ip: 45.249.212.190, mailfrom: cenjiahui@huawei.com) Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4CVB7D3SXmzkf2f; Mon, 9 Nov 2020 21:05:28 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Mon, 9 Nov 2020 21:05:27 +0800 From: "Jiahui Cen" To: CC: , , , , , , Jiahui Cen Subject: [PATCH v2 4/4] ArmVirtPkg: Support extra pci roots Date: Mon, 9 Nov 2020 21:05:11 +0800 Message-ID: <20201109130511.5946-5-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201109130511.5946-1-cenjiahui@huawei.com> References: <20201109130511.5946-1-cenjiahui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Yubo Miao As the implementation of extra pci roots is shared in PciHostBridgeUtilityLib, let's call PciHostBridgeExtraRoots to support it. Cc: Laszlo Ersek Cc: Ard Biesheuvel Cc: Leif Lindholm Signed-off-by: Yubo Miao Signed-off-by: Jiahui Cen --- ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf | 3 + ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 162 +++++= ++++++++------- 2 files changed, 111 insertions(+), 54 deletions(-) diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf= b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf index 97e9368c8e9f..1b0f9a2b9013 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf @@ -39,6 +39,9 @@ [LibraryClasses] DxeServicesTableLib=0D MemoryAllocationLib=0D PciPcdProducerLib=0D + PciHostBridgeLib=0D + BaseMemoryLib=0D + QemuFwCfgLib=0D PciHostBridgeUtilityLib=0D =0D [FixedPcd]=0D diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c b= /ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c index 3952f511b4d2..d33f833a5040 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c @@ -15,6 +15,11 @@ #include =0D #include =0D #include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include "Library/PciHostBridgeLib/PciHostBridge.h"=0D =0D #include =0D #include =0D @@ -304,7 +309,60 @@ ProcessPciHost ( return Status;=0D }=0D =0D -STATIC PCI_ROOT_BRIDGE mRootBridge;=0D +EFI_STATUS=0D +InitRootBridge (=0D + IN UINT64 Supports,=0D + IN UINT64 Attributes,=0D + IN UINT64 AllocAttributes,=0D + IN UINT8 RootBusNumber,=0D + IN UINT8 MaxSubBusNumber,=0D + IN PCI_ROOT_BRIDGE_APERTURE *Io,=0D + IN PCI_ROOT_BRIDGE_APERTURE *Mem,=0D + IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,=0D + IN PCI_ROOT_BRIDGE_APERTURE *PMem,=0D + IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,=0D + OUT PCI_ROOT_BRIDGE *RootBus=0D + )=0D +{=0D + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;=0D +=0D + //=0D + // Be safe if other fields are added to PCI_ROOT_BRIDGE later.=0D + //=0D + ZeroMem (RootBus, sizeof *RootBus);=0D +=0D + RootBus->Segment =3D 0;=0D + RootBus->ResourceAssigned =3D FALSE;=0D + RootBus->Supports =3D Supports;=0D + RootBus->Attributes =3D Attributes;=0D +=0D + RootBus->DmaAbove4G =3D TRUE;=0D +=0D + RootBus->AllocationAttributes =3D AllocAttributes;=0D + RootBus->Bus.Base =3D RootBusNumber;=0D + RootBus->Bus.Limit =3D MaxSubBusNumber;=0D + CopyMem (&RootBus->Io, Io, sizeof (*Io));=0D + CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));=0D + CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));=0D + CopyMem (&RootBus->PMem, PMem, sizeof (*PMem));=0D + CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G));=0D +=0D + RootBus->NoExtendedConfigSpace =3D FALSE;=0D +=0D + DevicePath =3D AllocateCopyPool (sizeof mEfiPciRootBridgeDevicePath,=0D + &mEfiPciRootBridgeDevicePath);=0D + if (DevicePath =3D=3D NULL) {=0D + DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));= =0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D + DevicePath->AcpiDevicePath.UID =3D RootBusNumber;=0D + RootBus->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;=0D +=0D + DEBUG ((EFI_D_INFO,=0D + "%a: populated root bus %d, with room for %d subordinate bus(es)\n",=0D + __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));=0D + return EFI_SUCCESS;=0D +}=0D =0D /**=0D Return all the root bridge instances in an array.=0D @@ -321,11 +379,19 @@ PciHostBridgeGetRootBridges ( UINTN *Count=0D )=0D {=0D - UINT64 IoBase, IoSize;=0D - UINT64 Mmio32Base, Mmio32Size;=0D - UINT64 Mmio64Base, Mmio64Size;=0D - UINT32 BusMin, BusMax;=0D - EFI_STATUS Status;=0D + UINT64 IoBase, IoSize;=0D + UINT64 Mmio32Base, Mmio32Size;=0D + UINT64 Mmio64Base, Mmio64Size;=0D + UINT32 BusMin, BusMax;=0D + PCI_ROOT_BRIDGE *Bridges;=0D + UINT64 Attributes;=0D + UINT64 AllocationAttributes;=0D + EFI_STATUS Status;=0D + PCI_ROOT_BRIDGE_APERTURE Io;=0D + PCI_ROOT_BRIDGE_APERTURE PMem;=0D + PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;=0D + PCI_ROOT_BRIDGE_APERTURE Mem;=0D + PCI_ROOT_BRIDGE_APERTURE MemAbove4G;=0D =0D if (PcdGet64 (PcdPciExpressBaseAddress) =3D=3D 0) {=0D DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__)= );=0D @@ -343,33 +409,27 @@ PciHostBridgeGetRootBridges ( return NULL;=0D }=0D =0D - *Count =3D 1;=0D + ZeroMem (&Io, sizeof (Io));=0D + ZeroMem (&Mem, sizeof (Mem));=0D + ZeroMem (&MemAbove4G, sizeof (MemAbove4G));=0D =0D - mRootBridge.Segment =3D 0;=0D - mRootBridge.Supports =3D EFI_PCI_ATTRIBUTE_ISA_IO_16 |=0D - EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO= |=0D - EFI_PCI_ATTRIBUTE_VGA_IO_16 |=0D - EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;= =0D - mRootBridge.Attributes =3D mRootBridge.Supports;=0D + Attributes =3D EFI_PCI_ATTRIBUTE_ISA_IO_16 |=0D + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |=0D + EFI_PCI_ATTRIBUTE_VGA_IO_16 |=0D + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;=0D =0D - mRootBridge.DmaAbove4G =3D TRUE;=0D - mRootBridge.NoExtendedConfigSpace =3D FALSE;=0D - mRootBridge.ResourceAssigned =3D FALSE;=0D + AllocationAttributes =3D EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;=0D =0D - mRootBridge.AllocationAttributes =3D EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PM= EM;=0D -=0D - mRootBridge.Bus.Base =3D BusMin;=0D - mRootBridge.Bus.Limit =3D BusMax;=0D - mRootBridge.Io.Base =3D IoBase;=0D - mRootBridge.Io.Limit =3D IoBase + IoSize - 1;=0D - mRootBridge.Mem.Base =3D Mmio32Base;=0D - mRootBridge.Mem.Limit =3D Mmio32Base + Mmio32Size - 1;=0D + Io.Base =3D IoBase;=0D + Io.Limit =3D IoBase + IoSize - 1;=0D + Mem.Base =3D Mmio32Base;=0D + Mem.Limit =3D Mmio32Base + Mmio32Size - 1;=0D =0D if (sizeof (UINTN) =3D=3D sizeof (UINT64)) {=0D - mRootBridge.MemAbove4G.Base =3D Mmio64Base;=0D - mRootBridge.MemAbove4G.Limit =3D Mmio64Base + Mmio64Size - 1;=0D + MemAbove4G.Base =3D Mmio64Base;=0D + MemAbove4G.Limit =3D Mmio64Base + Mmio64Size - 1;=0D if (Mmio64Size > 0) {=0D - mRootBridge.AllocationAttributes |=3D EFI_PCI_HOST_BRIDGE_MEM64_DECO= DE;=0D + AllocationAttributes |=3D EFI_PCI_HOST_BRIDGE_MEM64_DECODE;=0D }=0D } else {=0D //=0D @@ -378,37 +438,31 @@ PciHostBridgeGetRootBridges ( // BARs unless they are allocated below 4 GB. So ignore the range abov= e=0D // 4 GB in this case.=0D //=0D - mRootBridge.MemAbove4G.Base =3D MAX_UINT64;=0D - mRootBridge.MemAbove4G.Limit =3D 0;=0D + MemAbove4G.Base =3D MAX_UINT64;=0D + MemAbove4G.Limit =3D 0;=0D }=0D =0D //=0D // No separate ranges for prefetchable and non-prefetchable BARs=0D //=0D - mRootBridge.PMem.Base =3D MAX_UINT64;=0D - mRootBridge.PMem.Limit =3D 0;=0D - mRootBridge.PMemAbove4G.Base =3D MAX_UINT64;=0D - mRootBridge.PMemAbove4G.Limit =3D 0;=0D + PMem.Base =3D MAX_UINT64;=0D + PMem.Limit =3D 0;=0D + PMemAbove4G.Base =3D MAX_UINT64;=0D + PMemAbove4G.Limit =3D 0;=0D =0D - mRootBridge.DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridg= eDevicePath;=0D -=0D - return &mRootBridge;=0D + Bridges =3D PciHostBridgeExtraRoots (=0D + Count,=0D + PMem,=0D + PMemAbove4G,=0D + BusMax,=0D + Attributes,=0D + AllocationAttributes,=0D + Io,=0D + Mem,=0D + MemAbove4G=0D + );=0D + if (Bridges) {=0D + return Bridges;=0D + }=0D + return NULL;=0D }=0D -=0D -/**=0D - Free the root bridge instances array returned from=0D - PciHostBridgeGetRootBridges().=0D -=0D - @param Bridges The root bridge instances array.=0D - @param Count The count of the array.=0D -**/=0D -VOID=0D -EFIAPI=0D -PciHostBridgeFreeRootBridges (=0D - PCI_ROOT_BRIDGE *Bridges,=0D - UINTN Count=0D - )=0D -{=0D - ASSERT (Count =3D=3D 1);=0D -}=0D -=0D --=20 2.28.0