From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web08.22208.1604975079377218235 for ; Mon, 09 Nov 2020 18:24:39 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: w.sheng@intel.com) IronPort-SDR: 19YNtBKVVww6xV5wW472/9lbIe9zoFRoXq62iIOjSLxhT9xw66kZTaFwxQVhrnXWRvGL8UJQVB QLMo0R4tvvfA== X-IronPort-AV: E=McAfee;i="6000,8403,9800"; a="149755499" X-IronPort-AV: E=Sophos;i="5.77,465,1596524400"; d="scan'208";a="149755499" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2020 18:24:37 -0800 IronPort-SDR: zz15V3UTN7VrXYZlRKokoAI1uPDFqHu7ch20gtuGYMiA7SzdIfYMH5iwf7U2F/AfFy6zFQRUAT uef8GamiF11w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,465,1596524400"; d="scan'208";a="541136704" Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.46]) by orsmga005.jf.intel.com with ESMTP; 09 Nov 2020 18:24:34 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar , Jiewen Yao Subject: [PATCH v6 0/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reflect page table depth with page table address Date: Tue, 10 Nov 2020 10:24:28 +0800 Message-Id: <20201110022430.19560-1-w.sheng@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 When trying to get page table base, if mInternalCr3 is zero, it will use the page table from CR3, and reflect the page table depth by CR4 LA57 bit. If mInternalCr3 is non zero, it will use the page table from mInternalCr3 and reflect the page table depth of mInternalCr3 at same time. In the case of X64, we use m5LevelPagingNeeded to reflect the depth of the page table. And in the case of IA32, it will not the page table depth information. This patch is a bug fix when enable CET feature with 5 level paging. The SMM page tables are allocated / initialized in PiCpuSmmEntry(). When CET is enabled, PiCpuSmmEntry() must further modify the attribute of shadow stack pages. This page table is not set to CR3 in PiCpuSmmEntry(). So the page table base address is set to mInternalCr3 for modifty the page table attribute. It could not use CR4 LA57 bit to reflect the page table depth for mInternalCr3. So we create a architecture-specific implementation GetPageTable() with 2 output parameters. One parameter is used to output the page table address. Another parameter is used to reflect if it is 5 level paging or not. Correct the Cr3 typo REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015 Signed-off-by: Sheng Wei Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Jiewen Yao Sheng Wei (2): UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo UefiCpuPkg/PiSmmCpuDxeSmm: Reflect page table depth with page table address UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 24 ++++++++++++- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 12 ++++--- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 33 +++++------------- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 40 +++++++++++++++++++--- 4 files changed, 73 insertions(+), 36 deletions(-) -- 2.16.2.windows.1