[edk2-platform][PATCH 0/3] Generalise UART GSI in SbsaQemu

[edk2-platform][PATCH 0/3] Generalise UART GSI in SbsaQemu

[Tomas Pilar (tpilar)]

The serial port global system interrupt is descibed in various
ACPI tables. The library that generates these for the SbsaQemu
platform hardcodes the value for the GSI. This pachset generalises
the process using a PCD defined in the platform DSC file.

This fixes broken keyboard support in a serial console when booting linux
on such a platform with misaligned UART GSI.

Tomas Pilar (4):
  Silicon/Qemu: Fix PCD numbering in SbsaQemu
  Silicon/Qemu: Add PCD for Serial port GSI
  Platform/Qemu: Specify UART GSI in SbsaQemu
  Platform/Nuvia: Specify GSI for UART in Comet

 Platform/Nuvia/CometPkg/CometPkg.dsc            | 3 +++
 Platform/Qemu/SbsaQemu/SbsaQemu.dsc             | 3 +++
 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 +
 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl       | 2 +-
 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc      | 2 +-
 Silicon/Qemu/SbsaQemu/SbsaQemu.dec              | 5 ++++-
 6 files changed, 13 insertions(+), 3 deletions(-)

-- 
2.25.1

[edk2-platform][PATCH 1/3] Silicon/Qemu: Fix PCD numbering in SbsaQemu

[Tomas Pilar (tpilar)]

Fix the PCD numbering for PcdPciExpressBarLimit to be sequential.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
---
 Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
index 1bc3e35b9b..2831781c4e 100644
--- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
@@ -45,7 +45,7 @@
   # PCDs complementing gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
   # BarLimit = BaseAddress + Size - 1
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000|UINT64|0x00000009
-  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF|UINT64|0x00000010
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF|UINT64|0x000000a
 
 [PcdsDynamic.common]
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000100
-- 
2.25.1

Re: [edk2-platform][PATCH 1/3] Silicon/Qemu: Fix PCD numbering in SbsaQemu

[Tanmay Jagdale]

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Hi Tomas,

On Thu, 19 Nov 2020 at 20:28, Tomas Pilar <tomas@nuviainc.com> wrote:

> Fix the PCD numbering for PcdPciExpressBarLimit to be sequential.
>
> Cc: Leif Lindholm <leif@nuviainc.com>
> Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
> Cc: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
>
Tested this patch series and didn't face any issues.

Tested-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>

> ---
>  Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> index 1bc3e35b9b..2831781c4e 100644
> --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
> @@ -45,7 +45,7 @@
>    # PCDs complementing gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
>    # BarLimit = BaseAddress + Size - 1
>
>  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000|UINT64|0x00000009
> -
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF|UINT64|0x00000010
> +
> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF|UINT64|0x000000a
>
>  [PcdsDynamic.common]
>
>  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000100
> --
> 2.25.1
>

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[edk2-platform][PATCH 2/3] Silicon/Qemu: Add PCD for Serial port GSI

[Tomas Pilar (tpilar)]

The UART specified in the SPCR table needs a GSI assigned
to it. The EDK2 will not use it because it does not use
interrupts, but it is necessary for OS boot.

Parametrize the value of the GSI assigned to the UART using
a PCD so that it might be specified in the platform DSC file.

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
---
 Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 +
 Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl       | 2 +-
 Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc      | 2 +-
 Silicon/Qemu/SbsaQemu/SbsaQemu.dec              | 3 +++
 4 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
index 1ce7e12890..10ece22d9d 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf
@@ -68,6 +68,7 @@
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSerialGlobalSystemInterrupt
 
   gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
 
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
index 307e031a7b..f5a709083e 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl
@@ -36,7 +36,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "LINARO", "SBSAQEMU",
         Memory32Fixed (ReadWrite,
                        FixedPcdGet32 (PcdSerialRegisterBase),
                        0x00001000)
-        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 }
+        Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { FixedPcdGet32 (PcdSerialGlobalSystemInterrupt) }
       })
     }
 
diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
index 0c3b627fc7..ff787bd8bf 100644
--- a/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
+++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Spcr.aslc
@@ -29,7 +29,7 @@ STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
   },
   EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
   0,                      /* Irq */
-  33,                     /* GlobalSystemInterrupt */
+  FixedPcdGet32 (PcdSerialGlobalSystemInterrupt),
   EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
   EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
   EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
index 2831781c4e..b53c5b82e9 100644
--- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
+++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec
@@ -47,6 +47,9 @@
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000|UINT64|0x00000009
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF|UINT64|0x000000a
 
+  # GSI for the UART. Recall that GSIs are offset by 32.
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSerialGlobalSystemInterrupt|33|UINT32|0x0000000b
+
 [PcdsDynamic.common]
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount|0x1|UINT32|0x00000100
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount|0x1|UINT32|0x00000101
-- 
2.25.1

[edk2-platform][PATCH 3/3] Platform/Qemu: Specify UART GSI in SbsaQemu

[Tomas Pilar (tpilar)]

Specify the Serial port Global System Interrupt
in the SbsaQemu platform to be 33 (1 + 32).

Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Signed-off-by: Tomas Pilar <tomas@nuviainc.com>
---
 Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 49fde83d13..2d9654ca89 100644
--- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
+++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
@@ -472,6 +472,9 @@ DEFINE NETWORK_HTTP_BOOT_ENABLE       = FALSE
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarSize|0x10000000
   gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdPciExpressBarLimit|0xFFFFFFFF
 
+  # GSI are shifted by 32, thus IRQ=1
+  gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSerialGlobalSystemInterrupt|33
+
   gArmTokenSpaceGuid.PcdPciIoTranslation|0x7fff0000
   gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
   gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0
-- 
2.25.1