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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id d29sm190876lfj.51.2020.11.19.19.11.42 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Nov 2020 19:11:43 -0800 (PST) From: "Marcin Wojtas" To: devel@edk2.groups.io Cc: leif@nuviainc.com, ard.biesheuvel@arm.com, mw@semihalf.com, jaz@semihalf.com Subject: [platforms: PATCH v2] SolidRun/Armada80x0McBin: Introduce SD/MMC ACPI description Date: Fri, 20 Nov 2020 04:11:12 +0100 Message-Id: <20201120031112.24266-1-mw@semihalf.com> X-Mailer: git-send-email 2.29.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This patch adds a new description of the board's SD/MMC interfaces in DSDT table that can work with the newly introduced support in Linux. Remaining Armada7k8k / CN913x platforms will follow after this binding is accepted. Signed-off-by: Marcin Wojtas --- Changelog: v1->v2 * Drop 'compatible' property from MMC0 node * Use dedicated _HID for each variant Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 59 ++++++= ++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl= b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl index 7e9e361988..9e771afc98 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -86,6 +86,65 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) })=0D }=0D =0D + Device (MMC0)=0D + {=0D + Name (_HID, "MRVL0002") // _HID: Hardware ID=0D + Name (_UID, 0x00) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF06E0000, // Address Base (MMIO)=0D + 0x00000300, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + 48=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "clock-frequency", 400000000 },=0D + Package () { "bus-width", 8 },=0D + Package () { "marvell,xenon-phy-slow-mode", 0x1 },=0D + Package () { "no-1-8-v", 0x1 },=0D + Package () { "no-sd", 0x1 },=0D + Package () { "no-sdio", 0x1 },=0D + Package () { "non-removable", 0x1 },=0D + }=0D + })=0D + }=0D +=0D + Device (MMC1)=0D + {=0D + Name (_HID, "MRVL0004") // _HID: Hardware ID=0D + Name (_UID, 0x01) // _UID: Unique ID=0D + Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D +=0D + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D + {=0D + Memory32Fixed (ReadWrite,=0D + 0xF2780000, // Address Base (MMIO)=0D + 0x00000300, // Address Length=0D + )=0D + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,= ,, )=0D + {=0D + CP_GIC_SPI_CP0_SDMMC=0D + }=0D + })=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () { "clock-frequency", 400000000 },=0D + Package () { "bus-width", 4 },=0D + Package () { "broken-cd", 0x1 },=0D + Package () { "no-1-8-v", 0x1 },=0D + }=0D + })=0D + }=0D +=0D Device (XHC0)=0D {=0D Name (_HID, "PNP0D10") // _HID: Hardware ID=0D --=20 2.29.0