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[82.27.183.148]) by smtp.gmail.com with ESMTPSA id p9sm4942639wrw.29.2020.11.25.04.56.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Nov 2020 04:56:01 -0800 (PST) From: "Leif Lindholm" To: devel@edk2.groups.io Cc: Ard Biesheuvel Subject: [PATCH edk2-platforms 01/15] Silicon/AMD: update Styx to use PcdSet*S APIs Date: Wed, 25 Nov 2020 12:55:45 +0000 Message-Id: <20201125125559.11631-2-leif@nuviainc.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201125125559.11631-1-leif@nuviainc.com> References: <20201125125559.11631-1-leif@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The non-status reporting PcdSet functions were deprecated and have now been removed. Update Styx code to assert on error status. Cc: Ard Biesheuvel Signed-off-by: Leif Lindholm --- .../Styx/Drivers/PlatInitPei/PlatInitPei.c | 11 ++++++---- .../Library/MemoryInitPei/MemoryInitPeiLib.c | 20 +++++++++++-------- 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c index 4de26404a8a7..3f359ffbd2d8 100644 --- a/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c +++ b/Silicon/AMD/Styx/Drivers/PlatInitPei/PlatInitPei.c @@ -111,7 +111,7 @@ PlatInitPeiEntryPoint ( IN CONST EFI_PEI_SERVICES **PeiServices ) { - EFI_STATUS Status = EFI_SUCCESS; + EFI_STATUS Status; AMD_MEMORY_RANGE_DESCRIPTOR IscpMemDescriptor = {0}; ISCP_FUSE_INFO IscpFuseInfo = {0}; ISCP_CPU_RESET_INFO CpuResetInfo = {0}; @@ -124,7 +124,8 @@ PlatInitPeiEntryPoint ( DEBUG ((EFI_D_ERROR, "PlatInit PEIM Loaded\n")); // CPUID - PcdSet32 (PcdSocCpuId, *CpuIdReg); + Status = PcdSet32S (PcdSocCpuId, *CpuIdReg); + ASSERT_EFI_ERROR (Status); DEBUG ((EFI_D_ERROR, "SocCpuId = 0x%X\n", PcdGet32 (PcdSocCpuId))); // Update core count based on PCD option @@ -186,7 +187,8 @@ PlatInitPeiEntryPoint ( // Update SocCoreCount on Dynamic PCD if (PcdGet32 (PcdSocCoreCount) != mAmdCoreCount) { - PcdSet32 (PcdSocCoreCount, mAmdCoreCount); + Status = PcdSet32S (PcdSocCoreCount, mAmdCoreCount); + ASSERT_EFI_ERROR (Status); } DEBUG ((EFI_D_ERROR, "SocCoreCount = %d\n", PcdGet32 (PcdSocCoreCount))); @@ -201,7 +203,8 @@ PlatInitPeiEntryPoint ( // Update SystemMemorySize on Dynamic PCD if (IscpMemDescriptor.Size0) { - PcdSet64 (PcdSystemMemorySize, IscpMemDescriptor.Size0); + Status = PcdSet64S (PcdSystemMemorySize, IscpMemDescriptor.Size0); + ASSERT_EFI_ERROR (Status); } if (IscpMemDescriptor.Size0 == 0) { DEBUG ((EFI_D_ERROR, "Warning: Could not get SystemMemorySize via ISCP, using default value.\n")); diff --git a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c index 0cbd960f30fb..c047d7444620 100644 --- a/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c +++ b/Silicon/AMD/Styx/Library/MemoryInitPei/MemoryInitPeiLib.c @@ -55,8 +55,9 @@ MoveNvStoreImage ( VOID ) { - VOID *OldBase, *NewBase; - UINTN Size; + VOID *OldBase, *NewBase; + UINTN Size; + EFI_STATUS Status; // // Move the in-memory image of the NV store firmware volume to a dynamically @@ -77,14 +78,17 @@ MoveNvStoreImage ( DEBUG ((EFI_D_INFO, "%a: Relocating NV store FV from %p to %p\n", __FUNCTION__, OldBase, NewBase)); - PcdSet64 (PcdFlashNvStorageVariableBase64, (UINT64)NewBase); + Status = PcdSet64S (PcdFlashNvStorageVariableBase64, (UINT64)NewBase); + ASSERT_EFI_ERROR (Status); - PcdSet64 (PcdFlashNvStorageFtwWorkingBase64, (UINT64)NewBase + - FixedPcdGet32 (PcdFlashNvStorageVariableSize)); + Status = PcdSet64S (PcdFlashNvStorageFtwWorkingBase64, + (UINT64)NewBase + FixedPcdGet32 (PcdFlashNvStorageVariableSize)); + ASSERT_EFI_ERROR (Status); - PcdSet64 (PcdFlashNvStorageFtwSpareBase64, (UINT64)NewBase + - FixedPcdGet32 (PcdFlashNvStorageVariableSize) + - FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize)); + Status = PcdSet64S (PcdFlashNvStorageFtwSpareBase64, (UINT64)NewBase + + FixedPcdGet32 (PcdFlashNvStorageVariableSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize)); + ASSERT_EFI_ERROR (Status); } /*++ -- 2.20.1