From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f194.google.com (mail-pf1-f194.google.com [209.85.210.194]) by mx.groups.io with SMTP id smtpd.web10.2925.1606782897393506623 for ; Mon, 30 Nov 2020 16:34:57 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=B9gbvC8L; spf=pass (domain: nuviainc.com, ip: 209.85.210.194, mailfrom: rebecca@nuviainc.com) Received: by mail-pf1-f194.google.com with SMTP id e8so11539430pfh.2 for ; Mon, 30 Nov 2020 16:34:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ltUxekI/QdkPRB8IumcAnuoNrPiUS4MHBRfnKEG3IY0=; b=B9gbvC8LexnPzomeSVNzTZYhIIwJsBQUQwZnmg+GNr/Rr+oZhv15lqpAosTGKL0Fsz 8w6rk5ZTvXmj4q6oj2O7aeC2iObgkyJIIn9+Ocyd+T87/peD4Q6A5ZrojGeTpDjdPfmN PavsegFEzp2ir9A0VDpc4mEE31lhsfuo5CmQKi0z8Oo1fnu78jBAxiZwj+oK2Dc5jnTv t3eZSgSyizyWOUDq+nfIV94MhCmb+6ye+im9qqoLEVDZMM4Po3aHbMBtejoE0yP0uALd 1LhYPfsCowisR5G/CoqCFFzrhrspsq9YY0g6tzttpGvZ+n/GucRAvGrIbnRPhnC+TCI8 sdvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ltUxekI/QdkPRB8IumcAnuoNrPiUS4MHBRfnKEG3IY0=; b=Lj2IPi3FZOjnYYssB6Zk8Pk6UYnDmMCv8c+Hzl5MMvq6l8pr4NVl4YftBTx7Vf8DTp m/87YJWndPOblpwsqGJ3pCEO3VXPj5lcDfwqqp0zCipYlnZm+qvCIld6jw+QZffjSA0Z gXMNVer9X0ApA9YCJhq6g/hczhjwZiVP55yY8lY4N4BIJH2OnizvKeyYbqTUrJ4v8mTS RQsaoAT5CsZPODIpf1mWlxtC/79pqHOW5AnMGM9lvXQRXJzCnR28VPcsmD2DQEsb2qWn xeU5RonO7THImWh4sTK/fr9uZEEB254Pha0ilTMy+r1KnGDkYjYTz5IYrxmiedUQeQjR YNvQ== X-Gm-Message-State: AOAM5324NdbqfsgUpqpJvU88gRJdbWW2FPMNco9DdkAhnSpPrb45/aho cJq40CHQ8I53a/q4NayfqokMTj2Z3I4rTl6/frb+O2NBbNDfvNms/gN7S2S/X/ksW9ShI6s/goM fkaIQfAz7xcFlxoHYRmb1x3ZRCeDL2FLu1lY7FrdHPTFfRxOAu3I0b6KXRBAdAswqyhLFwT94 X-Google-Smtp-Source: ABdhPJx4EqcF9tHYI94lkfwnKlT0XulHmMpf+desB6PbmZqXthQj1Fe39lnCgMs5+8FjvIeOiRv1Sw== X-Received: by 2002:a62:fb01:0:b029:19a:f68a:49bf with SMTP id x1-20020a62fb010000b029019af68a49bfmr256363pfm.64.1606782896448; Mon, 30 Nov 2020 16:34:56 -0800 (PST) Return-Path: Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id 22sm57899pjb.40.2020.11.30.16.34.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 16:34:55 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel , Sami Mujawar Subject: [PATCH v4 08/11] ArmPkg: Update ArmLibPrivate.h with cache register definitions Date: Mon, 30 Nov 2020 17:33:55 -0700 Message-Id: <20201201003358.8780-9-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201201003358.8780-1-rebecca@nuviainc.com> References: <20201201003358.8780-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Update the cache definitions in ArmLibPrivate.h based on current ARMv8 documentation. Signed-off-by: Rebecca Cran --- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 91 ++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h index 5eecbc0e1c43..fb1e2cc6b2ac 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -1,5 +1,7 @@ /** @file + ArmLibPrivate.h + Copyright (c) 2020, NUVIA Inc. All rights reserved.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -50,6 +52,95 @@ #define CACHE_ARCHITECTURE_UNIFIED (0UL) #define CACHE_ARCHITECTURE_SEPARATE (1UL) + +/// Defines the structure of the CSSELR (Cache Size Selection) register +typedef union { + struct { + UINT32 InD :1; ///< Instruction not Data bit + UINT32 Level :3; ///< Cache level (zero based) + UINT32 TnD :1; ///< Allocation not Data bit + UINT32 Reserved :27; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSELR_DATA; + +/// The cache type values for the InD field of the CSSELR register +typedef enum +{ + /// Select the data or unified cache + CsselrCacheTypeDataOrUnified = 0, + /// Select the instruction cache + CsselrCacheTypeInstruction, + CsselrCacheTypeMax +} CSSELR_CACHE_TYPE; + +/// Defines the structure of the CCSIDR (Current Cache Size ID) register +typedef union { + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) + UINT64 Associativity :10; ///< Associativity - 1 + UINT64 NumSets :15; ///< Number of sets in the cache -1 + UINT64 Unknown :4; ///< Reserved, UNKNOWN + UINT64 Reserved :32; ///< Reserved, RES0 + } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported. + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) + UINT64 Associativity :21; ///< Associativity - 1 + UINT64 Reserved1 :8; ///< Reserved, RES0 + UINT64 NumSets :24; ///< Number of sets in the cache -1 + UINT64 Reserved2 :8; ///< Reserved, RES0 + } BitsCcidx; ///< Bitfield definition of the register when FEAT_IDX is supported. + UINT64 Data; ///< The entire 64-bit value +} CCSIDR_DATA; + +/// Defines the structure of the AARCH32 CCSIDR2 register. +typedef union { + struct { + UINT32 NumSets :24; ///< Number of sets in the cache - 1 + UINT32 Reserved :8; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSIDR2_DATA; + +/** Defines the structure of the CLIDR (Cache Level ID) register. + * + * The lower 32 bits are the same for both AARCH32 and AARCH64 + * so we can use the same structure for both. +**/ +typedef union { + struct { + UINT32 Ctype1 : 3; ///< Level 1 cache type + UINT32 Ctype2 : 3; ///< Level 2 cache type + UINT32 Ctype3 : 3; ///< Level 3 cache type + UINT32 Ctype4 : 3; ///< Level 4 cache type + UINT32 Ctype5 : 3; ///< Level 5 cache type + UINT32 Ctype6 : 3; ///< Level 6 cache type + UINT32 Ctype7 : 3; ///< Level 7 cache type + UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable + UINT32 LoC : 3; ///< Level of Coherency + UINT32 LoUU : 3; ///< Level of Unification Uniprocessor + UINT32 Icb : 3; ///< Inner Cache Boundary + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CLIDR_DATA; + +/// The cache types reported in the CLIDR register. +typedef enum { + /// No cache is present + ClidrCacheTypeNone = 0, + /// There is only an instruction cache + ClidrCacheTypeInstructionOnly, + /// There is only a data cache + ClidrCacheTypeDataOnly, + /// There are separate data and instruction caches + ClidrCacheTypeSeparate, + /// There is a unified cache + ClidrCacheTypeUnified, + ClidrCacheTypeMax +} CLIDR_CACHE_TYPE; + +#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * level)) & 0b111) + VOID CPSRMaskInsert ( IN UINT32 Mask, -- 2.26.2