From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (NAM12-MW2-obe.outbound.protection.outlook.com [40.107.244.133]) by mx.groups.io with SMTP id smtpd.web10.5501.1606969788086515825 for ; Wed, 02 Dec 2020 20:29:48 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@os.amperecomputing.com header.s=selector2 header.b=nd2orfma; spf=pass (domain: os.amperecomputing.com, ip: 40.107.244.133, mailfrom: vunguyen@os.amperecomputing.com) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=l79iIaKQ7VtggWzBp7lHh/pcyOr1VMY5KwUkeRrSDEyZ9qHIdePY14Bi/hK+//54cTZYu4Kur9N+qb53F4slioY0YJyGy2c4ODAeBxbIuSFbdDZeV9sjwP6vpAuyDc926uweaPrPCA6kPzIcFFtUSY1hRk4k3qKK2F9VOUtz3CPKBh9ct/qnXIJZKYUjBEsnrZVhzuQpX5lI4ikUKfZfnVcvDLuqz8nUhU11rGL0EiJ6PaBzcxkdCK9slrbn4nqjtzPMs9wFPwgJrX0EoJJp/DJEcbpLnOgFbUSzBYBLr8DeAXDe82PM4EQ2IMi9KT9YSQFgLaL+mfwWwcKYQhAHLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cuQ5K+g/Z1l3k+BctAhbfjZJAgRWbC7qNeZMHjzNmOs=; b=S9bpi73hrnywZDVgBNPSvn8OrhjCIQ5JRitL0i+pXwyDyKJstVVBDZo0VeCCYj5/B0D0W0cooH+fYSrw8cE3SgTc5eEsDf4TKAMpFmYum3gCzLxxwWi8t4aXDaOJCbl77DIyBNLsr/wNJkbTJippy+Ao0919MSNwszn9NtDay9rMu+/PCuzK5C59U3iTgtl8uozPNIq6P756S1NeowJn9nAxiwWNzkb2M9tzBFRlPe6i9+c0wr2pTkQdpnfXdGEkrq9DNvifMnLN8BrxYkKaq5/Qddr3XNT9qye2vh3POtytS1SAysct+15el+FKUy0qHrh4A72X+sLOMn1XHRYsxw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=os.amperecomputing.com; dmarc=pass action=none header.from=os.amperecomputing.com; dkim=pass header.d=os.amperecomputing.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=os.amperecomputing.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cuQ5K+g/Z1l3k+BctAhbfjZJAgRWbC7qNeZMHjzNmOs=; b=nd2orfmaRsf3QSW04EoWlUnXwZ0FAVnp9oi5M8nj/Nzx3/njgA5XcNmb9Ka1dxRY8STaqNt1ZnRlx3RXHi2NxH5/ShtWk4lEmyKAQ9nCDn1VPCcTexzBM2P4WyDUPMNFbyadBhMduc+d4YfoxtsUJLFKMPFv4np3S6sh3e6qc9Y= Authentication-Results: edk2.groups.io; dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=os.amperecomputing.com; Received: from CH2PR01MB6007.prod.exchangelabs.com (2603:10b6:610:47::29) by CH2PR01MB6040.prod.exchangelabs.com (2603:10b6:610:46::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3611.25; Thu, 3 Dec 2020 04:29:46 +0000 Received: from CH2PR01MB6007.prod.exchangelabs.com ([fe80::a5bf:cd91:769d:a34b]) by CH2PR01MB6007.prod.exchangelabs.com ([fe80::a5bf:cd91:769d:a34b%5]) with mapi id 15.20.3632.017; Thu, 3 Dec 2020 04:29:46 +0000 From: "Vu Nguyen" To: devel@edk2.groups.io Cc: patches@amperecomputing.com, Leif Lindholm , Ard Biesheuvel , Nate DeSimone Subject: [edk2-non-osi][PATCH v2 1/2] AmpereAltraBinPkg: Add PciePhyLib library and header Date: Thu, 3 Dec 2020 11:29:23 +0700 Message-Id: <20201203042924.28557-2-vunguyen@os.amperecomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201203042924.28557-1-vunguyen@os.amperecomputing.com> References: <20201203042924.28557-1-vunguyen@os.amperecomputing.com> X-Originating-IP: [118.69.219.201] X-ClientProxiedBy: HK2PR03CA0044.apcprd03.prod.outlook.com (2603:1096:202:17::14) To CH2PR01MB6007.prod.exchangelabs.com (2603:10b6:610:47::29) Return-Path: vunguyen@os.amperecomputing.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sw003.amperecomputing.com (118.69.219.201) by HK2PR03CA0044.apcprd03.prod.outlook.com (2603:1096:202:17::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3654.5 via Frontend Transport; Thu, 3 Dec 2020 04:29:44 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bcd49a67-3a43-4a55-6a10-08d89744105a X-MS-TrafficTypeDiagnostic: CH2PR01MB6040: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vNR5ncjwzK2vIEt3woU/p+cKwfE+NpBzZuhLrTKe1o/DRV93GbCFE3yt3hcQluP/aPVd+ODjG3KOr8NNjjgGK1grD2qWOsZX0iOo70QdvQsZpT5qtP1N6ZVr3tlwuAibTz4N2b9YyarZdy1ACVxmMp5XgQSW0SIMCV1cWXTNmU2nKhtwognWlViBYjYDCw1hBW6TZfHGhCfoQ0L/qtStDspXP51oKH3XvutrCP7ODGPKOSCT5AJ2s3jbcH96QmwvowQXknGqYGwSUODB6/o35C7whWwlzm8rtSXr7P71eZumpWXXa2GxbHoHtgBoP1nwbF6r9W/57gTl5Q9GbAd4iw== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CH2PR01MB6007.prod.exchangelabs.com;PTR:;CAT:NONE;SFS:(4636009)(366004)(396003)(376002)(39850400004)(346002)(136003)(52116002)(86362001)(6506007)(54906003)(6666004)(2906002)(6486002)(2616005)(316002)(6916009)(956004)(6512007)(19627235002)(8676002)(8936002)(4326008)(26005)(5660300002)(83380400001)(66476007)(16526019)(66556008)(186003)(66946007)(1076003)(478600001);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?VSbdhG9ArihlbYLTVWK9NRlyV5ffLYLJpavQsM7mtyH8iIt22KzfRpvWMk3q?= =?us-ascii?Q?tpe1gnd99jyrS7LF7vIrBJI9ZZeFk0+MEwg8uIsUva8rQHF/W5BNFByQ6iPR?= =?us-ascii?Q?Uhy65KNBGnfNOEJveZlS0vtgLqTnFhXd4f8+Ai5tG9Svq2zse+rj5bLR8ZBL?= =?us-ascii?Q?u7r7MnGL0yMrCXZra05DRMJHE6/7z5DHvJFqzTxPn1NAfc5bFOVBoqQdIgFu?= =?us-ascii?Q?sWAaCYllacIeqrIhM968xFzi/ZnkDanv30V7CuB3p1EcxHF3CG+leg5tZ4PX?= =?us-ascii?Q?RUXmYSwwPZAmND8Y2ozkoiGp5p+tM1L/yb7efeweFmnH3QCV8GbZgprkwSRI?= =?us-ascii?Q?K8vvHdS1m/iQmzqLNVvzZP6FNIja/5LKV6Ct26QkOwvSZuwIqxbgKWsCxZpH?= =?us-ascii?Q?+uROtzEli2cSdYZrcHCQry0Vp1r7eH475bBOYbmKafU2UNc+SjRnrQ1zVJNZ?= =?us-ascii?Q?rlx3kGmyNxIPcpIXSfn4Nnv3P/DNil/sAE6VnpL1WUU3DT4PJi2hRqJwYvUe?= =?us-ascii?Q?biRZuENc9c/ZRUC6nXQ8UiEOJPYyGQHp7tlZe+BHZGMxi7yF1LNG4wLuwX/v?= =?us-ascii?Q?oQGLq3PjJJLwRtL/gWlyBeWlggxY9lcgX5irz11Wh3wvjSbGxuvxP2RLy72X?= =?us-ascii?Q?uzspjaVFvRLqIGpAwelHfw2e9ZMc0GynEr34Qezc+I+ycIDiMqnIfQlgsf0R?= =?us-ascii?Q?2+Se2/l4H/Ly8H6DjFpsOiBsKamK/YQfpTVXsy2Y1xQxpcGHAaeeAUmjZnPr?= =?us-ascii?Q?W2Ht3niKoYt/tn00l5OwXE3FhQABWLCCRb/VMXEfirzpMgEOqtwi8YrwthxH?= =?us-ascii?Q?r1UUCCS2P3Ljao2gxEwnxQ4YXssPBa7FFdKP8VPOYQk32ET14f+fciTXYYxn?= =?us-ascii?Q?v+kFStjbTjbatcm2ugUJwai7mhZFjguLxJN5yY65dg0rRg9rzmYvaQYuXEZG?= =?us-ascii?Q?Hr3Fax4JCzUKvw1cBpCoUuppQxkNtps1bdUXNSu9CPugiEz9BpQ6MCd1icNT?= =?us-ascii?Q?6z6N?= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-Network-Message-Id: bcd49a67-3a43-4a55-6a10-08d89744105a X-MS-Exchange-CrossTenant-AuthSource: CH2PR01MB6007.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Dec 2020 04:29:46.3704 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xK9bmMVwr7aYFCTh6X+4hwjGUf/cb03qzCgZFqO7IXT977DNWe6u3/VbYFk4LbMt4wweYtDbE0S15YPYUK2e83gtw5bJKwEPVzq6YZJ8RJH7XRPIzy412vWAEnAhVqqr X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR01MB6040 Content-Type: text/plain Initialization library for PCIe PHY on Ampere Altra. Cc: Leif Lindholm Cc: Ard Biesheuvel Cc: Nate DeSimone Signed-off-by: Vu Nguyen --- Silicon/Ampere/License.txt | 25 +++ .../Ampere/AmpereAltraBinPkg/Ac01BinPkg.dec | 16 ++ .../Library/PciePhyLib/PciePhyLib.inf | 23 +++ .../Include/Library/PciePhyLib.h | 165 ++++++++++++++++++ .../Library/PciePhyLib/PciePhyLib.lib | Bin 0 -> 26026 bytes 5 files changed, 229 insertions(+) create mode 100644 Silicon/Ampere/License.txt create mode 100644 Silicon/Ampere/AmpereAltraBinPkg/Ac01BinPkg.dec create mode 100644 Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.inf create mode 100644 Silicon/Ampere/AmpereAltraBinPkg/Include/Library/PciePhyLib.h create mode 100644 Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.lib diff --git a/Silicon/Ampere/License.txt b/Silicon/Ampere/License.txt new file mode 100644 index 000000000000..2fd43292fa64 --- /dev/null +++ b/Silicon/Ampere/License.txt @@ -0,0 +1,25 @@ +Copyright (c) 2020, Ampere Computing LLC. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. diff --git a/Silicon/Ampere/AmpereAltraBinPkg/Ac01BinPkg.dec b/Silicon/Ampere/AmpereAltraBinPkg/Ac01BinPkg.dec new file mode 100644 index 000000000000..2a8ec5e693ec --- /dev/null +++ b/Silicon/Ampere/AmpereAltraBinPkg/Ac01BinPkg.dec @@ -0,0 +1,16 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x0001001B + PACKAGE_NAME = Ac01BinPkg + PACKAGE_GUID = 04F7CB64-0F97-4D05-86B8-34987F4E1B21 + PACKAGE_VERSION = 0.1 + +[Includes] + Include diff --git a/Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.inf b/Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.inf new file mode 100644 index 000000000000..84b1b58ed58c --- /dev/null +++ b/Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.inf @@ -0,0 +1,23 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = PciePhyLib + FILE_GUID = F2AD0AD0-D4B6-11E3-9C1A-0800200C9A66 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PciePhyLib + +[Binaries.AArch64] + LIB|PciePhyLib.lib|* + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec diff --git a/Silicon/Ampere/AmpereAltraBinPkg/Include/Library/PciePhyLib.h b/Silicon/Ampere/AmpereAltraBinPkg/Include/Library/PciePhyLib.h new file mode 100644 index 000000000000..2f0817ea0da1 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraBinPkg/Include/Library/PciePhyLib.h @@ -0,0 +1,165 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PCIE_PHY_LIB_H_ +#define PCIE_PHY_LIB_H_ + +#define PHY_TX_PARAM_SIZE 2 +#define PHY_RX_PARAM_SIZE 2 + +#define BUG_67112 1 +#define UPDATE_SRAM 0 + +#define MULTWRITE_ENABLE 0 +#define MULTI_WR_EN 0 +#define PHY_N_ADDR_OFFSET 0x40000 +#define SNPS_PHY0_BASE_ADDR 0x100000 +#define SNPS_PHY1_BASE_ADDR (SNPS_PHY0_BASE_ADDR + PHY_N_ADDR_OFFSET) +#define SNPS_PHY2_BASE_ADDR (SNPS_PHY1_BASE_ADDR + PHY_N_ADDR_OFFSET) +#define SNPS_PHY3_BASE_ADDR (SNPS_PHY2_BASE_ADDR + PHY_N_ADDR_OFFSET) + +#define BROADCAST_PMA(Src) ((Src | (0x5 << 12)) * 4) +#define BROADCAST_RAW_PCS(Src) ((Src | (0x6 << 12)) * 4) +#define BROADCAST_RAW_PCS_AON(Src) ((Src | (0x7 << 12)) * 4) + +#define PHY_CALIB_TO_VALUE 1000 +#define SRAM_INIT_TO_VALUE 1000 +#define MRDY_DELAY 10 + +#define SRAM_BYPASS_0 0 +#define SRAM_BYPASS_1 1 +#define SRAM_BYPASS_2 2 +#define SRAM_BYPASS_3 3 + +#define SRAM_BOOTLOAD_BYPASS_0 0x1 +#define SRAM_BOOTLOAD_BYPASS_1 0x2 +#define SRAM_BOOTLOAD_BYPASS_2 0x4 +#define SRAM_BOOTLOAD_BYPASS_3 0x8 + +#define SRIS_MODE_EN 0 +#define CLK_REF_SEL 0 +#define CLK_SSC_SEL 1 + +#define CRP_SEL 1 +#define MAX_PHY 3 + +#define LANE_PER_PHY_NUM_MAX 4 + +#define HOST_SECURE_ACCESS(Addr) (UINT64)(Addr | 0x40000000000000) +#define STARTING_SRAM_ADDRESS 0x130000 + +/* + * PCIe PHY error code + */ +typedef enum { + PHY_SRAM_UPDATE_FAIL = -1, + PHY_INIT_PASS = 0, + PHY_ROM_ECC_FAIL, + PHY_SRAM_ECC_FAIL, + PHY_CALIB_FAIL, + PHY_CALIB_TIMEOUT, + PHY_PLL_FAIL +} PHY_STATUS; + +typedef enum { + PHY_DBG_ERROR = 0x0001, + PHY_DBG_INFO = 0x0002, + PHY_DBG_WARN = 0x0004, + PHY_DBG_VERBOSE = 0x0008, + GEN1 = 0, + GEN2 = 1, + GEN3 = 2, + GEN4 = 3, + CCIX = 4 +} PHY_DBG_FLAGS; + +typedef struct { + UINT8 IsCalBySram; + UINT32 PllSettings; + UINT64 TuneTxParam[PHY_RX_PARAM_SIZE]; + UINT64 TuneRxParam[PHY_TX_PARAM_SIZE]; +} PHY_SETTING; + +/** + * struct serdes_plat_resource - Serdes Platform Operations + * @Puts: Prints string to serial console + * @PutInt: Prints 32-bit unsigned integer to serial console + * @PutHex: Prints 32-bit unsigned hex to serial console + * @PutHex64: Prints 64-bit unsigned hex to serial console + * @DebugPrint: Prints formated string to serial console + * @MmioRd: Reads 32-bit unsigned integer + * @MmioWr: Writes 32-bit unsigned integer + */ +typedef struct { + VOID (*Puts)(CONST CHAR8 *Msg); + VOID (*PutInt)(UINT32 Val); + VOID (*PutHex)(UINT32 Val); + VOID (*PutHex64)(UINT64 Val); + INT32 (*DebugPrint)(CONST CHAR8 *Fmt, ...); + VOID (*MmioRd)(UINT64 Addr, UINT32 *Val); + VOID (*MmioWr)(UINT64 Addr, UINT32 Val); + VOID (*UsDelay)(UINT32 Val); +} PHY_PLAT_RESOURCE; + +typedef struct { + UINT64 SdsAddr; /* PHY base address */ + UINT64 PcieCtrlInfo; /* PCIe controller related information + * BIT0-1: SoC revision + * 0: Ampere Altra, 1: Ampere Altra Max, 2: Siryn + * BIT2 : SocketID (0: Socket0, 1: Socket1) + * BIT3 : Reserved + * BIT4-6: Root Complex context (RCA0/1/2/3 or RCB0/4/5/6) + * BIT7 : Reserved + * BIT8-9: PHY Numbers within RCA/RCB [0 to 3 each controls 4 lane] + * 0: x16, 1: x8 , 2:x4, 3: 0x2 + * BIT10-11 : Gen + * 0: Gen1, 1: Gen2, 2: Gen3, 3: Gen4 + ESM + * BIT13-15 : Setting configuration selection + */ + PHY_SETTING PhySetting; /* PHY input setting */ + PHY_PLAT_RESOURCE *PhyPlatResource; /* Debug & misc function pointers */ + PHY_DBG_FLAGS Debug; +} PHY_CONTEXT; + +/* + * Input: + * Ctx - Serdes context pointer + * + * Return: + * PHY_STATUS - Return status + */ +PHY_STATUS +SerdesSramUpdate ( + PHY_CONTEXT *Ctx + ); + +/* + * Input: + * Ctx - Serdes context pointer + * + * Return: + * PHY_STATUS - Return status + */ +PHY_STATUS +SerdesInitClkrst ( + PHY_CONTEXT *Ctx + ); + +/* + * Input: + * Ctx - Serdes context pointer + * + * Return: + * PHY_STATUS - Return status + */ +PHY_STATUS +SerdesInitCalib ( + PHY_CONTEXT *Ctx + ); + +#endif diff --git a/Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.lib b/Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.lib new file mode 100644 index 000000000000..88aaf2cd4adc Binary files /dev/null and b/Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.lib differ -- 2.17.1