From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f68.google.com (mail-pj1-f68.google.com [209.85.216.68]) by mx.groups.io with SMTP id smtpd.web11.152.1607363683875576735 for ; Mon, 07 Dec 2020 09:54:43 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=K8uFs+Cp; spf=pass (domain: nuviainc.com, ip: 209.85.216.68, mailfrom: rebecca@nuviainc.com) Received: by mail-pj1-f68.google.com with SMTP id p21so280350pjv.0 for ; Mon, 07 Dec 2020 09:54:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z+1qAhfd7Lm05ya/KF25iwh8+L/nIjTka3bYRgymc/U=; b=K8uFs+Cp9I9MsciiEwN86qdjORJAFsWI3Qzrgu2MrSM8oAT5YBdV0tquvF7UAD/6tT qFa7GXQvAReT3kkM8+Byt+K/1AdBhUJGTs68xIAEFN6i/p7aMBegAPbJDvDXf6qXtdTB uv4vfjTzbGPNvJ3z8aYjvxTdxl0u78UTxYJS2pphFAcnHs4khmBeVKqh+DpGUt6RiRvd 86+9D2lTln/WscetOOMx0ZeD1c1wkfjzkdw5jcU2Bqi0IiAOQrZcpBRmEoO89c9xNePq T2G83JEm/RF4ILuUU0/sgX6KDTzh13+KkH22IV4wfwO908zTC24dLeQL2txJWXyQ3C94 0QHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z+1qAhfd7Lm05ya/KF25iwh8+L/nIjTka3bYRgymc/U=; b=kBv+ftfLPu9W/s2/7bn36U5tqvA4LXPV9kgJWE3iYeNkFbOD4VDVQS9XnsVNTMAukm BfJsBVSTbPnGyXx3Wgv2zMrd8LCOJV+La/04eNJe62EPjBLdPTcWlXlionktx/SqMJS4 4JR2/gCKdbd7iQyET/zMxo71hgZoOtzlw08pVXvApGRHiLLKld4NH7YPCYULYAidQUsh zVqhTfGC52LZFU/auosV38hluhNxkfdEq8uZ34/h7AzoxE9UsTku+SgIq1saTSwiL9sF rjKdC4zdvKBaF0374lof7Iqrt+5aWIARdx58PFjZzvpiCkpk+bn9VTD9M28xEzf7VNAa 7mQA== X-Gm-Message-State: AOAM533EWjuY4KhCbvjqW2kK6CWmdepQK5gdCpPQdIvGHzjJTti7e4vw 6TvxGuwvw2w3jWm5iHJUiemC1mBudPnhLOlIM6W5Tr2MIu1mfEYw6m9hbbID7LedqAJzAFH9YHM O7D1wCokv4apawrDVjmmF7hi5JcRSUK8T8nzjp7apYapaYRWdOEe5+xwWHnJ1ocBlKcAOeSXB X-Google-Smtp-Source: ABdhPJz8Cc9quc8a7bv+lfDY9hum4w3LCP6gbGyxbpg4D4iE5ktyrXn2iMobDgq6eN7CXB4Pg8fjMw== X-Received: by 2002:a17:90a:c484:: with SMTP id j4mr17705896pjt.69.1607363682895; Mon, 07 Dec 2020 09:54:42 -0800 (PST) Return-Path: Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id nm6sm2369pjb.25.2020.12.07.09.54.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Dec 2020 09:54:42 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Michael D Kinney , Liming Gao , Zhiguang Liu , Leif Lindholm , Ard Biesheuvel Subject: [PATCH v4 03/10] ArmPkg: Add register encoding definition for MMFR2 Date: Mon, 7 Dec 2020 10:54:20 -0700 Message-Id: <20201207175427.28712-4-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com> References: <20201207175427.28712-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add register encoding definition for Memory Model Feature Register 2. We need to define it here because we build for ARMv8.0, which doesn't have it. Signed-off-by: Rebecca Cran --- ArmPkg/Include/Chipset/AArch64.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h index 0ade5cce91c3..7c2b592f92ee 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -112,6 +112,10 @@ #define ARM_VECTOR_LOW_A32_FIQ 0x700 #define ARM_VECTOR_LOW_A32_SERR 0x780 +// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we +// build for ARMv8.0, we need to define the register here. +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + #define VECTOR_BASE(tbl) \ .section .text.##tbl##,"ax"; \ .align 11; \ -- 2.26.2