From: "Rebecca Cran" <rebecca@nuviainc.com>
To: devel@edk2.groups.io
Cc: Rebecca Cran <rebecca@nuviainc.com>,
Michael D Kinney <michael.d.kinney@intel.com>,
Liming Gao <gaoliming@byosoft.com.cn>,
Zhiguang Liu <zhiguang.liu@intel.com>,
Leif Lindholm <leif@nuviainc.com>,
Ard Biesheuvel <ard.biesheuvel@arm.com>
Subject: [PATCH v4 08/10] ArmPkg: Update ArmLibPrivate.h with cache register definitions
Date: Mon, 7 Dec 2020 10:54:25 -0700 [thread overview]
Message-ID: <20201207175427.28712-9-rebecca@nuviainc.com> (raw)
In-Reply-To: <20201207175427.28712-1-rebecca@nuviainc.com>
Update the cache definitions in ArmLibPrivate.h based on current
ARMv8 documentation.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
---
ArmPkg/Library/ArmLib/ArmLibPrivate.h | 91 ++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
index 5eecbc0e1c43..fb1e2cc6b2ac 100644
--- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h
+++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
@@ -1,5 +1,7 @@
/** @file
+ ArmLibPrivate.h
+ Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -50,6 +52,95 @@
#define CACHE_ARCHITECTURE_UNIFIED (0UL)
#define CACHE_ARCHITECTURE_SEPARATE (1UL)
+
+/// Defines the structure of the CSSELR (Cache Size Selection) register
+typedef union {
+ struct {
+ UINT32 InD :1; ///< Instruction not Data bit
+ UINT32 Level :3; ///< Cache level (zero based)
+ UINT32 TnD :1; ///< Allocation not Data bit
+ UINT32 Reserved :27; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
+} CSSELR_DATA;
+
+/// The cache type values for the InD field of the CSSELR register
+typedef enum
+{
+ /// Select the data or unified cache
+ CsselrCacheTypeDataOrUnified = 0,
+ /// Select the instruction cache
+ CsselrCacheTypeInstruction,
+ CsselrCacheTypeMax
+} CSSELR_CACHE_TYPE;
+
+/// Defines the structure of the CCSIDR (Current Cache Size ID) register
+typedef union {
+ struct {
+ UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity :10; ///< Associativity - 1
+ UINT64 NumSets :15; ///< Number of sets in the cache -1
+ UINT64 Unknown :4; ///< Reserved, UNKNOWN
+ UINT64 Reserved :32; ///< Reserved, RES0
+ } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
+ struct {
+ UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity :21; ///< Associativity - 1
+ UINT64 Reserved1 :8; ///< Reserved, RES0
+ UINT64 NumSets :24; ///< Number of sets in the cache -1
+ UINT64 Reserved2 :8; ///< Reserved, RES0
+ } BitsCcidx; ///< Bitfield definition of the register when FEAT_IDX is supported.
+ UINT64 Data; ///< The entire 64-bit value
+} CCSIDR_DATA;
+
+/// Defines the structure of the AARCH32 CCSIDR2 register.
+typedef union {
+ struct {
+ UINT32 NumSets :24; ///< Number of sets in the cache - 1
+ UINT32 Reserved :8; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
+} CSSIDR2_DATA;
+
+/** Defines the structure of the CLIDR (Cache Level ID) register.
+ *
+ * The lower 32 bits are the same for both AARCH32 and AARCH64
+ * so we can use the same structure for both.
+**/
+typedef union {
+ struct {
+ UINT32 Ctype1 : 3; ///< Level 1 cache type
+ UINT32 Ctype2 : 3; ///< Level 2 cache type
+ UINT32 Ctype3 : 3; ///< Level 3 cache type
+ UINT32 Ctype4 : 3; ///< Level 4 cache type
+ UINT32 Ctype5 : 3; ///< Level 5 cache type
+ UINT32 Ctype6 : 3; ///< Level 6 cache type
+ UINT32 Ctype7 : 3; ///< Level 7 cache type
+ UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
+ UINT32 LoC : 3; ///< Level of Coherency
+ UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
+ UINT32 Icb : 3; ///< Inner Cache Boundary
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
+} CLIDR_DATA;
+
+/// The cache types reported in the CLIDR register.
+typedef enum {
+ /// No cache is present
+ ClidrCacheTypeNone = 0,
+ /// There is only an instruction cache
+ ClidrCacheTypeInstructionOnly,
+ /// There is only a data cache
+ ClidrCacheTypeDataOnly,
+ /// There are separate data and instruction caches
+ ClidrCacheTypeSeparate,
+ /// There is a unified cache
+ ClidrCacheTypeUnified,
+ ClidrCacheTypeMax
+} CLIDR_CACHE_TYPE;
+
+#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * level)) & 0b111)
+
VOID
CPSRMaskInsert (
IN UINT32 Mask,
--
2.26.2
next prev parent reply other threads:[~2020-12-07 17:54 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-07 17:54 [PATCH v4 00/10] ArmPkg,MdePkg: Add Universal/Smbios, and related changes Rebecca Cran
2020-12-07 17:54 ` [PATCH v4 01/10] ArmPkg: Add ARM SMC Architecture functions to ArmStdSmc.h Rebecca Cran
2020-12-15 18:06 ` Leif Lindholm
2020-12-16 11:23 ` [edk2-devel] " Sami Mujawar
2020-12-07 17:54 ` [PATCH v4 02/10] MdePkg: Update IndustryStandard/SmBios.h with processor status data Rebecca Cran
2020-12-08 4:50 ` 回复: " gaoliming
2020-12-07 17:54 ` [PATCH v4 03/10] ArmPkg: Add register encoding definition for MMFR2 Rebecca Cran
2020-12-15 18:42 ` Leif Lindholm
2020-12-16 11:31 ` [edk2-devel] " Sami Mujawar
2020-12-07 17:54 ` [PATCH v4 04/10] ArmPkg: Add helper to read the Memory Model Features Register 2 Rebecca Cran
2020-12-15 19:11 ` Leif Lindholm
2020-12-16 11:06 ` [edk2-devel] " Sami Mujawar
2020-12-17 13:38 ` Laszlo Ersek
2020-12-17 13:47 ` Ard Biesheuvel
2020-12-17 18:04 ` Leif Lindholm
2020-12-17 18:19 ` Rebecca Cran
2020-12-17 17:57 ` Leif Lindholm
2020-12-07 17:54 ` [PATCH v4 05/10] ArmPkg: Add helper function to read the Memory Model Feature Register 4 Rebecca Cran
2020-12-16 11:23 ` [edk2-devel] " Sami Mujawar
2020-12-07 17:54 ` [PATCH v4 06/10] ArmPkg: Add helper to read CCIDX status Rebecca Cran
2020-12-16 11:23 ` [edk2-devel] " Sami Mujawar
2020-12-07 17:54 ` [PATCH v4 07/10] ArmPkg: Fix the return type of the ReadCCSIDR function Rebecca Cran
2020-12-15 19:24 ` Leif Lindholm
2020-12-16 11:31 ` [edk2-devel] " Sami Mujawar
2020-12-07 17:54 ` Rebecca Cran [this message]
2020-12-15 19:27 ` [PATCH v4 08/10] ArmPkg: Update ArmLibPrivate.h with cache register definitions Leif Lindholm
2020-12-07 17:54 ` [PATCH v4 09/10] ArmPkg: Add definition of the maximum cache level in ARMv8-A Rebecca Cran
2020-12-15 19:27 ` Leif Lindholm
2020-12-16 11:31 ` [edk2-devel] " Sami Mujawar
2020-12-07 17:54 ` [PATCH v4 10/10] ArmPkg: Add Universal/Smbios, a generic SMBIOS library for ARM Rebecca Cran
2020-12-15 19:29 ` Leif Lindholm
2020-12-15 21:14 ` Rebecca Cran
2020-12-16 15:13 ` [edk2-devel] " Sami Mujawar
2020-12-16 15:21 ` Rebecca Cran
2020-12-19 3:14 ` Rebecca Cran
[not found] ` <16513B32D4BA613C.12945@groups.io>
2020-12-29 15:10 ` Sami Mujawar
2021-01-03 23:52 ` Rebecca Cran
2021-01-04 10:21 ` Sami Mujawar
2020-12-14 15:45 ` [PATCH v4 00/10] ArmPkg,MdePkg: Add Universal/Smbios, and related changes Rebecca Cran
2020-12-15 18:36 ` Leif Lindholm
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