From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.4174.1607403076586454759 for ; Mon, 07 Dec 2020 20:51:16 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: yun.lou@intel.com) IronPort-SDR: 1bFuVLoPnr0KlNSw+4KiHkJaFf9H+gkuOlh/0DoWgbiDbPib5kmb1O+x2Q3jGJ7pML2/6U3fQL SHLONmWDpnkQ== X-IronPort-AV: E=McAfee;i="6000,8403,9828"; a="235431787" X-IronPort-AV: E=Sophos;i="5.78,401,1599548400"; d="scan'208";a="235431787" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2020 20:51:14 -0800 IronPort-SDR: tFDgbKAH7jNNkh2XVYl46sEDOy32wZGYoUpfcRLntHTh5GdSQMBcAicQUoAVahm5AMkpkTVxz6 Tb4APHRfpsSg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,401,1599548400"; d="scan'208";a="437245125" Received: from shwdeopenlab102.ccr.corp.intel.com ([10.239.183.61]) by fmsmga001.fm.intel.com with ESMTP; 07 Dec 2020 20:51:12 -0800 From: "Jason Lou" To: devel@edk2.groups.io Cc: Jason , Ray Ni , Eric Dong , Laszlo Ersek , Rahul Kumar Subject: [PATCH v2 2/2] UefiCpuPkg/CpuCacheInfoLib: Add new CpuCacheInfoLib. Date: Tue, 8 Dec 2020 12:51:04 +0800 Message-Id: <20201208045104.1234-2-yun.lou@intel.com> X-Mailer: git-send-email 2.28.0.windows.1 In-Reply-To: <20201208045104.1234-1-yun.lou@intel.com> References: <20201208045104.1234-1-yun.lou@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable https://bugzilla.tianocore.org/show_bug.cgi?id=3D3105 This new library uses a platform agnostic algorithm to get CPU cache information. It provides user with an API(GetCpuCacheInfo) to get detailed CPU cache information by each package, each core type included in this package, and each cache level & type. This library can be used by code that produces SMBIOS_TABLE_TYPE7 SMBIOS table. Signed-off-by: Jason Lou Cc: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek Cc: Rahul Kumar --- UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 541 +++++++= +++++++++++++ UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c | 122 +++++ UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c | 121 +++++ UefiCpuPkg/Include/Library/CpuCacheInfoLib.h | 73 +++ UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.uni | 15 + UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf | 43 ++ UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h | 69 +++ UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf | 43 ++ UefiCpuPkg/UefiCpuPkg.dec | 3 + UefiCpuPkg/UefiCpuPkg.dsc | 4 + 10 files changed, 1034 insertions(+) diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c b/UefiCpu= Pkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c new file mode 100644 index 000000000000..b13187f68f24 --- /dev/null +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c @@ -0,0 +1,541 @@ +/** @file=0D + Provides cache info for each package, core type, cache level and cache t= ype.=0D +=0D + Copyright (c) 2020 Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/*=0D + Defines the maximum count of Deterministic Cache Parameters Leaf of all = APs and BSP.=0D + To save boot time, skip starting up all APs to calculate each AP's count= of Deterministic=0D + Cache Parameters Leaf, so use a definition instead.=0D + Anyway, definition value will be checked in CpuCacheInfoCollectCoreAndCa= cheData function.=0D +*/=0D +#define MAX_NUM_OF_CACHE_PARAMS_LEAF 5=0D +=0D +/*=0D + Defines the maximum count of Core Type of all BSP and APs in one package= .=0D + Core Type value comes from CPUID.1Ah.EAX[31:24].=0D +*/=0D +#define MAX_NUM_OF_CORE_TYPE 256=0D +=0D +/*=0D + Defines the maximum count of packages.=0D +*/=0D +#define MAX_NUM_OF_PACKAGE 100=0D +=0D +/**=0D + Get EFI_MP_SERVICES_PROTOCOL pointer.=0D +=0D + @retval Return MP_SERVICES structure.=0D +**/=0D +MP_SERVICES=0D +CpuCacheInfoGetMpServices (=0D + VOID=0D + );=0D +=0D +/**=0D + Activate all of the logical processors.=0D +=0D + @param[in] MpServices MP_SERVICES structure.=0D + @param[in] Procedure A pointer to the function to be run on e= nabled logical processors.=0D + @param[in] ProcedureArgument The parameter passed into Procedure for = all enabled logical processors.=0D +**/=0D +VOID=0D +CpuCacheInfoStartupAllCPUs (=0D + IN MP_SERVICES MpServices,=0D + IN EFI_AP_PROCEDURE Procedure,=0D + IN VOID *ProcedureArgument=0D + );=0D +=0D +/**=0D + Get detailed information of the requested logical processor.=0D +=0D + @param[in] MpServices MP_SERVICES structure.=0D + @param[in] ProcessorNum The requested logical processor number.= =0D +=0D + @retval Return EFI_PROCESSOR_INFORMATION structure of requested logical= processors.=0D +**/=0D +EFI_PROCESSOR_INFORMATION=0D +CpuCacheInfoGetProcessorInfo (=0D + IN MP_SERVICES MpServices,=0D + IN UINTN ProcessorNum=0D + );=0D +=0D +/**=0D + Get the logical processor number.=0D +=0D + @param[in] MpServices MP_SERVICES structure.=0D +=0D + @retval Return the logical processor number.=0D +**/=0D +UINT32=0D +CpuCacheInfoWhoAmI (=0D + IN MP_SERVICES MpServices=0D + );=0D +=0D +/**=0D + Get the total number of logical processors in the platform.=0D +=0D + @param[in] MpServices MP_SERVICES structure.=0D +=0D + @retval Return the total number of logical processors.=0D +**/=0D +UINT32=0D +CpuCacheInfoGetNumberOfProcessors (=0D + IN MP_SERVICES MpServices=0D + );=0D +=0D +/**=0D + Print CpuCacheInfo array.=0D +=0D + @param[in] CpuCacheInfo Pointer to the CpuCacheInfo array.=0D + @param[in] CpuCacheInfoCount The length of CpuCacheInfo array.=0D +=0D +**/=0D +VOID=0D +CpuCacheInfoPrintCpuCacheInfoTable (=0D + IN CPU_CACHE_INFO *CpuCacheInfo,=0D + IN UINTN CpuCacheInfoCount=0D + )=0D +{=0D + UINTN Index;=0D +=0D + DEBUG ((DEBUG_INFO, "+-------+------------------------------------------= -------------------------------------+\n"));=0D + DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType = CacheWays CacheSizeinKB CacheCount |\n"));=0D + DEBUG ((DEBUG_INFO, "+-------+------------------------------------------= -------------------------------------+\n"));=0D +=0D + for (Index =3D 0; Index < CpuCacheInfoCount; Index++) {=0D + DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x = %4x %8x %4x |\n", Index, \=0D + CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCach= eInfo[Index].CacheLevel, \=0D + CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuC= acheInfo[Index].CacheSizeinKB, \=0D + CpuCacheInfo[Index].CacheCount));=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "+-------+------------------------------------------= -------------------------------------+\n"));=0D +}=0D +=0D +/**=0D + Get the total number of package in the platform.=0D +=0D + @param[in] CpuidCacheData Pointer to the CpuidCacheData array.= =0D + @param[in] CpuidCacheDataCount The length of CpuidCacheData array.= =0D + @param[in, out] Package Pointer to the Package array.=0D +=0D + @retval Return the total number of package and package ID in the platfo= rm.=0D +**/=0D +UINT32=0D +CpuCacheInfoGetNumberOfPackage (=0D + IN CPUID_CACHE_DATA *CpuidCacheData,=0D + IN UINTN CpuidCacheDataCount,=0D + IN OUT UINT32 *Package=0D + )=0D +{=0D + UINTN ProcessorNum;=0D + UINT32 PackageIndex;=0D + UINT32 PackageCount;=0D + CPUID_CACHE_DATA *CurrentCpuidCacheData;=0D +=0D + PackageCount =3D 0;=0D +=0D + for (ProcessorNum =3D 0; ProcessorNum * MAX_NUM_OF_CACHE_PARAMS_LEAF < C= puidCacheDataCount; ProcessorNum++) {=0D + CurrentCpuidCacheData =3D &CpuidCacheData[ProcessorNum * MAX_NUM_OF_CA= CHE_PARAMS_LEAF];=0D +=0D + //=0D + // For the package has already existed in Package array, break out the= loop.=0D + //=0D + for (PackageIndex =3D 0; PackageIndex < PackageCount; PackageIndex++) = {=0D + if (CurrentCpuidCacheData->Location.Package =3D=3D Package[PackageIn= dex]) {=0D + break;=0D + }=0D + }=0D +=0D + //=0D + // For the new package, save it in Package array.=0D + //=0D + if (PackageIndex =3D=3D PackageCount) {=0D + ASSERT (PackageCount < MAX_NUM_OF_PACKAGE);=0D + Package[PackageCount++] =3D CurrentCpuidCacheData->Location.Package;= =0D + }=0D + }=0D +=0D + return PackageCount;=0D +}=0D +=0D +/**=0D + Get the number of CoreType of requested package.=0D +=0D + @param[in] CpuidCacheData Pointer to the CpuidCacheData array.=0D + @param[in] CpuidCacheDataCount The length of CpuidCacheData array.=0D + @param[in] Package The requested package number.=0D +=0D + @retval Return the number of CoreType of requested package.=0D +**/=0D +UINT16=0D +CpuCacheInfoGetNumberOfCoreTypePerPackage(=0D + IN CPUID_CACHE_DATA *CpuidCacheData,=0D + IN UINTN CpuidCacheDataCount,=0D + IN UINTN Package=0D + )=0D +{=0D + UINTN ProcessorNum;=0D + UINT16 CoreTypeIndex;=0D + UINT8 CoreType[MAX_NUM_OF_CORE_TYPE];=0D + UINT16 CoreTypeCount;=0D + CPUID_CACHE_DATA *CurrentCpuidCacheData;=0D +=0D + //=0D + // CoreType array is empty.=0D + //=0D + CoreTypeCount =3D 0;=0D + ZeroMem (CoreType, sizeof (CoreType));=0D +=0D + for (ProcessorNum =3D 0; ProcessorNum * MAX_NUM_OF_CACHE_PARAMS_LEAF < C= puidCacheDataCount; ProcessorNum++) {=0D + CurrentCpuidCacheData =3D &CpuidCacheData[ProcessorNum * MAX_NUM_OF_CA= CHE_PARAMS_LEAF];=0D +=0D + if (CurrentCpuidCacheData->Location.Package !=3D Package) {=0D + continue;=0D + }=0D +=0D + //=0D + // For the type has already existed in CoreType array, break out the l= oop.=0D + //=0D + for (CoreTypeIndex =3D 0; CoreTypeIndex < CoreTypeCount; CoreTypeIndex= ++) {=0D + if (CurrentCpuidCacheData->CoreType =3D=3D CoreType[CoreTypeIndex]) = {=0D + break;=0D + }=0D + }=0D +=0D + //=0D + // For the new type, save it in CoreType array.=0D + //=0D + if (CoreTypeIndex =3D=3D CoreTypeCount) {=0D + ASSERT (CoreTypeCount < MAX_NUM_OF_CORE_TYPE);=0D + CoreType[CoreTypeCount++] =3D CurrentCpuidCacheData->CoreType;=0D + }=0D + }=0D +=0D + return CoreTypeCount;=0D +}=0D +=0D +/**=0D + Collect core and cache information of calling processor via CPUID instru= ctions.=0D +=0D + @param[in] Buffer The pointer to private data buffer.=0D +**/=0D +VOID=0D +CpuCacheInfoCollectCoreAndCacheData (=0D + IN OUT VOID *Buffer=0D + )=0D +{=0D + UINTN ProcessorNum;=0D + UINT32 CpuidMaxInput;=0D + UINT8 CoreType;=0D + UINT8 CacheParamLeafNum;=0D + CPUID_CACHE_PARAMS_EAX CacheParamEax;=0D + CPUID_CACHE_PARAMS_EBX CacheParamEbx;=0D + UINT32 CacheParamEcx;=0D + CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX NativeModelIdAndCoreTypeEax;=0D + COLLECT_CPUID_CACHE_DATA_CONTEXT *Context;=0D + CPUID_CACHE_DATA *CpuidCacheData;=0D +=0D + Context =3D (COLLECT_CPUID_CACHE_DATA_CONTEXT *)Buffer;=0D +=0D + ProcessorNum =3D CpuCacheInfoWhoAmI (Context->MpServices);=0D +=0D + CpuidCacheData =3D &Context->CpuidCacheData[MAX_NUM_OF_CACHE_PARAMS_LEAF= * ProcessorNum];=0D +=0D + AsmCpuid (CPUID_SIGNATURE, &CpuidMaxInput, NULL, NULL, NULL);=0D +=0D + //=0D + // get CoreType if CPUID_HYBRID_INFORMATION leaf is supported.=0D + //=0D + CoreType =3D 0;=0D + if (CpuidMaxInput >=3D CPUID_HYBRID_INFORMATION) {=0D + AsmCpuidEx (CPUID_HYBRID_INFORMATION, CPUID_HYBRID_INFORMATION_SUB_LEA= F, &NativeModelIdAndCoreTypeEax.Uint32, NULL, NULL, NULL);=0D + CoreType =3D (UINT8)NativeModelIdAndCoreTypeEax.Bits.CoreType;=0D + }=0D +=0D + //=0D + // cache hierarchy starts with an index value of 0.=0D + //=0D + CacheParamLeafNum =3D 0;=0D +=0D + while (CacheParamLeafNum !=3D MAX_NUM_OF_CACHE_PARAMS_LEAF) {=0D + AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafNum, &CacheParamEax.Uint= 32, &CacheParamEbx.Uint32, &CacheParamEcx, NULL);=0D +=0D + if (CacheParamEax.Bits.CacheType =3D=3D 0) {=0D + break;=0D + }=0D +=0D + CpuidCacheData[CacheParamLeafNum].CoreType =3D CoreType;=0D + CpuidCacheData[CacheParamLeafNum].CacheLevel =3D (UINT8)CacheParamEax.= Bits.CacheLevel;=0D + CpuidCacheData[CacheParamLeafNum].CacheType =3D (UINT8)CacheParamEax.B= its.CacheType;=0D + CpuidCacheData[CacheParamLeafNum].CacheWays =3D (UINT16)CacheParamEbx.= Bits.Ways;=0D + CpuidCacheData[CacheParamLeafNum].CacheShareBits =3D (UINT16)CachePara= mEax.Bits.MaximumAddressableIdsForLogicalProcessors;=0D + CpuidCacheData[CacheParamLeafNum].CacheSizeinKB =3D ((CacheParamEbx.Bi= ts.Ways + 1) * \=0D + (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.Line= Size + 1) * (CacheParamEcx + 1)) / SIZE_1KB;=0D +=0D + ASSERT (CacheParamLeafNum !=3D MAX_NUM_OF_CACHE_PARAMS_LEAF);=0D + CacheParamLeafNum++;=0D + }=0D +}=0D +=0D +/**=0D + Collect processor location information of all logical processors via MpS= ervices.=0D +=0D + @param[in] Context The pointer to COLLECT_CPUID_CACHE_DATA_= CONTEXT structure.=0D + @param[in] NumberOfProcessor The total number of logical processors i= n the platform.=0D +=0D +**/=0D +VOID=0D +CpuCacheInfoCollectProcessorLocationData (=0D + IN COLLECT_CPUID_CACHE_DATA_CONTEXT *Context,=0D + IN UINTN NumberOfProcessor=0D + )=0D +{=0D + UINTN ProcessorNum;=0D + UINTN CacheParamLeafNum;=0D + EFI_PROCESSOR_INFORMATION ProcessorInfo;=0D + IN CPUID_CACHE_DATA *CpuidCacheData;=0D +=0D + for (ProcessorNum =3D 0; ProcessorNum < NumberOfProcessor; ProcessorNum+= +) {=0D + CpuidCacheData =3D &Context->CpuidCacheData[MAX_NUM_OF_CACHE_PARAMS_LE= AF * ProcessorNum];=0D + ProcessorInfo =3D CpuCacheInfoGetProcessorInfo (Context->MpServices, P= rocessorNum);=0D +=0D + for (CacheParamLeafNum =3D 0; CacheParamLeafNum < MAX_NUM_OF_CACHE_PAR= AMS_LEAF; CacheParamLeafNum++) {=0D + CpuidCacheData[CacheParamLeafNum].Location.Package =3D ProcessorInfo= .Location.Package;=0D + CpuidCacheData[CacheParamLeafNum].Location.Core =3D ProcessorInfo.Lo= cation.Core;=0D + CpuidCacheData[CacheParamLeafNum].Location.Thread =3D ProcessorInfo.= Location.Thread;=0D + CpuidCacheData[CacheParamLeafNum].ApicId =3D (UINT32)ProcessorInfo.P= rocessorId;=0D + }=0D + }=0D +}=0D +=0D +/**=0D + Collect CpuCacheInfo data from the CpuidCacheData.=0D +=0D + @param[in] CpuidCacheData Pointer to the CpuidCacheData array.= =0D + @param[in] CpuidCacheDataCount The length of CpuidCacheData array.= =0D + @param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.=0D + @param[in, out] CpuCacheInfoCount As input, point to the length of res= ponse CpuCacheInfo array.=0D + As output, point to the actual lengt= h of response CpuCacheInfo array.=0D +=0D + @retval EFI_SUCCESS Function completed successfully.= =0D + @retval EFI_OUT_OF_RESOURCES Required resources could not be = allocated.=0D + @retval EFI_BUFFER_TOO_SMALL CpuCacheInfoCount is too small t= o hold the response CpuCacheInfo=0D + array. CpuCacheInfoCount has bee= n updated with the length needed=0D + to complete the request.=0D +**/=0D +EFI_STATUS=0D +CpuCacheInfoCollectCpuCacheInfoData (=0D + IN CPUID_CACHE_DATA *CpuidCacheData,=0D + IN UINTN CpuidCacheDataCount,=0D + IN OUT CPU_CACHE_INFO *CpuCacheInfo,=0D + IN OUT UINTN *CpuCacheInfoCount=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT32 NumberOfPackage;=0D + UINTN PackageIndex;=0D + UINT16 NumberOfCoreType;=0D + UINTN TotalNumberOfCoreType;=0D + CPU_CACHE_INFO *TempCpuCacheInfo;=0D + UINTN TempCacheInfoIndex;=0D + UINTN TempCacheInfoCount;=0D + UINTN CurrentCacheDataIndex;=0D + UINTN NextCacheDataIndex;=0D + UINTN CacheInfoIndex;=0D + UINTN ValidCacheInfoCount;=0D + UINT32 Package[MAX_NUM_OF_PACKAGE];=0D +=0D + //=0D + // Get number of Packages and Package ID.=0D + //=0D + ZeroMem (Package, sizeof (Package));=0D + NumberOfPackage =3D CpuCacheInfoGetNumberOfPackage (CpuidCacheData, Cpui= dCacheDataCount, Package);=0D +=0D + //=0D + // Get number of core types for each package and count the total number.= =0D + // E.g. If Packege1 and Package2 both have 2 core types, the total numbe= r is 4.=0D + //=0D + TotalNumberOfCoreType =3D 0;=0D +=0D + for (PackageIndex =3D 0; PackageIndex < NumberOfPackage; PackageIndex++)= {=0D + NumberOfCoreType =3D CpuCacheInfoGetNumberOfCoreTypePerPackage (CpuidC= acheData, CpuidCacheDataCount, Package[PackageIndex]);=0D + TotalNumberOfCoreType +=3D NumberOfCoreType;=0D + }=0D +=0D + TempCacheInfoCount =3D TotalNumberOfCoreType * MAX_NUM_OF_CACHE_PARAMS_L= EAF;=0D + TempCpuCacheInfo =3D AllocatePages (EFI_SIZE_TO_PAGES (TempCacheInfoCoun= t * sizeof (*TempCpuCacheInfo)));=0D + ASSERT (TempCpuCacheInfo !=3D NULL);=0D + if (TempCpuCacheInfo =3D=3D NULL) {=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D +=0D + ZeroMem (TempCpuCacheInfo, TempCacheInfoCount * sizeof (*TempCpuCacheInf= o));=0D +=0D + //=0D + // TempCpuCacheInfo is empty.=0D + //=0D + ValidCacheInfoCount =3D 0;=0D +=0D + for (CurrentCacheDataIndex =3D 0; CurrentCacheDataIndex < CpuidCacheData= Count; CurrentCacheDataIndex++) {=0D + if (CpuidCacheData[CurrentCacheDataIndex].CacheSizeinKB =3D=3D 0)=0D + continue;=0D +=0D + //=0D + // For the sharing caches, clear their CacheSize.=0D + //=0D + for (NextCacheDataIndex =3D CurrentCacheDataIndex + 1; NextCacheDataIn= dex < CpuidCacheDataCount; NextCacheDataIndex++) {=0D + if (CpuidCacheData[NextCacheDataIndex].CacheSizeinKB =3D=3D 0)=0D + continue;=0D +=0D + if (CpuidCacheData[CurrentCacheDataIndex].Location.Package =3D=3D Cp= uidCacheData[NextCacheDataIndex].Location.Package && \=0D + CpuidCacheData[CurrentCacheDataIndex].CoreType =3D=3D CpuidCache= Data[NextCacheDataIndex].CoreType && \=0D + CpuidCacheData[CurrentCacheDataIndex].CacheLevel =3D=3D CpuidCac= heData[NextCacheDataIndex].CacheLevel && \=0D + CpuidCacheData[CurrentCacheDataIndex].CacheType =3D=3D CpuidCach= eData[NextCacheDataIndex].CacheType && \=0D + (CpuidCacheData[CurrentCacheDataIndex].ApicId & ~CpuidCacheData[= CurrentCacheDataIndex].CacheShareBits) =3D=3D \=0D + (CpuidCacheData[NextCacheDataIndex].ApicId & ~CpuidCacheData[Nex= tCacheDataIndex].CacheShareBits)) {=0D + CpuidCacheData[NextCacheDataIndex].CacheSizeinKB =3D 0; // uses th= e sharing cache=0D + }=0D + }=0D +=0D + //=0D + // For the cache has already existed in TempCpuCacheInfo buffer, incre= ase its CacheCount.=0D + //=0D + for (TempCacheInfoIndex =3D 0; TempCacheInfoIndex < ValidCacheInfoCoun= t; TempCacheInfoIndex++) {=0D + if (CpuidCacheData[CurrentCacheDataIndex].Location.Package =3D=3D Te= mpCpuCacheInfo[TempCacheInfoIndex].Package && \=0D + CpuidCacheData[CurrentCacheDataIndex].CoreType =3D=3D TempCpuCac= heInfo[TempCacheInfoIndex].CoreType && \=0D + CpuidCacheData[CurrentCacheDataIndex].CacheLevel =3D=3D TempCpuC= acheInfo[TempCacheInfoIndex].CacheLevel && \=0D + CpuidCacheData[CurrentCacheDataIndex].CacheType =3D=3D TempCpuCa= cheInfo[TempCacheInfoIndex].CacheType) {=0D + TempCpuCacheInfo[TempCacheInfoIndex].CacheCount++;=0D + break;=0D + }=0D + }=0D +=0D + //=0D + // For the new cache with different Package, CoreType, CacheLevel or C= acheType, copy its=0D + // data into TempCpuCacheInfo buffer.=0D + //=0D + if (TempCacheInfoIndex =3D=3D ValidCacheInfoCount) {=0D + ASSERT (ValidCacheInfoCount < TempCacheInfoCount);=0D +=0D + TempCpuCacheInfo[ValidCacheInfoCount].Package =3D CpuidCacheData[Cur= rentCacheDataIndex].Location.Package;=0D + TempCpuCacheInfo[ValidCacheInfoCount].CoreType =3D CpuidCacheData[Cu= rrentCacheDataIndex].CoreType;=0D + TempCpuCacheInfo[ValidCacheInfoCount].CacheLevel =3D CpuidCacheData[= CurrentCacheDataIndex].CacheLevel;=0D + TempCpuCacheInfo[ValidCacheInfoCount].CacheType =3D CpuidCacheData[C= urrentCacheDataIndex].CacheType;=0D + TempCpuCacheInfo[ValidCacheInfoCount].CacheWays =3D CpuidCacheData[C= urrentCacheDataIndex].CacheWays;=0D + TempCpuCacheInfo[ValidCacheInfoCount].CacheSizeinKB =3D CpuidCacheDa= ta[CurrentCacheDataIndex].CacheSizeinKB;=0D + TempCpuCacheInfo[ValidCacheInfoCount].CacheCount =3D 1;=0D +=0D + ValidCacheInfoCount++;=0D + }=0D + }=0D +=0D + if (*CpuCacheInfoCount < ValidCacheInfoCount) {=0D + Status =3D EFI_BUFFER_TOO_SMALL;=0D + } else {=0D + Status =3D EFI_SUCCESS;=0D +=0D + for (CacheInfoIndex =3D 0; CacheInfoIndex < ValidCacheInfoCount; Cache= InfoIndex++) {=0D + CopyMem (&CpuCacheInfo[CacheInfoIndex], &TempCpuCacheInfo[CacheInfoI= ndex], sizeof (*CpuCacheInfo));=0D + }=0D +=0D + DEBUG_CODE (=0D + CpuCacheInfoPrintCpuCacheInfoTable (CpuCacheInfo, ValidCacheInfoCoun= t);=0D + );=0D + }=0D +=0D + *CpuCacheInfoCount =3D ValidCacheInfoCount;=0D +=0D + FreePages (TempCpuCacheInfo, EFI_SIZE_TO_PAGES (TempCacheInfoCount * siz= eof (*TempCpuCacheInfo)));=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Get CpuCacheInfo data array.=0D +=0D + @param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.=0D + @param[in, out] CpuCacheInfoCount As input, point to the length of res= ponse CpuCacheInfo array.=0D + As output, point to the actual lengt= h of response CpuCacheInfo array.=0D +=0D + @retval EFI_SUCCESS Function completed successfully.= =0D + @retval EFI_INVALID_PARAMETER CpuCacheInfoCount is NULL.=0D + @retval EFI_INVALID_PARAMETER CpuCacheInfo is NULL while CpuCa= cheInfoCount contains the value=0D + greater than zero.=0D + @retval EFI_OUT_OF_RESOURCES Required resources could not be = allocated.=0D + @retval EFI_BUFFER_TOO_SMALL CpuCacheInfoCount is too small t= o hold the response CpuCacheInfo=0D + array. CpuCacheInfoCount has bee= n updated with the length needed=0D + to complete the request.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetCpuCacheInfo (=0D + IN OUT CPU_CACHE_INFO *CpuCacheInfo,=0D + IN OUT UINTN *CpuCacheInfoCount=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT32 NumberOfProcessor;=0D + UINTN CpuidCacheDataCount;=0D + COLLECT_CPUID_CACHE_DATA_CONTEXT Context;=0D +=0D + if (CpuCacheInfoCount =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D +=0D + } else if (*CpuCacheInfoCount !=3D 0 && CpuCacheInfo =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + //=0D + // Initialize COLLECT_CPUID_CACHE_DATA_CONTEXT.MpServices.=0D + //=0D + Context.MpServices =3D CpuCacheInfoGetMpServices ();=0D +=0D + NumberOfProcessor =3D CpuCacheInfoGetNumberOfProcessors (Context.MpServi= ces);=0D +=0D + //=0D + // Initialize COLLECT_CPUID_CACHE_DATA_CONTEXT.CpuidCacheData.=0D + // CpuidCacheData array consists of CPUID_CACHE_DATA data structure for = each Cpuid Cache Parameter Leaf=0D + // per logical processor. The array begin with data of each Cache Parame= ter Leaf of processor 0, followed=0D + // by data of each Cache Parameter Leaf of processor 1 ...=0D + //=0D + CpuidCacheDataCount =3D NumberOfProcessor * MAX_NUM_OF_CACHE_PARAMS_LEAF= ;=0D + Context.CpuidCacheData =3D AllocatePages (EFI_SIZE_TO_PAGES (CpuidCacheD= ataCount * sizeof (*Context.CpuidCacheData)));=0D + ASSERT (Context.CpuidCacheData !=3D NULL);=0D + if (Context.CpuidCacheData =3D=3D NULL) {=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D +=0D + ZeroMem (Context.CpuidCacheData, CpuidCacheDataCount * sizeof (*Context.= CpuidCacheData));=0D +=0D + //=0D + // Wakeup all processors for CpuidCacheData(core and cache data) collect= ion.=0D + //=0D + CpuCacheInfoStartupAllCPUs (Context.MpServices, CpuCacheInfoCollectCoreA= ndCacheData, &Context);=0D +=0D + //=0D + // Collect CpuidCacheData(ProcessorLocation data) of all processors.=0D + //=0D + CpuCacheInfoCollectProcessorLocationData (&Context, NumberOfProcessor);= =0D +=0D + //=0D + // Collect CpuCacheInfo data from CpuidCacheData.=0D + //=0D + Status =3D CpuCacheInfoCollectCpuCacheInfoData (Context.CpuidCacheData, = CpuidCacheDataCount, CpuCacheInfo, CpuCacheInfoCount);=0D +=0D + FreePages (Context.CpuidCacheData, EFI_SIZE_TO_PAGES (CpuidCacheDataCoun= t * sizeof (*Context.CpuidCacheData)));=0D +=0D + return Status;=0D +}=0D diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c b/Uefi= CpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c new file mode 100644 index 000000000000..8d2e75614588 --- /dev/null +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c @@ -0,0 +1,122 @@ +/** @file=0D + Provides cache info for each package, core type, cache level and cache t= ype.=0D +=0D + Copyright (c) 2020 Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Get EFI_MP_SERVICES_PROTOCOL pointer.=0D +=0D + @retval Return MP_SERVICES structure.=0D +**/=0D +MP_SERVICES=0D +CpuCacheInfoGetMpServices (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + MP_SERVICES MpServices;=0D +=0D + Status =3D gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID = **)&MpServices.Protocol);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return MpServices;=0D +}=0D +=0D +/**=0D + Activate all of the logical processors.=0D +=0D + @param[in] MpServices MP_SERVICES structure.=0D + @param[in] Procedure A pointer to the function to be run on e= nabled logical processors.=0D + @param[in] ProcedureArgument The parameter passed into Procedure for = all enabled logical processors.=0D +**/=0D +VOID=0D +CpuCacheInfoStartupAllCPUs (=0D + IN MP_SERVICES MpServices,=0D + IN EFI_AP_PROCEDURE Procedure,=0D + IN VOID *ProcedureArgument=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D MpServices.Protocol->StartupAllAPs (MpServices.Protocol, Proc= edure, TRUE, NULL, 0, ProcedureArgument, NULL);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Procedure (ProcedureArgument);=0D +}=0D +=0D +/**=0D + Get detailed information of the requested logical processor.=0D +=0D + @param[in] MpServices MP_SERVICES structure.=0D + @param[in] ProcessorNum The requested logical processor number.= =0D +=0D + @retval Return EFI_PROCESSOR_INFORMATION structure of requested logical= processors.=0D +**/=0D +EFI_PROCESSOR_INFORMATION=0D +CpuCacheInfoGetProcessorInfo (=0D + IN MP_SERVICES MpServices,=0D + IN UINTN ProcessorNum=0D +=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_PROCESSOR_INFORMATION ProcessorInfo;=0D +=0D + Status =3D MpServices.Protocol->GetProcessorInfo (MpServices.Protocol, P= rocessorNum, &ProcessorInfo);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return ProcessorInfo;=0D +}=0D +=0D +/**=0D + Get the logical processor number.=0D +=0D + @param[in] MpServices MP_SERVICES structure.=0D +=0D + @retval Return the logical processor number.=0D +**/=0D +UINT32=0D +CpuCacheInfoWhoAmI (=0D + IN MP_SERVICES MpServices=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINTN ProcessorNum;=0D +=0D + Status =3D MpServices.Protocol->WhoAmI (MpServices.Protocol, &ProcessorN= um);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return (UINT32)ProcessorNum;=0D +}=0D +=0D +/**=0D + Get the total number of logical processors in the platform.=0D +=0D + @param[in] MpServices MP_SERVICES structure.=0D +=0D + @retval Return the total number of logical processors.=0D +**/=0D +UINT32=0D +CpuCacheInfoGetNumberOfProcessors (=0D + IN MP_SERVICES MpServices=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINTN NumberOfProcessor;=0D + UINTN NumberOfEnabledProcessor;=0D +=0D + Status =3D MpServices.Protocol->GetNumberOfProcessors (MpServices.Protoc= ol, &NumberOfProcessor, &NumberOfEnabledProcessor);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return (UINT32)NumberOfProcessor;=0D +}=0D diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c b/Uefi= CpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c new file mode 100644 index 000000000000..9d793a840686 --- /dev/null +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c @@ -0,0 +1,121 @@ +/** @file=0D + Provides cache info for each package, core type, cache level and cache t= ype.=0D +=0D + Copyright (c) 2020 Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Get EDKII_PEI_MP_SERVICES2_PPI pointer.=0D +=0D + @retval Return MP_SERVICES structure.=0D +**/=0D +MP_SERVICES=0D +CpuCacheInfoGetMpServices (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + MP_SERVICES MpServices;=0D +=0D + Status =3D PeiServicesLocatePpi (&gEdkiiPeiMpServices2PpiGuid, 0, NULL, = (VOID **)&MpServices.Ppi);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return MpServices;=0D +}=0D +=0D +/**=0D + Activate all of the logical processors.=0D +=0D + @param[in] MpServices MP_SERVICES structure.=0D + @param[in] Procedure A pointer to the function to be run on e= nabled logical processors.=0D + @param[in] ProcedureArgument The parameter passed into Procedure for = all enabled logical processors.=0D +**/=0D +VOID=0D +CpuCacheInfoStartupAllCPUs (=0D + IN MP_SERVICES MpServices,=0D + IN EFI_AP_PROCEDURE Procedure,=0D + IN VOID *ProcedureArgument=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D MpServices.Ppi->StartupAllCPUs (MpServices.Ppi, Procedure, 0,= ProcedureArgument);=0D + ASSERT_EFI_ERROR (Status);=0D +}=0D +=0D +/**=0D + Get detailed information of the requested logical processor.=0D +=0D + @param[in] MpServices MP_SERVICES structure.=0D + @param[in] ProcessorNum The requested logical processor number.= =0D +=0D + @retval Return EFI_PROCESSOR_INFORMATION structure of requested logical= processors.=0D +**/=0D +EFI_PROCESSOR_INFORMATION=0D +CpuCacheInfoGetProcessorInfo (=0D + IN MP_SERVICES MpServices,=0D + IN UINTN ProcessorNum=0D +=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_PROCESSOR_INFORMATION ProcessorInfo;=0D +=0D + Status =3D MpServices.Ppi->GetProcessorInfo (MpServices.Ppi, ProcessorNu= m, &ProcessorInfo);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return ProcessorInfo;=0D +}=0D +=0D +/**=0D + Get the logical processor number.=0D +=0D + @param[in] MpServices MP_SERVICES structure.=0D +=0D + @retval Return the logical processor number.=0D +**/=0D +UINT32=0D +CpuCacheInfoWhoAmI (=0D + IN MP_SERVICES MpServices=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINTN ProcessorNum;=0D +=0D + Status =3D MpServices.Ppi->WhoAmI (MpServices.Ppi, &ProcessorNum);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return (UINT32)ProcessorNum;=0D +}=0D +=0D +/**=0D + Get the total number of logical processors in the platform.=0D +=0D + @param[in] MpServices MP_SERVICES structure.=0D +=0D + @retval Return the total number of logical processors.=0D +**/=0D +UINT32=0D +CpuCacheInfoGetNumberOfProcessors (=0D + IN MP_SERVICES MpServices=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINTN NumberOfProcessor;=0D + UINTN NumberOfEnabledProcessor;=0D +=0D + Status =3D MpServices.Ppi->GetNumberOfProcessors (MpServices.Ppi, &Numbe= rOfProcessor, &NumberOfEnabledProcessor);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return (UINT32)NumberOfProcessor;=0D +}=0D diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h b/UefiCpuPkg/Incl= ude/Library/CpuCacheInfoLib.h new file mode 100644 index 000000000000..d478211da609 --- /dev/null +++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h @@ -0,0 +1,73 @@ +/** @file=0D + Header file for CPU Cache info Library.=0D +=0D + Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _CPU_CACHE_INFO_LIB_H_=0D +#define _CPU_CACHE_INFO_LIB_H_=0D +=0D +typedef struct {=0D + //=0D + // Package number.=0D + //=0D + UINT32 Package;=0D + //=0D + // Core type of logical processor.=0D + // Value =3D CPUID.1Ah:EAX[31:24]=0D + //=0D + UINT8 CoreType;=0D + //=0D + // Level of the cache that this package's this type of logical processor= corresponds to.=0D + // Value =3D CPUID.04h:EAX[07:05]=0D + //=0D + UINT8 CacheLevel : 3;=0D + //=0D + // Type of the cache that this package's this type of logical processor = corresponds to.=0D + // Value =3D CPUID.04h:EAX[04:00]=0D + //=0D + UINT8 CacheType : 5;=0D + //=0D + // Ways of associativity.=0D + // Value =3D CPUID.04h:EBX[31:22]=0D + //=0D + UINT16 CacheWays;=0D + //=0D + // Size of single cache that this package's this type of logical process= or corresponds to.=0D + // Value =3D (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) * /= =0D + // (CPUID.04h:EBX[11:00] + 1) * (CPUID.04h:ECX[31:00] + 1)=0D + //=0D + UINT32 CacheSizeinKB;=0D + //=0D + // Number of the cache that this package's this type of logical processo= r corresponds to.=0D + // Have subtracted the number of caches that are shared.=0D + //=0D + UINT16 CacheCount;=0D +} CPU_CACHE_INFO;=0D +=0D +/**=0D + Get CpuCacheInfo data array.=0D +=0D + @param[in, out] CpuCacheInfo Pointer to the CpuCacheInfo array.=0D + @param[in, out] CpuCacheInfoCount As input, point to the length of res= ponse CpuCacheInfo array.=0D + As output, point to the actual lengt= h of response CpuCacheInfo array.=0D +=0D + @retval EFI_SUCCESS Function completed successfully.= =0D + @retval EFI_INVALID_PARAMETER CpuCacheInfoCount is NULL.=0D + @retval EFI_INVALID_PARAMETER CpuCacheInfo is NULL while CpuCa= cheInfoCount contains the value=0D + greater than zero.=0D + @retval EFI_OUT_OF_RESOURCES Required resources could not be = allocated.=0D + @retval EFI_BUFFER_TOO_SMALL CpuCacheInfoCount is too small t= o hold the response CpuCacheInfo=0D + array. CpuCacheInfoCount has bee= n updated with the length needed=0D + to complete the request.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetCpuCacheInfo (=0D + IN OUT CPU_CACHE_INFO *CpuCacheInfo,=0D + IN OUT UINTN *CpuCacheInfoCount=0D + );=0D +=0D +#endif=0D diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.uni b/UefiC= puPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.uni new file mode 100644 index 000000000000..1bc801f15f84 --- /dev/null +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.uni @@ -0,0 +1,15 @@ +// /** @file=0D +// CPU Cache Info Library=0D +//=0D +// Provides cache info for each package, core type, cache level and cache = type.=0D +//=0D +// Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +// **/=0D +=0D +=0D +#string STR_MODULE_ABSTRACT #language en-US "CPU Cache Info Li= brary"=0D +=0D +#string STR_MODULE_DESCRIPTION #language en-US "Provides cache in= fo for each package, core type, cache level and cache type."=0D diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf b/Ue= fiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf new file mode 100644 index 000000000000..c481080e49d8 --- /dev/null +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf @@ -0,0 +1,43 @@ +## @file=0D +# CPU Cache Info Library instance for DXE driver.=0D +#=0D +# Provides cache info for each package, core type, cache level and cache = type.=0D +#=0D +# Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D DxeCpuCacheInfoLib=0D + FILE_GUID =3D B25C288F-C309-41F1-8325-37E64DC5EA3D= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D CpuCacheInfoLib|DXE_DRIVER UEFI_APPLI= CATION=0D + MODULE_UNI_FILE =3D CpuCacheInfoLib.uni=0D +=0D +[Sources]=0D + InternalCpuCacheInfoLib.h=0D + CpuCacheInfoLib.c=0D + DxeCpuCacheInfoLib.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + BaseMemoryLib=0D + MemoryAllocationLib=0D + UefiBootServicesTableLib=0D +=0D +[Protocols]=0D + gEfiMpServiceProtocolGuid=0D +=0D +[Pcd]=0D +=0D +[Depex]=0D + gEfiMpServiceProtocolGuid=0D diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h b= /UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h new file mode 100644 index 000000000000..2136ce1ccef7 --- /dev/null +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h @@ -0,0 +1,69 @@ +/** @file=0D + Internal header file for CPU Cache info Library.=0D +=0D + Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _INTERNAL_CPU_CACHE_INFO_LIB_H_=0D +#define _INTERNAL_CPU_CACHE_INFO_LIB_H_=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +typedef struct {=0D + //=0D + // APIC ID.=0D + //=0D + UINT32 ApicId;=0D + //=0D + // Processor location information.=0D + // The information comes from MP Services.=0D + //=0D + EFI_CPU_PHYSICAL_LOCATION Location;=0D + //=0D + // Core type of logical processor.=0D + // Value =3D CPUID.1Ah:EAX[31:24]=0D + //=0D + UINT8 CoreType;=0D + //=0D + // Level of the cache.=0D + // Value =3D CPUID.04h:EAX[07:05]=0D + //=0D + UINT8 CacheLevel : 3;=0D + //=0D + // Type of the cache.=0D + // Value =3D CPUID.04h:EAX[04:00]=0D + //=0D + UINT8 CacheType : 5;=0D + //=0D + // Ways of associativity.=0D + // Value =3D CPUID.04h:EBX[31:22]=0D + //=0D + UINT16 CacheWays;=0D + //=0D + // Cache share bits.=0D + // Value =3D CPUID.04h:EAX[25:14]=0D + //=0D + UINT16 CacheShareBits;=0D + //=0D + // Size of single cache.=0D + // Value =3D (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) * /= =0D + // (CPUID.04h:EBX[11:00] + 1) * (CPUID.04h:ECX[31:00] + 1)=0D + //=0D + UINT32 CacheSizeinKB;=0D +} CPUID_CACHE_DATA;=0D +=0D +typedef union {=0D + EDKII_PEI_MP_SERVICES2_PPI *Ppi;=0D + EFI_MP_SERVICES_PROTOCOL *Protocol;=0D +} MP_SERVICES;=0D +=0D +typedef struct {=0D + MP_SERVICES MpServices;=0D + CPUID_CACHE_DATA *CpuidCacheData;=0D +} COLLECT_CPUID_CACHE_DATA_CONTEXT;=0D +=0D +#endif=0D diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf b/Ue= fiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf new file mode 100644 index 000000000000..0c73015cac8b --- /dev/null +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf @@ -0,0 +1,43 @@ +## @file=0D +# CPU Cache Info Library instance for PEI module.=0D +#=0D +# Provides cache info for each package, core type, cache level and cache = type.=0D +#=0D +# Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PeiCpuCacheInfoLib=0D + FILE_GUID =3D CFEE2DBE-53B2-4916-84CA-0BA83C3DDA6E= =0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D CpuCacheInfoLib|PEIM=0D + MODULE_UNI_FILE =3D CpuCacheInfoLib.uni=0D +=0D +[Sources]=0D + InternalCpuCacheInfoLib.h=0D + CpuCacheInfoLib.c=0D + PeiCpuCacheInfoLib.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + BaseMemoryLib=0D + MemoryAllocationLib=0D + PeiServicesTablePointerLib=0D +=0D +[Ppis]=0D + gEdkiiPeiMpServices2PpiGuid=0D +=0D +[Pcd]=0D +=0D +[Depex]=0D + gEdkiiPeiMpServices2PpiGuid=0D diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index d83c084467b3..a639ce5412e4 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -56,6 +56,9 @@ [LibraryClasses.IA32, LibraryClasses.X64] ## @libraryclass Provides function to support VMGEXIT processing.=0D VmgExitLib|Include/Library/VmgExitLib.h=0D =0D + ## @libraryclass Provides function to get CPU cache information.=0D + CpuCacheInfoLib|Include/Library/CpuCacheInfoLib.h=0D +=0D [Guids]=0D gUefiCpuPkgTokenSpaceGuid =3D { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa,= 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}=0D gMsegSmramGuid =3D { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1,= 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}=0D diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index b2b6d78a71b0..5834eafaa200 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -75,6 +75,7 @@ [LibraryClasses.common.PEIM] LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf=0D MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf=0D RegisterCpuFeaturesLib|UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegi= sterCpuFeaturesLib.inf=0D + CpuCacheInfoLib|UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.in= f=0D =0D [LibraryClasses.IA32.PEIM, LibraryClasses.X64.PEIM]=0D PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/= PeiServicesTablePointerLibIdt.inf=0D @@ -86,6 +87,7 @@ [LibraryClasses.common.DXE_DRIVER] CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf=0D MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf=0D RegisterCpuFeaturesLib|UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegi= sterCpuFeaturesLib.inf=0D + CpuCacheInfoLib|UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.in= f=0D =0D [LibraryClasses.common.DXE_SMM_DRIVER]=0D SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableL= ib.inf=0D @@ -109,6 +111,8 @@ [Components] UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf=0D UefiCpuPkg/Library/CpuTimerLib/DxeCpuTimerLib.inf=0D UefiCpuPkg/Library/CpuTimerLib/PeiCpuTimerLib.inf=0D + UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf=0D + UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf=0D =0D [Components.IA32, Components.X64]=0D UefiCpuPkg/CpuDxe/CpuDxe.inf=0D --=20 2.28.0.windows.1