From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by mx.groups.io with SMTP id smtpd.web12.8940.1607436686204362297 for ; Tue, 08 Dec 2020 06:11:26 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=F9qwyKK4; spf=pass (domain: nuviainc.com, ip: 209.85.128.67, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f67.google.com with SMTP id e25so2499685wme.0 for ; Tue, 08 Dec 2020 06:11:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=VjyL8oex1ZI70oE0AKmKTs9IOMps98k0gznAXmO2fyI=; b=F9qwyKK4fxrnLDWG4HEXQMmKSprImnp5iXcRW5rfLK/74+pi3HgplRyRfB//GYxrYz eQDLtKZiaGwfUQo3yiXrxnoWZI72RgGdSflOj0gAXoYtMmF+OTYyd3+IuJSvD0eeERVj xBrrFx+ZPIKKSajcIDbLRx9uOlmS+KVuojWk3CLLNYE+RoOKAFpdzDJi400urTpIAiAo VzBbN7GBHluZYDKFit3w1Mwf3s/j5PJg5K8tzKEU/4jnCWmZAiyCBHNZBHNgnCr2X8CY RjEZVJXdn2gPVNKMrS0rgvy1jInUhLm/dU5W375JfbfB5FnQOoKgIfIbsKA68HVy4v5V /5BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=VjyL8oex1ZI70oE0AKmKTs9IOMps98k0gznAXmO2fyI=; b=JuGQxLT8ecBbZ7tE/w6REXjxDOLka1hZYX4r8ib3a9bEX/xv6Cys4vBRTfA0roURpo EM80unSg9GeJzVEqtr9wKaehpkyuBHijawyuaPfCwUXdUa7JAkhJBTc+9itPjALAJQv3 s4nE5OCgHyFbHupp1nDqwhIMQYI3E63fo1M4TCdjlITWy0YXobVg0LSz41BXzXaI5AJd kAbYIS22Cmwr0Oh7bTPDkzvNH8EwYJWIw5T/vVw1vKw+r1xZZnW95ftdtz7GRfqXnFAC nlVUsmwHLEYmKhySE08JLjwSBe6QfK3Hul41r9vxMUkJ8OlSylV+BfAo0BDdDmJVFOXD Lugg== X-Gm-Message-State: AOAM532u960SUlhfFrOzXvnbR+rOxEql3mRjwEC3t6NOk2i0Xe74ZrWw dAjQdQxCfb4mjYJ3Ak9RK9rJvg== X-Google-Smtp-Source: ABdhPJxtXW0WNDxdDpPePkfhD7bh2YWKsgFHXNZk8cTgdJjL3gJcj799uti86JNIytKRfC4L6Vcg7w== X-Received: by 2002:a1c:f715:: with SMTP id v21mr4152998wmh.2.1607436684756; Tue, 08 Dec 2020 06:11:24 -0800 (PST) Return-Path: Received: from vanye (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id y7sm19803498wrp.3.2020.12.08.06.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Dec 2020 06:11:24 -0800 (PST) Date: Tue, 8 Dec 2020 14:11:22 +0000 From: "Leif Lindholm" To: Vu Nguyen Cc: devel@edk2.groups.io, patches@amperecomputing.com, Ard Biesheuvel , Nate DeSimone Subject: Re: [edk2-non-osi][PATCH v2 0/2] Introduce Silicon/Ampere and AmpereAltraBinPkg package Message-ID: <20201208141122.GM1664@vanye> References: <20201203042924.28557-1-vunguyen@os.amperecomputing.com> MIME-Version: 1.0 In-Reply-To: <20201203042924.28557-1-vunguyen@os.amperecomputing.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Vu, For the series: Reviewed-by: Leif Lindholm However, I'm not sure it makes sense to push this until there is some platform in edk2-platforms that makes use of it. So I'm holding off on that for now. Best Regards, Leif On Thu, Dec 03, 2020 at 11:29:22 +0700, Vu Nguyen wrote: > This patchset creates edk2-non-osi component holder for Ampere Silicon. > Included is PciePhyLib library that provides necessary functions to > initialize PCIe PHY on ARM64-based Ampere Altra processor. This library > will be used by all Ampere Altra platforms later. > > The changes for this patchset can be found at: > https://github.com/AmpereComputing/edk2-non-osi/tree/add-PciePhyLib-v2 > > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Cc: Nate DeSimone > Signed-off-by: Vu Nguyen > > Version History: > V2: > Remove PciePhyLib.lib binary from the commit > Update header guard to align with coding standard > > Vu Nguyen (2): > AmpereAltraBinPkg: Add PciePhyLib library and header > edk2-non-osi: Add AmpereAltraBinPkg maintainers > > Maintainers.txt | 4 + > Silicon/Ampere/License.txt | 25 +++ > .../Ampere/AmpereAltraBinPkg/Ac01BinPkg.dec | 16 ++ > .../Library/PciePhyLib/PciePhyLib.inf | 23 +++ > .../Include/Library/PciePhyLib.h | 165 ++++++++++++++++++ > .../Library/PciePhyLib/PciePhyLib.lib | Bin 0 -> 26026 bytes > 6 files changed, 233 insertions(+) > create mode 100644 Silicon/Ampere/License.txt > create mode 100644 Silicon/Ampere/AmpereAltraBinPkg/Ac01BinPkg.dec > create mode 100644 Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.inf > create mode 100644 Silicon/Ampere/AmpereAltraBinPkg/Include/Library/PciePhyLib.h > create mode 100644 Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.lib > > -- > 2.17.1 >