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dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=none action=none header.from=os.amperecomputing.com; Received: from DM6PR01MB5849.prod.exchangelabs.com (2603:10b6:5:205::20) by DM6PR01MB5609.prod.exchangelabs.com (2603:10b6:5:157::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.21; Wed, 9 Dec 2020 09:24:33 +0000 Received: from DM6PR01MB5849.prod.exchangelabs.com ([fe80::c814:9a08:5c2e:4076]) by DM6PR01MB5849.prod.exchangelabs.com ([fe80::c814:9a08:5c2e:4076%5]) with mapi id 15.20.3632.023; Wed, 9 Dec 2020 09:24:33 +0000 From: "Nhi Pham" To: devel@edk2.groups.io Cc: Vu Nguyen Subject: [edk2-platforms][PATCH 15/34] JadePkg: Enable PCIe support Date: Wed, 9 Dec 2020 16:25:12 +0700 Message-Id: <20201209092531.30867-16-nhi@os.amperecomputing.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201209092531.30867-1-nhi@os.amperecomputing.com> References: <20201209092531.30867-1-nhi@os.amperecomputing.com> X-Originating-IP: [118.69.219.201] X-ClientProxiedBy: HK0PR01CA0054.apcprd01.prod.exchangelabs.com (2603:1096:203:a6::18) To DM6PR01MB5849.prod.exchangelabs.com (2603:10b6:5:205::20) Return-Path: nhi@os.amperecomputing.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sw004.amperecomputing.com (118.69.219.201) by HK0PR01CA0054.apcprd01.prod.exchangelabs.com (2603:1096:203:a6::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3654.12 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: =?us-ascii?Q?+TCtgbQEyV43QiFyTki6D1yq0zkCt4ShylXjDMM4ICrQUgFzR6vBD0RyGdEp?= =?us-ascii?Q?KuCMWMvpuZPL1XlctSheXUdyPeEpG54wDc/LgDDcXBc1iPb56DPyuxTVEkOt?= =?us-ascii?Q?xGTxNVjz00m6mEYLPIaL5fBJcrwK0UuU80ksny9jo28Kwsm9Zay3G3gld/ky?= =?us-ascii?Q?jklabi7VpZvlVpbhZuc1x7TTvZ2Z01hxjclv5+xZIKoP4TIIh0SO8HVjU/PR?= =?us-ascii?Q?WcDbuvWbMaBBR8RASYqRM7Y1QSiUmyvKpy7i1yQ4iGvWVUIDBZmDOg+T0N5F?= =?us-ascii?Q?toPw9ANQmERdZlAbC9+i2RpOogQ4mu1NLk6087y+X+CmohoPGSCTz113IFnE?= =?us-ascii?Q?LJxzVU2Pw+v+nN6TaqqrG+BOZEsRfo4IaeLBSV9z1PPDohMKSCyX/XvzONDc?= =?us-ascii?Q?WIBLhJA9rZviUeBRjMo7Imr9VcQPpUHxwFZxgsWc6Ab7oFdFKdzF7pYwyw5L?= =?us-ascii?Q?3mFzSCXfwJwN2VwhS9wir4gtHQUH7YRxdc8U+c6O26J4I33Piup+rWTIL25S?= =?us-ascii?Q?E02vqaEzegSNRN8Kw1EiX5fjZnMaZTG0ksyXdVhElk4MGvkMqsYxvgtE0+Zs?= =?us-ascii?Q?HXSkm6A6Z/uBU1Az7Q/SxqBFmK3lMACvaPE3S+aOwWulW6dvaB/IY/YBA0kk?= =?us-ascii?Q?eziKcuYtTpFIySPEXKjeBuq4bFLy617bUM/EKTgMI0HHgAusIoVO3gXUqbj/?= =?us-ascii?Q?Q2fYDL1LwYRi0yYqEx4/pDj+WGlxcXwfpxO2AOb6ZeT4iGY7HX+BEGWWbEFw?= =?us-ascii?Q?QGzyhP+Bus76WZfHck/E+7DlrneF0AyriEJAMW38/iGqbk9sVoMCmgpMNLmK?= =?us-ascii?Q?T/ydpETohW8rIELhJLoHOrpBMcUcX8bYKqlN3OV0BosgLOBqCl9vVGC7cKAG?= =?us-ascii?Q?GjucqCTk/iCgfdjS5+/00K3aPZ8izUaTdpg5iP60ADw71ueLTHetPxSuMfqn?= =?us-ascii?Q?Q36Lly8/FLGDAMh9Pyb6zInaL2wIhk3clwQslRnB6smGHJEv3aAhel7Tl7SB?= =?us-ascii?Q?XpcM?= X-OriginatorOrg: os.amperecomputing.com X-MS-Exchange-CrossTenant-AuthSource: DM6PR01MB5849.prod.exchangelabs.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2020 09:24:33.6479 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-Network-Message-Id: 1c9384c0-c3f9-4c27-013e-08d89c243d7e X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 1farZecvsUAlobfoTK8gz10NBCh/Xk4UY+1RNCz0aIDSs2VJna5ra3ftbp5SRYX9/4OHpKZWPMfDWTINRZejfvzfDz7iNokIiOQTbRSNwPA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB5609 Content-Type: text/plain From: Vu Nguyen Bringup function for all PCIe Root Complex on Ampere Altra SoC. Upto 16 RCs on 2P system and 8 RCs on 1P system. Each PCIe RC bifurcation setting can be done vi PCIe setup screen. The setting can also be hardcoded in BoardSetting due to platform specific. Signed-off-by: Vu Nguyen --- Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dsc.inc | 2 ++ Platform/Ampere/JadePkg/Jade.dsc | 5 +++++ Platform/Ampere/JadePkg/Jade.fdf | 1 + 3 files changed, 8 insertions(+) diff --git a/Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dsc.inc index bb0e5edc3dd7..fab2d3fa800f 100755 --- a/Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dsc.inc +++ b/Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dsc.inc @@ -88,6 +88,7 @@ [LibraryClasses.common] SMProLib|Silicon/Ampere/AmpereAltraPkg/Library/SMProLib/SMProLib.inf PMProLib|Silicon/Ampere/AmpereAltraPkg/Library/PMProLib/PMProLib.inf PciePhyLib|Silicon/Ampere/AmpereAltraBinPkg/Library/PciePhyLib/PciePhyLib.inf + PcieCoreLib|Silicon/Ampere/AmpereAltraPkg/Library/PcieCore/PcieCoreLib.inf AmpereCpuLib|Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.inf TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf I2CLib|Silicon/Ampere/AmpereAltraPkg/Library/DWI2CLib/I2CLib.inf @@ -662,6 +663,7 @@ [Components.common] # PCIe Support # MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + Silicon/Ampere/AmpereAltraPkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf # # Bds diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc index 66f1b6ab94d2..52ad0f2cea94 100755 --- a/Platform/Ampere/JadePkg/Jade.dsc +++ b/Platform/Ampere/JadePkg/Jade.dsc @@ -68,6 +68,11 @@ [LibraryClasses] AcpiHelperLib|Platform/Ampere/Library/AcpiHelperLib/AcpiHelperLib.inf AcpiPccLib|Platform/Ampere/Library/AcpiPccLib/AcpiPccLib.inf + # + # Pcie Board + # + PcieBoardLib|Platform/Ampere/JadePkg/Library/Pcie/BoardPcie.inf + ################################################################################ # # Specific Platform Pcds diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf index 8efbd79461de..d38b20989407 100755 --- a/Platform/Ampere/JadePkg/Jade.fdf +++ b/Platform/Ampere/JadePkg/Jade.fdf @@ -306,6 +306,7 @@ [FV.FvMain] # PCIe Support # INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf # # UEFI application (Shell Embedded Boot Loader) -- 2.17.1