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X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Dec 2020 09:24:11.5109 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-Network-Message-Id: d99620ae-07d0-49b3-d63b-08d89c243056 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6cU3uzVo7wnYU0rRCtlql7oXr4MuvJ4+p4u/y8vdfWW7tDMw4z2ko+LQbgcLeRohlHZNH4/YFLraXqVTxY+VX1YuyyvbGQFBqSlPZrPKLM4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR01MB5609 Content-Type: text/plain From: Vu Nguyen Provides minimalist modules support for Ampere Altra silicon and Jade platform for basic booting to UiApp. Signed-off-by: Vu Nguyen --- Platform/Ampere/AmperePkg.dec | 28 + Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec | 40 ++ Silicon/Ampere/AmperePkg.dec | 63 ++ Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dsc.inc | 705 ++++++++++++++++++++ Platform/Ampere/JadePkg/Jade.dsc | 85 +++ Platform/Ampere/JadePkg/Jade.fdf | 279 ++++++++ Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.inf | 63 ++ Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.inf | 56 ++ Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.inf | 34 + Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.inf | 46 ++ Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.inf | 61 ++ Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf | 63 ++ Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.inf | 35 + Silicon/Ampere/AmpereAltraPkg/Library/NVParamDxeLib/NVParamDxeLib.inf | 35 + Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.inf | 32 + Silicon/Ampere/AmpereAltraPkg/Library/PMProLib/PMProLib.inf | 33 + Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.inf | 42 ++ Silicon/Ampere/AmpereAltraPkg/Library/SMProLib/SMProLib.inf | 41 ++ Silicon/Ampere/Drivers/ATFHobPei/ATFHobPeim.inf | 39 ++ Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunicate.h | 22 + Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h | 253 +++++++ Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h | 19 + Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h | 131 ++++ Silicon/Ampere/AmpereAltraPkg/Include/Library/PMProLib.h | 72 ++ Silicon/Ampere/AmpereAltraPkg/Include/Library/SMProInterface.h | 101 +++ Silicon/Ampere/AmpereAltraPkg/Include/Library/SMProLib.h | 105 +++ Silicon/Ampere/AmpereAltraPkg/Include/MmLib.h | 79 +++ Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h | 421 ++++++++++++ Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h | 182 +++++ Silicon/Ampere/AmpereAltraPkg/Include/PlatformInfoHob.h | 202 ++++++ Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.c | 145 ++++ Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.c | 424 ++++++++++++ Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.c | 36 + Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c | 641 ++++++++++++++++++ Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c | 198 ++++++ Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLibMemory.c | 388 +++++++++++ Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.c | 90 +++ Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.c | 183 +++++ Silicon/Ampere/AmpereAltraPkg/Library/NVParamDxeLib/NVParamDxeLib.c | 295 ++++++++ Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c | 200 ++++++ Silicon/Ampere/AmpereAltraPkg/Library/PMProLib/PMPro.c | 209 ++++++ Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.c | 46 ++ Silicon/Ampere/AmpereAltraPkg/Library/SMProLib/SMPro.c | 263 ++++++++ Silicon/Ampere/Drivers/ATFHobPei/ATFHobPeim.c | 52 ++ Platform/Ampere/FvRules.fdf.inc | 176 +++++ Platform/Ampere/JadePkg/TestKeys/Dbb_AmpereTest.cer.pem | 19 + Platform/Ampere/JadePkg/TestKeys/Dbb_AmpereTest.priv.pem | 28 + Platform/Ampere/JadePkg/jade_board_setting.txt | 187 ++++++ Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformHelper.S | 45 ++ 49 files changed, 6992 insertions(+) diff --git a/Platform/Ampere/AmperePkg.dec b/Platform/Ampere/AmperePkg.dec new file mode 100755 index 000000000000..e6a73b25286c --- /dev/null +++ b/Platform/Ampere/AmperePkg.dec @@ -0,0 +1,28 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x0001001B + PACKAGE_NAME = Ampere + PACKAGE_GUID = 7A78F1B2-E9BE-4F94-891C-385ED524036C + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes] + +[LibraryClasses] + +[Guids] diff --git a/Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec b/Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec new file mode 100644 index 000000000000..acf5a9621a4c --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec @@ -0,0 +1,40 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x0001001B + PACKAGE_NAME = Ac01Pkg + PACKAGE_GUID = 481F7D0D-7525-4B76-AF12-58E7B82C46C2 + PACKAGE_VERSION = 0.1 + +[Includes] + Include + +[LibraryClasses] + ## @libraryclass Defines a set of methods to retrieve CPU info. + AmpereCpuLib|Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h + + ## @libraryclass Defines a set of methods to get/set NVParam. + NVParamLib|Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h + + ## @libraryclass Defines a set of methods to communicate with SMPro. + SMProLib|Silicon/Ampere/AmpereAltraPkg/Include/Library/SMProLib.h + + ## @libraryclass Defines a set of methods to communicate with secure parition over MM interface. + MmCommunicationLib|Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h + + ## @libraryclass Defines a set of methods to communicate with PMPro. + PMProLib|Silicon/Ampere/AmpereAltraPkg/Include/Library/PMProLib.h + +[Guids] + + ## SPI NOR Proxy MM GUID + gSpiNorMmGuid = { 0xC8D76438, 0x4D3C, 0x4BEA, { 0xBF, 0x86, 0x92, 0x6B, 0x83, 0x07, 0xA2, 0x39 } } + + ## NVParam MM GUID + gNVParamMmGuid = { 0xE4AC5024, 0x29BE, 0x4ADC, { 0x93, 0x36, 0x87, 0xB5, 0xA0, 0x76, 0x23, 0x2D } } diff --git a/Silicon/Ampere/AmperePkg.dec b/Silicon/Ampere/AmperePkg.dec new file mode 100755 index 000000000000..47b29f508185 --- /dev/null +++ b/Silicon/Ampere/AmperePkg.dec @@ -0,0 +1,63 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION = 0x0001001B + PACKAGE_NAME = AmperePkg + PACKAGE_GUID = F9EB69A8-7569-4C0E-87D1-3CC9EB7CBF09 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] + +[LibraryClasses] + +[Guids] + gAmpereTokenSpaceGuid = { 0xdbd4436e, 0x89cb, 0x44dc, { 0xb5, 0xc0, 0x49, 0xc3, 0x91, 0x35, 0xbf, 0xdf } } + +[Ppis] + +[PcdsFixedAtBuild] + # + # SMPro PMPro Pcds + # + gAmpereTokenSpaceGuid.PcdSmproDb|0x0|UINT8|0x00000002 + gAmpereTokenSpaceGuid.PcdSmproDbBaseReg|0x100000540000|UINT64|0x00000003 + gAmpereTokenSpaceGuid.PcdSmproEfuseShadow0|0x10000054a000|UINT64|0x00000004 + gAmpereTokenSpaceGuid.PcdSmproI2cBmcBusAddr|0x2f|UINT32|0x00000005 + gAmpereTokenSpaceGuid.PcdSmproNsMailboxIndex|0x1|UINT32|0x00000006 + gAmpereTokenSpaceGuid.PcdPmproDbBaseReg|0x100001540000|UINT64|0x00000007 + + # + # Default Turbo Frequency Pcd + # + gAmpereTokenSpaceGuid.PcdTurboDefaultFreq|3350000000|UINT64|0x00000008 + + # + # SMBIOS Type 1 Pcd + # + gAmpereTokenSpaceGuid.PcdSmbiosTables1MajorVersion|0|UINT8|0xB0000009 + gAmpereTokenSpaceGuid.PcdSmbiosTables1MinorVersion|0|UINT8|0xB000000A + +[PcdsFixedAtBuild, PcdsDynamic] + # + # Firmware Volume Pcds + # + gAmpereTokenSpaceGuid.PcdFvPeiBaseAddress|0|UINT64|0xA0000000 + gAmpereTokenSpaceGuid.PcdFvPeiSize|0|UINT32|0xA0000001 + gAmpereTokenSpaceGuid.PcdFvMainCoreBaseAddress|0|UINT64|0xA0000002 + gAmpereTokenSpaceGuid.PcdFvMainCoreSize|0|UINT32|0xA0000003 + gAmpereTokenSpaceGuid.PcdFvBlockSize|0x00040000|UINT32|0xA0000004 diff --git a/Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dsc.inc b/Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dsc.inc new file mode 100755 index 000000000000..4ee79342283b --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dsc.inc @@ -0,0 +1,705 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICATION] + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x1000 + +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000 + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG + +[LibraryClasses.common] +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + + # + # Allow dynamic PCDs + # + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf + + # Consumed by IScsiDxe module + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + RngLib|MdePkg/Library/DxeRngLib/DxeRngLib.inf + + # ARM Libraries + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf + + # ARM Architectural Libraries + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf + + ResetSystemLib|ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf + + # + # Ampere Altra specific Libraries + # + ArmPlatformLib|Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.inf + PlatformPeiLib|Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.inf + NVParamLib|Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.inf + SMProLib|Silicon/Ampere/AmpereAltraPkg/Library/SMProLib/SMProLib.inf + PMProLib|Silicon/Ampere/AmpereAltraPkg/Library/PMProLib/PMProLib.inf + AmpereCpuLib|Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.inf + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf + MmCommunicationLib|Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.inf + + RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf + + # ARM PL011 UART Driver + PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf + PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartClockLib.inf + + # Timer Library + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf + + # + # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window + # in the debugger will show load and unload commands for symbols. You can cut and paste this + # into the command window to load symbols. We should be able to use a script to do this, but + # the version of RVD I have does not support scripts accessing system memory. + # + #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf + #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf + + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf + + # + # BDS Libraries + # + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + + # + # UEFI Shell libraries + # + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + + # + # Secure Boot dependencies + # +!if $(SECURE_BOOT_ENABLE) == TRUE + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + + # re-use the UserPhysicalPresent() dummy implementation from the ovmf tree + PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf + + # Networking Requirements +!if $(NETWORK_TLS_ENABLE) == TRUE + TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf +!endif + + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf + + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + +[LibraryClasses.common.SEC] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + +!ifdef $(EDK2_SKIP_PEICORE) + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf +!endif + + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf + # Specific ArmPlatformLib + +[LibraryClasses.common.PEI_CORE] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + +[LibraryClasses.common.PEIM] + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf + +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM] + MemoryInitPeiLib|Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf + +[LibraryClasses.common.DXE_DRIVER] + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiTianoCustomDecompressLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + + # UiApp dependencies + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf +!if $(SECURE_BOOT_ENABLE) == TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif +!if $(TARGET) != RELEASE + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf +!endif + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf + + EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + NVParamLib|Silicon/Ampere/AmpereAltraPkg/Library/NVParamDxeLib/NVParamDxeLib.inf + +[LibraryClasses.ARM,LibraryClasses.AARCH64] + # + # It is not possible to prevent the ARM compiler for generic intrinsic functions. + # This library provides the instrinsic functions generate by a given compiler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + # Add support for GCC stack protector + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|FALSE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|FALSE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle + ## created by ConsplitterDxe. It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + +[PcdsFixedAtBuild.common] +!ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" +!endif + + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + + # DEBUG_ASSERT_ENABLED 0x01 + # DEBUG_PRINT_ENABLED 0x02 + # DEBUG_CODE_ENABLED 0x04 + # CLEAR_MEMORY_ENABLED 0x08 + # ASSERT_BREAKPOINT_ENABLED 0x10 + # ASSERT_DEADLOOP_ENABLED 0x20 +!if $(TARGET) == RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F +!endif + + ## SBSA Watchdog Count +!ifndef DISABLE_SBSA_WATCHDOG + gArmPlatformTokenSpaceGuid.PcdWatchdogCount|1 +!endif + + # DEBUG_INIT 0x00000001 // Initialization + # DEBUG_WARN 0x00000002 // Warnings + # DEBUG_LOAD 0x00000004 // Load events + # DEBUG_FS 0x00000008 // EFI File system + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) + # DEBUG_INFO 0x00000040 // Informational debug messages + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers + # DEBUG_VARIABLE 0x00000100 // Variable + # DEBUG_BM 0x00000400 // Boot Manager + # DEBUG_BLKIO 0x00001000 // BlkIo Driver + # DEBUG_NET 0x00004000 // SNP Driver + # DEBUG_UNDI 0x00010000 // UNDI Driver + # DEBUG_LOADFILE 0x00020000 // LoadFile + # DEBUG_EVENT 0x00080000 // Event messages + # DEBUG_GCD 0x00100000 // Global Coherency Database changes + # DEBUG_CACHE 0x00200000 // Memory range cachability changes + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may + # // significantly impact boot performance + # DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL) + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + # + # Optional feature to help prevent EFI memory map fragments + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob + # Values are in EFI Pages (4K). DXE Core will make sure that + # at least this much of each type of memory can be allocated + # from a single memory range. This way you only end up with + # maximum of two fragements for each type in the memory map + # (the memory used, and the free memory that was prereserved + # but not used). + # + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + gArmTokenSpaceGuid.PcdArmPrimaryCore|0x0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 + + # Stacks for MPCores in Normal World + # Non-Trusted SRAM + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x91100000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x20000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000 + + # System Memory Base + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x90000000 + + # Firmware Volume + gArmTokenSpaceGuid.PcdFvBaseAddress|0x92000000 + gArmTokenSpaceGuid.PcdFvSize|0x007c0000 + + # UEFI region size + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000 + + # + # Ampere Altra Core-Cluster profile + # + gArmPlatformTokenSpaceGuid.PcdCoreCount|80 + gArmPlatformTokenSpaceGuid.PcdClusterCount|40 + + # + # PL011 - Serial Terminal + # Ampere Altra UART0 + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x100002600000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|32 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|1843200 + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x62 + + # + # PL011 - Serial Debug UART + # Ampere Altra UART2 + # + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x100002620000 + gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200 + + # RunAxf support via Dynamic Shell Command protocol + # We want to use the Shell Libraries but don't want it to initialise + # automatically. We initialise the libraries when the command is called by the + # Shell. + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE + + # + # ARM SBSA Watchdog + # + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x1000027c0000 + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x1000027d0000 + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|92 + + # + # ARM Generic Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0x100100000000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x100100140000 + + # + # ARM Architectural Timer Frequency + # + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000 + gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000 + + # use the TTY terminal type + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4 + + # GUID of the UI app + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 } + + # + # Enable strict image permissions for all images. (This applies + # only to images that were built with >= 4 KB section alignment.) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3 + + # + # Enable NX memory protection for all non-code regions, including OEM and OS + # reserved ones, with the exception of LoaderData regions, of which OS loaders + # (i.e., GRUB) may assume that its contents are executable. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC000000000007FD1 + + # + # Enable the non-executable DXE stack. (This gets set up by DxeIpl) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack|TRUE + + # + # MmCommunication + # + gArmTokenSpaceGuid.PcdMmBufferBase|0x88300000 + gArmTokenSpaceGuid.PcdMmBufferSize|0x100000 + +[PcdsDynamicHii.common.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|10 + +[PcdsDynamicDefault.common] + # Fist DRAM Memory region under 4GB address range + gArmTokenSpaceGuid.PcdSystemMemorySize|0x90000000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0 + +################################################################################ +# +# Component Section - list of all EDK II Component Entries defined by this Platform +# +################################################################################ + +[Components.common] + # + # PEI Phase modules + # + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + Silicon/Ampere/Drivers/ATFHobPei/ATFHobPeim.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + UefiCpuPkg/CpuIoPei/CpuIoPei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } + MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + + # + # DXE Phase modules + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + + # + # PCD + # + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) == TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf + } + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.inf + + # + # Environment Variables Protocol + # + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE + + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + + # + # Timer + # + ArmPkg/Drivers/TimerDxe/TimerDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + # + # ARM GIC Dxe + # + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + # + # Uefi Cpu + # + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + + # + # Console + # + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # Simple TextIn/TextOut for UEFI Terminal + EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + + # + # Hii Database + # + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # Semi-hosting filesystem + # + ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + FatPkg/EnhancedFatDxe/Fat.inf + + # + # SCSI Bus and Disk Driver + # + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + + # + # SATA Support + # + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + + # + # NVME Support + # + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # USB Support + # + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # PCIe Support + # + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Application/UiApp/UiApp.inf { + + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf + } + + # + # Networking stack + # +!include NetworkPkg/Network.dsc.inc + + # + # UEFI application (Shell Embedded Boot Loader) + # + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } +!ifdef $(INCLUDE_TFTP_COMMAND) + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + # + # EBC + # + MdeModulePkg/Universal/EbcDxe/EbcDxe.inf diff --git a/Platform/Ampere/JadePkg/Jade.dsc b/Platform/Ampere/JadePkg/Jade.dsc new file mode 100755 index 000000000000..c14bb62e02e8 --- /dev/null +++ b/Platform/Ampere/JadePkg/Jade.dsc @@ -0,0 +1,85 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Jade + PLATFORM_GUID = 7BDD00C0-68F3-4CC1-8775-F0F00572019F + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x0001001B + OUTPUT_DIRECTORY = Build/Jade + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Ampere/JadePkg/Jade.fdf + + # + # Defines for default states. These can be changed on the command line. + # -D FLAG=VALUE + # + DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x8000000F + DEFINE FIRMWARE_VER = 0.01.001 + DEFINE EDK2_SKIP_PEICORE = TRUE + DEFINE SECURE_BOOT_ENABLE = FALSE + DEFINE INCLUDE_TFTP_COMMAND = TRUE + + # + # Network definition + # + DEFINE NETWORK_IP6_ENABLE = TRUE + DEFINE NETWORK_HTTP_BOOT_ENABLE = TRUE + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE + DEFINE NETWORK_TLS_ENABLE = TRUE + +# Include default Ampere Platform DSC file +!include Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dsc.inc + +################################################################################ +# +# Specific Platform Library +# +################################################################################ +[LibraryClasses] + +################################################################################ +# +# Specific Platform Pcds +# +################################################################################ + +[PcdsFixedAtBuild] +!ifdef $(FIRMWARE_VER) + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)" +!endif + +[PcdsFixedAtBuild.common] +!if $(SECURE_BOOT_ENABLE) == TRUE + # Override the default values from SecurityPkg to ensure images + # from all sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04 +!endif + +[PcdsPatchableInModule] + # + # Console Resolution (HD mode) + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768 + +################################################################################ +# +# Specific Platform Component +# +################################################################################ +[Components.common] diff --git a/Platform/Ampere/JadePkg/Jade.fdf b/Platform/Ampere/JadePkg/Jade.fdf new file mode 100755 index 000000000000..db6a6abf0359 --- /dev/null +++ b/Platform/Ampere/JadePkg/Jade.fdf @@ -0,0 +1,279 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.BL33_JADE_UEFI] +BaseAddress = 0x92000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +Size = 0x007C0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x40000 +NumBlocks = 0x1F + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +# +# FV_PEI +# Offset: 0x00000000 +# Size: 0x000C0000 +# +0x00000000|0x000C0000 +gAmpereTokenSpaceGuid.PcdFvPeiBaseAddress|gAmpereTokenSpaceGuid.PcdFvPeiSize +FV = FV_PEI + +# +# NV Variables +# Offset: 0x000C0000 +# Size: 0x00080000 +# T.B.D +# + +# +# NVRAM Backup +# Offset: 0x00140000 +# Size: 0x00080000 +# T.B.D +# + +# +# FV_MAIN +# Offset: 0x001C0000 +# Size: 0x00600000 +# +0x001C0000|0x00600000 +gAmpereTokenSpaceGuid.PcdFvMainCoreBaseAddress|gAmpereTokenSpaceGuid.PcdFvMainCoreSize +FV = FvMain + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FV_PEI] +BlockSize = 0x40000 +NumBlocks = 0x3 +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 61C0F511-A691-4F54-974F-B9A42172CE53 + +APRIORI PEI { + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + +} + + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF Silicon/Ampere/Drivers/ATFHobPei/ATFHobPeim.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + +[FV.FvMain] +BlockSize = 0x40000 +NumBlocks = 0x18 +FvAlignment = 16 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE +FvNameGuid = 5C60F367-A505-419A-859E-2A4FF6CA6FE5 + +APRIORI DXE { + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.inf +} + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) == TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf +!endif + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.inf + + # + # Environment Variables Protocol + # + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # Timer + # + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + + # + # ARM GIC Dxe + # + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # SCSI Bus and Disk Driver + # + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + + # + # SATA Support + # + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + INF MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf + + # + # NVME Support + # + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # USB Support + # + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # PCIe Support + # + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellPkg/Application/Shell/Shell.inf +!if $(INCLUDE_TFTP_COMMAND) == TRUE + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + + # + # Networking stack + # +!include NetworkPkg/Network.fdf.inc + + # + # EFI Byte Code + # + INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf + +!include Platform/Ampere/FvRules.fdf.inc diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.inf new file mode 100755 index 000000000000..5b8adcee3a92 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.inf @@ -0,0 +1,63 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = MemoryInit + FILE_GUID = AC939A4D-D185-463F-A0CE-4120BF0ACF79 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeMemory + +[Sources] + MemoryInitPeim.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec + +[LibraryClasses] + PeimEntryPoint + DebugLib + HobLib + ArmLib + ArmPlatformLib + MemoryInitPeiLib + +[Guids] + gEfiMemoryTypeInformationGuid + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize + + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[Depex] + TRUE diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.inf new file mode 100644 index 000000000000..46af3e447172 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.inf @@ -0,0 +1,56 @@ +#/** @file +# +# DXE MM Communicate driver +# +# Copyright (c) 2016 - 2018, ARM Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = ArmMmCommunication + FILE_GUID = 09EE81D3-F15E-43F4-85B4-CB9873DA5D6B + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = MmCommunicationInitialize + +# +# The following is for reference only and not required by +# build tools +# +# VALID_ARCHITECTURES = AARCH64 +# + +[Sources.AARCH64] + MmCommunication.c + MmCommunicate.h + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + ArmLib + ArmSmcLib + BaseMemoryLib + DebugLib + DxeServicesTableLib + HobLib + UefiDriverEntryPoint + +[Protocols] + gEfiMmCommunicationProtocolGuid ## PRODUCES + +[Guids] + gEfiEndOfDxeEventGroupGuid + gEfiEventExitBootServicesGuid + gEfiEventReadyToBootGuid + +[Pcd.common] + gArmTokenSpaceGuid.PcdMmBufferBase + gArmTokenSpaceGuid.PcdMmBufferSize + +[Depex] + gEfiCpuArchProtocolGuid diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.inf b/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.inf new file mode 100755 index 000000000000..110658b33e56 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.inf @@ -0,0 +1,34 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = MmCommunicationPei + FILE_GUID = B5AE0F80-DF81-11EA-8B6E-0800200C9A66 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = MmCommunicationPeiEntryPoint + +[Sources] + MmCommunicationPei.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + HobLib + PcdLib + PeimEntryPoint + +[Pcd] + gArmTokenSpaceGuid.PcdMmBufferBase + gArmTokenSpaceGuid.PcdMmBufferSize + +[Depex] + TRUE diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.inf new file mode 100644 index 000000000000..b6b66201513a --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.inf @@ -0,0 +1,46 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = AmpereCpuLib + FILE_GUID = 4ACE898C-4DDC-4EF7-BB6C-91549BDF5B9C + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = AmpereCpuLib + +[Sources] + AmpereCpuLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Ampere/AmperePkg.dec + Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec + +[LibraryClasses] + BaseLib + HobLib + IoLib + NVParamLib + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PcdClusterCount + + gAmpereTokenSpaceGuid.PcdTurboDefaultFreq + gAmpereTokenSpaceGuid.PcdSmproDb + gAmpereTokenSpaceGuid.PcdSmproDbBaseReg + gAmpereTokenSpaceGuid.PcdSmproEfuseShadow0 + gAmpereTokenSpaceGuid.PcdSmproI2cBmcBusAddr + gAmpereTokenSpaceGuid.PcdSmproNsMailboxIndex + +[Depex] + TRUE diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.inf new file mode 100755 index 000000000000..7d8f292aa17c --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.inf @@ -0,0 +1,61 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = ArmPlatformLib + FILE_GUID = 7F829BB1-5092-4D8E-8FB7-2B2C2A80D783 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Sources] + ArmPlatformLib.c + ArmPlatformLibMemory.c + ArmPlatformHelper.S + +[LibraryClasses] + IoLib + ArmLib + ArmSmcLib + MemoryAllocationLib + PL011UartLib + SerialPortLib + PcdLib + HobLib + AmpereCpuLib + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Ampere/AmperePkg.dec + Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdMmBufferBase + gArmTokenSpaceGuid.PcdMmBufferSize + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdClusterCount + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmPlatformTokenSpaceGuid.PcdClusterCount + gArmTokenSpaceGuid.PcdSystemMemoryBase + + gArmTokenSpaceGuid.PcdArmPrimaryCore + + gArmPlatformTokenSpaceGuid.PL011UartClkInHz + + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf new file mode 100755 index 000000000000..357a63f2950b --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.inf @@ -0,0 +1,63 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = ArmMemoryInitPeiLib + FILE_GUID = 55DDB6E0-70B5-11E0-B33E-0002A5D5C51B + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformPeiLib + +[Sources] + MemoryInitPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Ampere/AmperePkg.dec + Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec + +[LibraryClasses] + DebugLib + HobLib + ArmLib + ArmMmuLib + ArmPlatformLib + +[Guids] + gEfiMemoryTypeInformationGuid + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize + + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + +[Depex] + TRUE diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.inf new file mode 100755 index 000000000000..bfca80cec8e7 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.inf @@ -0,0 +1,35 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = MmCommunicationLib + FILE_GUID = 106099B8-0051-4B35-9578-EFB1045D2FA8 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = MmCommunicationLib + CONSTRUCTOR = MmCommunicationLibConstructor + +[Sources] + MmCommunicationLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec + +[LibraryClasses] + ArmLib + ArmSmcLib + BaseMemoryLib + DebugLib + PcdLib + +[Pcd] + gArmTokenSpaceGuid.PcdMmBufferBase + gArmTokenSpaceGuid.PcdMmBufferSize diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamDxeLib/NVParamDxeLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamDxeLib/NVParamDxeLib.inf new file mode 100644 index 000000000000..aa5926d8f9fe --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamDxeLib/NVParamDxeLib.inf @@ -0,0 +1,35 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = NVParamDxeLib + FILE_GUID = 501DF419-0DC0-43E5-841A-98F645F15ECA + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 0.1 + LIBRARY_CLASS = NVParamDxeLib + CONSTRUCTOR = NVParamLibConstructor + +[Sources.common] + NVParamDxeLib.c + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + +[Guids] + gNVParamMmGuid + +[Protocols] + gEfiMmCommunicationProtocolGuid diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.inf new file mode 100755 index 000000000000..d427856afcef --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.inf @@ -0,0 +1,32 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = NVParamLib + FILE_GUID = 8512FF56-11DF-4A16-A0CF-81B27DBD23FB + MODULE_TYPE = BASE + VERSION_STRING = 0.1 + LIBRARY_CLASS = NVParamLib + +[Sources.common] + NVParamLib.c + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + MmCommunicationLib + +[Guids] + gNVParamMmGuid diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PMProLib/PMProLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/PMProLib/PMProLib.inf new file mode 100644 index 000000000000..f008dd4e8610 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PMProLib/PMProLib.inf @@ -0,0 +1,33 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = PMPro + FILE_GUID = 2E533FEA-8A5B-11EA-BC55-0242AC130003 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PMProLib + +[Sources.common] + PMPro.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Ampere/AmperePkg.dec + Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + IoLib + TimerLib + +[FixedPcd] + gAmpereTokenSpaceGuid.PcdPmproDbBaseReg diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.inf new file mode 100644 index 000000000000..197ec6d6c3b9 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.inf @@ -0,0 +1,42 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = ArmPlatformPeiLib + FILE_GUID = 49D37060-70B5-11E0-AA2D-0002A5D5C51B + MODULE_TYPE = SEC + VERSION_STRING = 0.1 + LIBRARY_CLASS = PlatformPeiLib + +[Sources] + PlatformPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Ampere/AmperePkg.dec + Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec + +[LibraryClasses] + ArmLib + ArmSmcLib + DebugLib + HobLib + PeiServicesLib + ArmPlatformLib + PcdLib + +[FixedPcd] + gAmpereTokenSpaceGuid.PcdFvMainCoreBaseAddress + gAmpereTokenSpaceGuid.PcdFvMainCoreSize + +[Depex] + TRUE diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/SMProLib/SMProLib.inf b/Silicon/Ampere/AmpereAltraPkg/Library/SMProLib/SMProLib.inf new file mode 100644 index 000000000000..e4ac431582fd --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/SMProLib/SMProLib.inf @@ -0,0 +1,41 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = SMPro + FILE_GUID = 844B9D12-984F-4138-BDF1-412A638AAC89 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SMProLib + +[Sources.common] + SMPro.c + +[Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Ampere/AmperePkg.dec + Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec + +[LibraryClasses] + ArmLib + ArmPlatformLib + BaseLib + BaseMemoryLib + DebugLib + TimerLib + +[FixedPcd] + gAmpereTokenSpaceGuid.PcdSmproDb + gAmpereTokenSpaceGuid.PcdSmproDbBaseReg + gAmpereTokenSpaceGuid.PcdSmproEfuseShadow0 + gAmpereTokenSpaceGuid.PcdSmproI2cBmcBusAddr + gAmpereTokenSpaceGuid.PcdSmproNsMailboxIndex diff --git a/Silicon/Ampere/Drivers/ATFHobPei/ATFHobPeim.inf b/Silicon/Ampere/Drivers/ATFHobPei/ATFHobPeim.inf new file mode 100644 index 000000000000..9e4a0c453bac --- /dev/null +++ b/Silicon/Ampere/Drivers/ATFHobPei/ATFHobPeim.inf @@ -0,0 +1,39 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x0001001B + BASE_NAME = ATFHobPeim + FILE_GUID = B1975734-77C2-4827-9617-914883F3B578 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = InitializeATFHobPeim + +[Sources] + ATFHobPeim.c + +[FixedPcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Ampere/AmperePkg.dec + Silicon/Ampere/AmpereAltraPkg/Ac01Pkg.dec + +[LibraryClasses] + BaseLib + DebugLib + PeimEntryPoint + HobLib + PcdLib + PeiServicesLib + +[Depex] + TRUE diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunicate.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunicate.h new file mode 100644 index 000000000000..d1b31b9e6c95 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunicate.h @@ -0,0 +1,22 @@ +/** @file + + Copyright (c) 2016-2018, ARM Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_COMMUNICATE_H_ +#define _MM_COMMUNICATE_H_ + +#define MM_MAJOR_VER_MASK 0xEFFF0000 +#define MM_MINOR_VER_MASK 0x0000FFFF +#define MM_MAJOR_VER_SHIFT 16 + +#define MM_MAJOR_VER(x) (((x) & MM_MAJOR_VER_MASK) >> MM_MAJOR_VER_SHIFT) +#define MM_MINOR_VER(x) ((x) & MM_MINOR_VER_MASK) + +#define MM_CALLER_MAJOR_VER 0x1UL +#define MM_CALLER_MINOR_VER 0x0 + +#endif /* _MM_COMMUNICATE_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h new file mode 100644 index 000000000000..d5ba18ba89be --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h @@ -0,0 +1,253 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _AMPERE_CPU_LIB_H_ +#define _AMPERE_CPU_LIB_H_ + +/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */ +#define CLIDR_CTYPE_SHIFT(Level) (3 * (Level - 1)) +#define CLIDR_CTYPE_MASK(Level) (7 << CLIDR_CTYPE_SHIFT(Level)) +#define CLIDR_CTYPE(Clidr, Level) \ + (((Clidr) & CLIDR_CTYPE_MASK(Level)) >> CLIDR_CTYPE_SHIFT(Level)) + +#define CCSIDR_NUMSETS_SHIFT 13 +#define CCSIDR_NUMSETS_MASK 0xFFFE000 +#define CCSIDR_NUMSETS(Ccsidr) \ + (((Ccsidr) & CCSIDR_NUMSETS_MASK) >> CCSIDR_NUMSETS_SHIFT) +#define CCSIDR_ASSOCIATIVITY_SHIFT 3 +#define CCSIDR_ASSOCIATIVITY_MASK 0x1FF8 +#define CCSIDR_ASSOCIATIVITY(Ccsidr) \ + (((Ccsidr) & CCSIDR_ASSOCIATIVITY_MASK) >> CCSIDR_ASSOCIATIVITY_SHIFT) +#define CCSIDR_LINE_SIZE_SHIFT 0 +#define CCSIDR_LINE_SIZE_MASK 0x7 +#define CCSIDR_LINE_SIZE(Ccsidr) \ + (((Ccsidr) & CCSIDR_LINE_SIZE_MASK) >> CCSIDR_LINE_SIZE_SHIFT) + +#define SOC_EFUSE_SHADOWn(s,x) (SMPRO_EFUSE_SHADOW0 + (s) * SOCKET_BASE_OFFSET + (x) * 4) + +#define SUBNUMA_MODE_MONOLITHIC 0 +#define SUBNUMA_MODE_HEMISPHERE 1 +#define SUBNUMA_MODE_QUADRANT 2 + +/** + Get the SubNUMA mode. + + @return UINT8 The SubNUMA mode. + +**/ +UINT8 +EFIAPI +CPUGetSubNumaMode (VOID); + +/** + Get the number of SubNUMA region. + + @return UINT8 The number of SubNUMA region. + +**/ +UINT8 +EFIAPI +CPUGetNumOfSubNuma (VOID); + +/** + Get the SubNUMA node of a CPM. + + @param SocketId Socket index. + @param Cpm CPM index. + @return UINT8 The SubNUMA node of a CPM. + +**/ +UINT8 +EFIAPI +CPUGetSubNumNode ( + UINT8 Socket, + UINT32 Cpm + ); + +/** + Get the value of CLIDR register. + + @return UINT64 The value of CLIDR register. + +**/ +UINT64 +EFIAPI +AArch64ReadCLIDRReg (); + +/** + Get the value of CCSID register. + + @param Level Cache level. + @return UINT64 The value of CCSID register. + +**/ +UINT64 +EFIAPI +AArch64ReadCCSIDRReg ( + UINT64 Level + ); + +/** + Get the associativity of cache. + + @param Level Cache level. + @return UINT32 Associativity of cache. + +**/ +UINT32 +EFIAPI +CpuGetAssociativity ( + UINTN Level + ); + +/** + Get the cache size. + + @param Level Cache level. + @return UINT32 Cache size. + +**/ +UINT32 +EFIAPI +CpuGetCacheSize ( + UINTN Level + ); + +/** + Get the number of supported socket. + + @return UINT32 Number of supported socket. + +**/ +UINT32 +EFIAPI +GetNumberSupportedSockets (VOID); + +/** + Get the number of active socket. + + @return UINT32 Number of active socket. + +**/ +UINT32 +EFIAPI +GetNumberActiveSockets (VOID); + +/** + Get the number of active CPM per socket. + + @param SocketId Socket index. + @return UINT32 Number of CPM. + +**/ +UINT32 +EFIAPI +GetNumberActiveCPMsPerSocket ( + UINT32 SocketId + ); + +/** + Get the configured number of CPM per socket. + + @param SocketId Socket index. + @return UINT32 Configured number of CPM. + +**/ +UINT32 +EFIAPI +GetConfiguredNumberCPMs ( + IN UINTN Socket + ); + +/** + Set the configured number of CPM per socket. + + @param SocketId Socket index. + @param Number Number of CPM to be configured. + @return EFI_SUCCESS Operation succeeded. + @return Others An error has occurred. + +**/ +EFI_STATUS +EFIAPI +SetConfiguredNumberCPMs ( + UINTN Socket, + UINTN Number + ); + +/** + Get the maximum number of core per socket. This number + should be the same for all sockets. + + @return UINT32 Maximum number of core. + +**/ +UINT32 +EFIAPI +GetMaximumNumberOfCores (VOID); + +/** + Get the maximum number of CPM per socket. This number + should be the same for all sockets. + + @return UINT32 Maximum number of CPM. + +**/ +UINT32 +EFIAPI +GetMaximumNumberCPMs (VOID); + +/** + Get the number of active cores of a sockets. + + @return UINT32 Number of active core. + +**/ +UINT32 +EFIAPI +GetNumberActiveCoresPerSocket ( + UINT32 SocketId + ); + +/** + Get the number of active cores of all socket. + + @return UINT32 Number of active core. + +**/ +UINT32 +EFIAPI +GetNumberActiveCores (VOID); + +/** + Check if the logical CPU is enabled or not. + + @param CpuId The logical Cpu ID. Started from 0. + @return BOOLEAN TRUE if the Cpu enabled + FALSE if the Cpu disabled/ + +**/ +BOOLEAN +EFIAPI +IsCpuEnabled ( + UINTN CpuId + ); + + +/** + Check if the slave socket is present + + @return BOOLEAN TRUE if the Slave Cpu present + FALSE if the Slave Cpu present + +**/ +BOOLEAN +EFIAPI +PlatSlaveSocketPresent (VOID); + +#endif /* _AMPERE_CPU_LIB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h new file mode 100755 index 000000000000..0d7841f98c82 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h @@ -0,0 +1,19 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_COMMUNICATION_LIB_H_ +#define _MM_COMMUNICATION_LIB_H_ + +EFI_STATUS +EFIAPI +MmCommunicationCommunicate ( + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommSize OPTIONAL + ); + +#endif /* _MM_COMMUNICATION_LIB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h new file mode 100755 index 000000000000..c12ef66e7ee4 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h @@ -0,0 +1,131 @@ +/** @file + + The non-volatile parameter layout in SPI-NOR is shown below. There is + two copies. The master copy is changeable by the user. The Last Known + copy is handled by the fail safe future. It is a last know bootable copy. + + --------------------------- + | Master Copy | 16KB + | Pre-boot parameters | + --------------------------- + | Master Copy | 16KB + | Pre-boot parameters | + | w/o failsafe support | + --------------------------- + | Master Copy | + | Manufactory & | 32KB + | Users parameters | + --------------------------- + | Last Known Copy | 16KB + | Pre-boot parameters | + --------------------------- + | | 16KB + --------------------------- + | Last Known Copy | + | Manufactory & | 32KB + | Users parameters | + --------------------------- + + As each non-volatile parameter requires 8 bytes, there is a total of 8K + parameters. + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _NV_PARAM_LIB_H_ +#define _NV_PARAM_LIB_H_ + +#define NV_PARAM_MAX_SIZE (64 * 1024) +#define NV_PARAM_ENTRYSIZE 8 + +#define NV_PERM_ALL 0xFFFF /* Allowed for all */ +#define NV_PERM_ATF 0x0001 /* Allowed for EL3 code */ +#define NV_PERM_OPTEE 0x0004 /* Allowed for secure El1 */ +#define NV_PERM_BIOS 0x0008 /* Allowed for EL2 non-secure */ +#define NV_PERM_MANU 0x0010 /* Allowed for manufactory interface */ +#define NV_PERM_BMC 0x0020 /* Allowed for BMC interface */ + +#define NVPARAM_SIZE 0x8 + +/* + * Retrieve a non-volatile parameter + * + * @param: Parameter ID to retrieve + * @acl_rd: Permission for read operation. See NV_PERM_XXX. + * @val: Pointer to an UINT32 to store the value + * @return: EFI_INVALID_PARAMETER if parameter is invalid + * EFI_NOT_FOUND if value is not set + * EFI_UNSUPPORTED if service unavailable + * EFI_ACCESS_DENIED if permission not allowed + * Otherwise, 0 for success + * + * NOTE: If you need a signed value, cast it. It is expected that the + * caller will carry the correct permission over various call sequences. + * + */ +EFI_STATUS +NVParamGet ( + IN UINT32 Param, + IN UINT16 ACLRd, + OUT UINT32 *Val + ); + +/* + * Set a non-volatile parameter + * + * @param: Parameter ID to set + * @acl_rd: Permission for read operation + * @acl_wr: Permission for write operation + * @val: Unsigned int value to set. + * @return: EFI_INVALID_PARAMETER if parameter is invalid + * EFI_UNSUPPORTED if service unavailable + * EFI_ACCESS_DENIED if permission not allowed + * Otherwise, 0 for success + * + * NOTE: If you have a signed value, cast to unsigned. If the parameter has + * not being created before, the provied permission is used to create the + * parameter. Otherwise, it is checked for access. It is expected that the + * caller will carry the correct permission over various call sequences. + * + */ +EFI_STATUS +NVParamSet ( + IN UINT32 Param, + IN UINT16 ACLRd, + IN UINT16 ACLWr, + IN UINT32 Val + ); + +/* + * Clear a non-volatile parameter + * + * @param: Parameter ID to set + * @acl_wr: Permission for write operation + * @return: EFI_INVALID_PARAMETER if parameter is invalid + * EFI_UNSUPPORTED if service unavailable + * EFI_ACCESS_DENIED if permission not allowed + * Otherwise, 0 for success + * + * NOTE: It is expected that the caller will carry the correct permission + * over various call sequences. + * + */ +EFI_STATUS +NVParamClr ( + IN UINT32 Param, + IN UINT16 ACLWr + ); + +/* + * Clear all non-volatile parameters + * + * @return: EFI_UNSUPPORTED if service unavailable + * Otherwise, 0 for success + */ +EFI_STATUS +NVParamClrAll (VOID); + +#endif /* _NV_PARAM_LIB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/PMProLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/PMProLib.h new file mode 100644 index 000000000000..697a27a43a85 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/PMProLib.h @@ -0,0 +1,72 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PMPRO_LIB_H_ +#define _PMPRO_LIB_H_ + +#include + +/* + * Write the message to the doorbell + * Db Doorbell number + * Data Data to be written to DB OUT + * Param Data to be written to DB OUT0 + * Param1 Data to be written to DB OUT1 + * MsgReg Non-secure doorbell base virtual address + */ +EFI_STATUS +EFIAPI +PMProDBWr ( + UINT8 Db, + UINT32 Data, + UINT32 Param, + UINT32 Param1, + UINT64 MsgReg + ); + +/* + * Send Turbo enable message to PMpro + * + * Enable Enable value + */ +EFI_STATUS +EFIAPI +PMProTurboEnable ( + UINT8 Socket, + UINT8 Enable + ); + +/* + * Send PSCI Statistic address to ACL + * Socket Socket to send address to + * AdrHi Upper 32 bits of the address + * AdrLo Lower 32 bits of the address + */ +EFI_STATUS +EFIAPI +PMProAclAdd ( + UINT8 Socket, + UINT32 AdrHi, + UINT32 AdrLo + ); + +/* + * Send PSCI Statistic address to PMPro + * Socket Socket to send address to + * AdrHi Upper 32 bits of the address + * AdrLo Lower 32 bits of the address + */ +EFI_STATUS +EFIAPI +PMProSendPSCIAddr ( + UINT8 Socket, + UINT32 AdrHi, + UINT32 AdrLo + ); + +#endif /* _PMPRO_LIB_H_*/ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/SMProInterface.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/SMProInterface.h new file mode 100755 index 000000000000..96510ab17eaa --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/SMProInterface.h @@ -0,0 +1,101 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMPRO_INTERFACE_H_ +#define _SMPRO_INTERFACE_H_ + +#define IPP_ENCODE_OK_MSG (1 << 28) + +/* SMPro common definition */ +#define SMPRO_MSG_TYPE_SHIFT 28 +#define SMPRO_DEBUG_MSG 0 +#define SMPRO_USER_MSG 6 + +#define SMPRO_DBGMSG_TYPE_SHIFT 24 +#define SMPRO_DBGMSG_TYPE_MASK 0x0F000000U + +#define SMPRO_USER_TYPE_SHIFT 24 +#define SMPRO_USER_TYPE_MASK 0x0F000000U + +/* SMPro I2C message encode */ +#define SMPRO_I2C_PROTOCOL 0 +#define SMPRO_SMB_PROTOCOL 1 + +#define SMPRO_I2C_RD 0 +#define SMPRO_I2C_WR 1 + +#define SMPRO_DBG_SUBTYPE_I2C1READ 4 +#define SMPRO_I2C_DEV_SHIFT 23 +#define SMPRO_I2C_DEV_MASK 0x00800000 +#define SMPRO_I2C_DEVID_SHIFT 13 +#define SMPRO_I2C_DEVID_MASK 0x007FE000 +#define SMPRO_I2C_RW_SHIFT 12 +#define SMPRO_I2C_RW_MASK 0x00001000 +#define SMPRO_I2C_PROTO_SHIFT 11 +#define SMPRO_I2C_PROTO_MASK 0x00000800 +#define SMPRO_I2C_ADDRLEN_SHIFT 8 +#define SMPRO_I2C_ADDRLEN_MASK 0x00000700 +#define SMPRO_I2C_DATALEN_SHIFT 0 +#define SMPRO_I2C_DATALEN_MASK 0x000000FF + +#define SMPRO_I2C_ENCODE_MSG(dev, chip, op, proto, addrlen, datalen) \ + ((SMPRO_DEBUG_MSG << SMPRO_MSG_TYPE_SHIFT) | \ + ((SMPRO_DBG_SUBTYPE_I2C1READ << SMPRO_DBGMSG_TYPE_SHIFT) & \ + SMPRO_DBGMSG_TYPE_MASK) | \ + ((dev << SMPRO_I2C_DEV_SHIFT) & SMPRO_I2C_DEV_MASK) | \ + ((chip << SMPRO_I2C_DEVID_SHIFT) & SMPRO_I2C_DEVID_MASK) | \ + ((op << SMPRO_I2C_RW_SHIFT) & SMPRO_I2C_RW_MASK) | \ + ((proto << SMPRO_I2C_PROTO_SHIFT) & SMPRO_I2C_PROTO_MASK) | \ + ((addrlen << SMPRO_I2C_ADDRLEN_SHIFT) & SMPRO_I2C_ADDRLEN_MASK) | \ + ((datalen << SMPRO_I2C_DATALEN_SHIFT) & SMPRO_I2C_DATALEN_MASK)) + +#define SMPRO_I2C_ENCODE_FLAG_BUFADDR 0x80000000 +#define SMPRO_I2C_ENCODE_UPPER_DATABUF(a) \ + ((UINT32)(((UINT64)(a) >> 12) & 0x3FF00000)) +#define SMPRO_I2C_ENCODE_LOWER_DATABUF(a) \ + ((UINT32)((UINT64)(a) & 0xFFFFFFFF)) +#define SMPRO_I2C_ENCODE_DATAADDR(a) ((UINT64)(a) & 0xFFFF) + +#define SMPRO_USER_MSG_P0_SHIFT 8 +#define SMPRO_USER_MSG_P0_MASK 0x0000FF00U +#define SMPRO_USER_MSG_P1_SHIFT 0 +#define SMPRO_USER_MSG_P1_MASK 0x000000FFU + +/* SMPro Boot Process message encode */ +#define SMPRO_USER_SUBTYPE_BOOTPROCESS 6 +#define SMPRO_BOOT_PROCESS_ENCODE_MSG(msg1,msg2) \ + ((SMPRO_USER_MSG << SMPRO_MSG_TYPE_SHIFT) | \ + ((SMPRO_USER_SUBTYPE_BOOTPROCESS << SMPRO_USER_TYPE_SHIFT) & \ + SMPRO_USER_TYPE_MASK) | \ + (((msg1) << SMPRO_USER_MSG_P0_SHIFT) & SMPRO_USER_MSG_P0_MASK) | \ + (((msg2) << SMPRO_USER_MSG_P1_SHIFT) & SMPRO_USER_MSG_P1_MASK)) + +#define SMPRO_USER_SUBTYPE_RNG 7 +#define SMPRO_RNG_ENCODE_MSG(msg1,msg2) \ + ((SMPRO_USER_MSG << SMPRO_MSG_TYPE_SHIFT) | \ + ((SMPRO_USER_SUBTYPE_RNG << SMPRO_USER_TYPE_SHIFT) & \ + SMPRO_USER_TYPE_MASK) | \ + (((msg1) << SMPRO_USER_MSG_P0_SHIFT) & SMPRO_USER_MSG_P0_MASK) | \ + (((msg2) << SMPRO_USER_MSG_P1_SHIFT) & SMPRO_USER_MSG_P1_MASK)) + +#define IPP_DBGMSG_TYPE_SHIFT 24 +#define IPP_DBGMSG_TYPE_MASK 0x0F000000 +#define IPP_DEBUG_MSG 0x0 +#define IPP_DBG_SUBTYPE_REGREAD 0x1 +#define IPP_DBG_SUBTYPE_REGWRITE 0x2 +#define IPP_DBGMSG_P0_MASK 0x0000FF00 +#define IPP_DBGMSG_P0_SHIFT 8 +#define IPP_DBGMSG_P1_MASK 0x000000FF +#define IPP_DBGMSG_P1_SHIFT 0 +#define IPP_ENCODE_DEBUG_MSG(type, cb, p0, p1) \ + ((IPP_DEBUG_MSG << IPP_MSG_TYPE_SHIFT) | (((type) << IPP_DBGMSG_TYPE_SHIFT) & \ + IPP_DBGMSG_TYPE_MASK) | (((cb) << IPP_MSG_CONTROL_BYTE_SHIFT) & \ + IPP_MSG_CONTROL_BYTE_MASK) | (((p0) << IPP_DBGMSG_P0_SHIFT) & \ + IPP_DBGMSG_P0_MASK) | (((p1) << IPP_DBGMSG_P1_SHIFT) & IPP_DBGMSG_P1_MASK)) + +#endif /* _SMPRO_INTERFACE_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/SMProLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/SMProLib.h new file mode 100755 index 000000000000..200f8790b42e --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/SMProLib.h @@ -0,0 +1,105 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SMPRO_LIB_H_ +#define _SMPRO_LIB_H_ + +/* + * Read the doorbell status into data + * Db Doorbell number + * Data Data to be written from DB IN + * Param Data to be written from DB IN0 + * Param1 Data to be written from DB IN1 + * MsgReg Non-secure doorbell base virtual address + */ +EFI_STATUS +EFIAPI +SMProDBRd ( + UINT8 Db, + UINT32 *Data, + UINT32 *Param, + UINT32 *Param1, + UINT64 MsgReg + ); + +/* + * Write the message to the doorbell + * Db Doorbell number + * Data Data to be written to DB OUT + * Param Data to be written to DB OUT0 + * Param1 Data to be written to DB OUT1 + * MsgReg Non-secure doorbell base virtual address + */ +EFI_STATUS +EFIAPI +SMProDBWr ( + UINT8 Db, + UINT32 Data, + UINT32 Param, + UINT32 Param1, + UINT64 MsgReg + ); + +/* + * Send an APEI Check Message to SMPro + * + * UAddress Upper 32-bit of a 64-bit register for the APEI table pointer + * LAddress Lower 32-bit of a 64-bit register for the APEI table pointer + */ +EFI_STATUS +EFIAPI +SMProAPEISetupCheck ( + UINT32 UAddress, + UINT32 LAddress + ); + +/* + * Send an APEI Clear Message to SMPro + * + * UAddress Upper 32-bit of a 64-bit register for the APEI table pointer + * LAddress Lower 32-bit of a 64-bit register for the APEI table pointer + */ +EFI_STATUS +EFIAPI +SMProAPEISetupClear ( + UINT32 UAddress, + UINT32 LAddress + ); + +/* + * Enable/Disable APEI with SMPro + */ +EFI_STATUS +EFIAPI +SMProAPEIEnable ( + UINT8 Enable + ); + +/* + * Read register from SMPro + */ +EFI_STATUS +EFIAPI +SMProRegRd ( + UINT8 Socket, + UINT64 Addr, + UINT32 *Value + ); + +/* + * Write register to SMPro + */ +EFI_STATUS +EFIAPI +SMProRegWr ( + UINT8 Socket, + UINT64 Addr, + UINT32 Value + ); + +#endif /* _SMPRO_LIB_H_*/ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/MmLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/MmLib.h new file mode 100644 index 000000000000..bcb682ee3925 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/MmLib.h @@ -0,0 +1,79 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MM_LIB_H_ +#define _MM_LIB_H_ + +enum { + MM_SPINOR_FUNC_GET_INFO, + MM_SPINOR_FUNC_READ, + MM_SPINOR_FUNC_WRITE, + MM_SPINOR_FUNC_ERASE, + MM_SPINOR_FUNC_GET_NVRAM_INFO, + MM_SPINOR_FUNC_GET_NVRAM2_INFO, + MM_SPINOR_FUNC_GET_FAILSAFE_INFO +}; + +enum { + MM_NVPARAM_FUNC_READ = 1, + MM_NVPARAM_FUNC_WRITE, + MM_NVPARAM_FUNC_CLEAR, + MM_NVPARAM_FUNC_CLEAR_ALL +}; + +#define MM_SPINOR_RES_SUCCESS 0xAABBCC00 +#define MM_SPINOR_RES_FAIL 0xAABBCCFF + +#define MM_NVPARAM_RES_SUCCESS 0xAABBCC00 +#define MM_NVPARAM_RES_NOT_SET 0xAABBCC01 +#define MM_NVPARAM_RES_NO_PERM 0xAABBCC02 +#define MM_NVPARAM_RES_FAIL 0xAABBCCFF + +#define EFI_MM_MAX_PAYLOAD_U64_E 10 +#define EFI_MM_MAX_PAYLOAD_SIZE (EFI_MM_MAX_PAYLOAD_U64_E * sizeof(UINT64)) +#define EFI_MM_MAX_TMP_BUF_SIZE 0x1000000 + +typedef struct { + /* Allows for disambiguation of the message format */ + EFI_GUID HeaderGuid; + /* + * Describes the size of Data (in bytes) and does not include the size + * of the header + */ + UINTN MsgLength; +} EFI_MM_COMM_HEADER_NOPAYLOAD; + +typedef struct { + UINT64 Data[EFI_MM_MAX_PAYLOAD_U64_E]; +} EFI_MM_COMM_PAYLOAD; + +typedef struct { + EFI_MM_COMM_HEADER_NOPAYLOAD EfiMmHdr; + EFI_MM_COMM_PAYLOAD PayLoad; +} EFI_MM_COMM_REQUEST; + +typedef struct { + UINT64 Status; + UINT64 DeviceBase; + UINT64 PageSize; + UINT64 SectorSize; + UINT64 DeviceSize; +} EFI_MM_COMMUNICATE_SPINOR_RES; + +typedef struct { + UINT64 Status; + UINT64 NVBase; + UINT64 NVSize; +} EFI_MM_COMMUNICATE_SPINOR_NVINFO_RES; + +typedef struct { + UINT64 Status; + UINT64 Value; +} EFI_MM_COMMUNICATE_NVPARAM_RES; + +#endif /* _MM_LIB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h b/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h new file mode 100644 index 000000000000..1074b47298ed --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h @@ -0,0 +1,421 @@ +/** @file + + The non-volatile parameter layout in SPI-NOR is shown below. There is + two copies. The master copy is changeable by the user. The Last Known + copy is handled by the fail safe future. It is a last know bootable copy. + + --------------------------- + | Master Copy | 16KB + | Pre-boot parameters | + --------------------------- + | Master Copy | 16KB + | Pre-boot parameters | + | w/o failsafe support | + --------------------------- + | Master Copy | + | Manufactory & | 32KB + | Users parameters | + --------------------------- + | Last Known Copy | 16KB + | Pre-boot parameters | + --------------------------- + | | 16KB + --------------------------- + | Last Known Copy | + | Manufactory & | 32KB + | Users parameters | + --------------------------- + + As each non-volatile parameter requires 8 bytes, there is a total of 8K + parameters. + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _NVPARAMDEF_H_ +#define _NVPARAMDEF_H_ + +typedef enum { + /* + * SoC validation pre-boot non-volatile setting + * + * These parameters will reset to default value on failsafe. + * They are not used in production life cycle. + */ + NV_PREBOOT_PARAM_START = 0x000000, + NV_SI_PCP_VDMC = (1 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_FAILSAFE_RETRY = (2 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_PPR_EN = (3 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RESERVED0 = (4 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RESERVED1 = (5 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_LOG_LEVEL = (6 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RESERVED2 = (7 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RD_DBI_EN = (8 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_WR_DBI_EN = (9 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RETRY_EN = (10 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_BANK_HASH_EN = (11 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RESERVED3 = (12 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RCD_PARITY_EN = (13 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RESERVED4 = (14 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_IOCAL_MARGIN = (15 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RTR_S_MARGIN = (16 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RTR_L_MARGIN = (17 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RTR_CS_MARGIN = (18 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_WTW_S_MARGIN = (19 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_WTW_L_MARGIN = (20 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_WTW_CS_MARGIN = (21 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RTW_S_MARGIN = (22 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RTW_L_MARGIN = (23 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RTW_CS_MARGIN = (24 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_WTR_S_MARGIN = (25 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_WTR_L_MARGIN = (26 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_WTR_CS_MARGIN = (27 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_PARITY_EN = (28 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_SLC_DISABLE = (29 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_SLC_SIZE = (30 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_SLC_SCRUB = (31 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_CCIX_DISABLE = (32 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_ESM_SPEED = (33 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_PHY_CAL_MODE = (34 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_RAS_TEST_EN = (35 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_EYE_SCREEN_TEST_EN = (36 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_EYE_MASK_RD_MARGIN = (37 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_EYE_MASK_WR_MARGIN = (38 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RDODT_ON_MARGIN = (39 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_RDODT_OFF_MARGIN = (40 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_WRODT_ON_MARGIN = (41 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_WRODT_OFF_MARGIN = (42 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_SLC_OCM_EN = (43 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_ESM_WIDTH = (44 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_TM2_DISABLE = (45 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_CPUPLL_FREQ_MHZ = (46 * 8) + NV_PREBOOT_PARAM_START, + NV_PMPRO_REGION1_LOAD_START = NV_SI_CCIX_DISABLE, + NV_PMPRO_REGION1_LOAD_END = NV_SI_CPUPLL_FREQ_MHZ, + NV_SI_DDR_ERR_INJECT_MASK_SK0 = (47 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_ERR_INJECT_MASK_SK1 = (48 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_CXG_DISABLE_EARLY_COMPACK = (49 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_CXG_ENABLE_SAME_ADDR_COMP_ORDER = (50 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_TURNAROUND_CONTROL = (51 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_HIT_TURNAROUND_CONTROL = (52 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_QOS_CLASS_CONTROL = (53 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_ESCALATION_CONTROL = (54 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_QV_CONTROL_31_00 = (55 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_QV_CONTROL_63_32 = (56 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_CREDIT_CONTROL = (57 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_WRITE_PRIORITY_CONTROL_31_00 = (58 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_WRITE_PRIORITY_CONTROL_63_32 = (59 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_QUEUE_THRESHOLD_CONTROL_31_00 = (60 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_QUEUE_THRESHOLD_CONTROL_63_32 = (61 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_ATF_FAILURE_FAILSAFE = (62 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_UEFI_FAILURE_FAILSAFE = (63 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_STRIPE_DECODE = (64 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_DEBUG_CTRL = (65 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_CXG_RA_DEVNR_ORD_WFC_DIS = (66 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_PHY_DLL_TRACK_UPD_THRESHOLD = (67 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_PHY_DLL_TRACK_UPD_THRESHOLD_AC = (68 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_PHY_INIT_UPDATE_CONFIG = (69 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_PHY_UPDATE_CONTROL = (70 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_PROFILE_EN = (71 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_PCIE_PHY_SETTING = (72 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_PHY_CAL_THRESHOLD = (73 * 8) + NV_PREBOOT_PARAM_START, + NV_SI_DDR_PHY_CAL_INTERVAL_CNT = (74 * 8) + NV_PREBOOT_PARAM_START, + /* NOTE: Add before NV_PREBOOT_PARAM_MAX and increase its value */ + NV_PREBOOT_PARAM_MAX = (74 * 8) + NV_PREBOOT_PARAM_START, + + /* + * Manufactory non-volatile memory + * + * These parameters will reset to default value on failsafe. + */ + NV_MANU_PARAM_START = 0x004000, + NV_SI_DDR_VMARGIN = (0 * 8) + NV_MANU_PARAM_START, + NV_PMPRO_REGION2_LOAD_START = NV_SI_DDR_VMARGIN, + NV_SI_SOC_VMARGIN = (1 * 8) + NV_MANU_PARAM_START, + NV_SI_AVS_VMARGIN = (2 * 8) + NV_MANU_PARAM_START, + NV_SI_TPC_TM1_MARGIN = (3 * 8) + NV_MANU_PARAM_START, + NV_SI_TPC_TM2_MARGIN = (4 * 8) + NV_MANU_PARAM_START, + NV_SI_TPC_FREQ_THROTTLE = (5 * 8) + NV_MANU_PARAM_START, + NV_SI_T_LTLM_EN = (6 * 8) + NV_MANU_PARAM_START, + NV_SI_T_LTLM_THRSHLD = (7 * 8) + NV_MANU_PARAM_START, + NV_SI_T_GTLM_THRSHLD = (8 * 8) + NV_MANU_PARAM_START, + NV_SI_P_LM_EN = (9 * 8) + NV_MANU_PARAM_START, + NV_SI_P_LM_THRSHLD = (10 * 8) + NV_MANU_PARAM_START, + NV_SI_TPC_OVERTEMP_ISR_DISABLE = (11 * 8) + NV_MANU_PARAM_START, + NV_SI_VPP_VMARGIN = (12 * 8) + NV_MANU_PARAM_START, + NV_SI_PMPRO_FAILURE_FAILSAFE = (13 * 8) + NV_MANU_PARAM_START, + NV_SI_FAILSAFE_DISABLE = (14 * 8) + NV_MANU_PARAM_START, + NV_SI_PLIMIT_PM1_BURST_THRSHLD_MS = (15 * 8) + NV_MANU_PARAM_START, + NV_SI_PLIMIT_PM1_BREAK_THRSHLD_MS = (16 * 8) + NV_MANU_PARAM_START, + NV_SI_PLIMIT_PM1_PERCENTAGE_TDP = (17 * 8) + NV_MANU_PARAM_START, + NV_SI_CPU_LPI_FREQ_DISABLE = (18 * 8) + NV_MANU_PARAM_START, + NV_SI_CPU_LPI_FREQ_ENERGY_THRSHLD = (19 * 8) + NV_MANU_PARAM_START, + NV_SI_CCIX_OPT_CONFIG = (20 * 8) + NV_MANU_PARAM_START, + NV_SI_MESH_FREQ_MARGIN = (21 * 8) + NV_MANU_PARAM_START, + NV_SI_MESH_TURBO_EN = (22 * 8) + NV_MANU_PARAM_START, + NV_SI_PWR_HEADROOM_WATT = (23 * 8) + NV_MANU_PARAM_START, + NV_SI_EXTRA_PCP_VOLT_MV = (24 * 8) + NV_MANU_PARAM_START, + NV_SI_CPU_LPI_HYST_CNT = (25 * 8) + NV_MANU_PARAM_START, + NV_PMPRO_REGION2_LOAD_END = NV_SI_CPU_LPI_HYST_CNT, + /* NOTE: Add before NV_MANU_PARAM_MAX and increase its value */ + NV_MANU_PARAM_MAX = (25 * 8) + NV_MANU_PARAM_START, + + /* + * User non-volatile memory + * + * These parameters will reset to default value on failsafe. + */ + NV_USER_PARAM_START = 0x008000, + NV_SI_S0_PCP_ACTIVECPM_0_31 = (0 * 8) + NV_USER_PARAM_START, + NV_SI_S0_PCP_ACTIVECPM_32_63 = (1 * 8) + NV_USER_PARAM_START, + NV_SI_S1_PCP_ACTIVECPM_0_31 = (2 * 8) + NV_USER_PARAM_START, + NV_SI_S1_PCP_ACTIVECPM_32_63 = (3 * 8) + NV_USER_PARAM_START, + NV_PMPRO_REGION3_LOAD_START = NV_SI_S0_PCP_ACTIVECPM_0_31, + NV_PMPRO_REGION3_LOAD_END = NV_SI_S1_PCP_ACTIVECPM_32_63, + NV_SI_WDT_BIOS_EXP_MINS = (4 * 8) + NV_USER_PARAM_START, + NV_SI_DDR_CE_RAS_THRESHOLD = (5 * 8) + NV_USER_PARAM_START, + NV_SI_DDR_CE_RAS_INTERVAL = (6 * 8) + NV_USER_PARAM_START, + NV_SI_DDR_SPEED = (7 * 8) + NV_USER_PARAM_START, + NV_SI_DDR_SCRUB_EN = (8 * 8) + NV_USER_PARAM_START, + NV_SI_DDR_ECC_MODE = (9 * 8) + NV_USER_PARAM_START, + NV_SI_S0_RCA_PCI_DEVMAP = (10 * 8) + NV_USER_PARAM_START, + NV_SI_S0_RCB_PCI_DEVMAP = (11 * 8) + NV_USER_PARAM_START, + NV_SI_S1_RCA_PCI_DEVMAP = (12 * 8) + NV_USER_PARAM_START, + NV_SI_S1_RCB_PCI_DEVMAP = (13 * 8) + NV_USER_PARAM_START, + NV_SI_DDR_ERRCTRL = (14 * 8) + NV_USER_PARAM_START, + NV_SI_DDR_REFRESH_GRANULARITY = (15 * 8) + NV_USER_PARAM_START, + NV_SI_SUBNUMA_MODE = (16 * 8) + NV_USER_PARAM_START, + NV_SI_ERRATUM_1542419_WA = (17 * 8) + NV_USER_PARAM_START, + NV_SI_NEAR_ATOMIC_DISABLE = (18 * 8) + NV_USER_PARAM_START, + NV_SI_DDR_SLAVE_32BIT_MEM_EN = (19 * 8) + NV_USER_PARAM_START, + NV_SI_CPUECTLR_EL1_0_31 = (20 * 8) + NV_USER_PARAM_START, + NV_SI_CPUECTLR_EL1_32_63 = (21 * 8) + NV_USER_PARAM_START, + NV_SI_HARDWARE_EINJ = (22 * 8) + NV_USER_PARAM_START, + NV_SI_2P_CE_RAS_THRESHOLD = (23 * 8) + NV_USER_PARAM_START, + NV_SI_2P_CE_RAS_INTERVAL = (24 * 8) + NV_USER_PARAM_START, + NV_SI_RAS_BERT_ENABLED = (25 * 8) + NV_USER_PARAM_START, + NV_SI_HNF_AUX_CTL_0_31 = (26 * 8) + NV_USER_PARAM_START, + NV_SI_HNF_AUX_CTL_32_63 = (27 * 8) + NV_USER_PARAM_START, + NV_SI_CPM_CE_RAS_THRESHOLD = (28 * 8) + NV_USER_PARAM_START, + NV_SI_CPM_CE_RAS_INTERVAL = (29 * 8) + NV_USER_PARAM_START, + NV_SI_HNF_AUX_CTL_0_31_WR_EN_MASK = (30 * 8) + NV_USER_PARAM_START, + NV_SI_HNF_AUX_CTL_32_63_WR_EN_MASK = (31 * 8) + NV_USER_PARAM_START, + NV_SI_DDR_WR_BACK_EN = (32 * 8) + NV_USER_PARAM_START, + NV_SI_CPUECTLR_EL1_0_31_WR_EN_MASK = (33 * 8) + NV_USER_PARAM_START, + NV_SI_CPUECTLR_EL1_32_63_WR_EN_MASK = (34 * 8) + NV_USER_PARAM_START, + NV_SI_LINK_ERR_THRESHOLD = (35 * 8) + NV_USER_PARAM_START, + NV_SI_SEC_WDT_BIOS_EXP_MINS = (36 * 8) + NV_USER_PARAM_START, + NV_SI_NVDIMM_MODE = (37 * 8) + NV_USER_PARAM_START, + NV_SI_RAS_SDEI_ENABLED = (38 * 8) + NV_USER_PARAM_START, + NV_SI_NVDIMM_PROV_MASK_S0 = (39 * 8) + NV_USER_PARAM_START, + NV_SI_NVDIMM_PROV_MASK_S1 = (40 * 8) + NV_USER_PARAM_START, + NV_SI_DDR_ZQCS_EN = (41 * 8) + NV_USER_PARAM_START, + NV_SI_DDR_CRC_MODE = (42 * 8) + NV_USER_PARAM_START, + /* NOTE: Add before NV_USER_PARAM_MAX and increase its value */ + NV_USER_PARAM_MAX = (42 * 8) + NV_USER_PARAM_START, + + /* + * Non-volatile board read-only setting + * + * These parameters do not support failsafe and will always read + * from its location. Please note that the physical base address + * location for board setting is not the same as above region. This + * allows packaging these board setting along with the firmware + * image itself. See SPI-NOR flash layout design for more info. + * + * Please note that script will parse these and generate + * board setting. The keyword "Default: " is used to provide + * the default value. + */ + NV_BOARD_PARAM_START = 0x00C000, + NV_SI_RO_BOARD_VENDOR = (0 * 8) + NV_BOARD_PARAM_START, /* Default: 0x0000CD3A - Follow BMC FRU format */ + NV_PMPRO_REGION4_LOAD_START = NV_SI_RO_BOARD_VENDOR, + NV_SI_RO_BOARD_TYPE = (1 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000000 - Follow BMC FRU format */ + NV_SI_RO_BOARD_REV = (2 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000000 Follow BMC FRU format */ + NV_SI_RO_BOARD_CFG = (3 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000000 Follow BMC FRU format */ + NV_SI_RO_BOARD_S0_DIMM_AVAIL = (4 * 8) + NV_BOARD_PARAM_START, /* Default: 0x0000FFFF */ + NV_SI_RO_BOARD_S1_DIMM_AVAIL = (5 * 8) + NV_BOARD_PARAM_START, /* Default: 0x0000FFFF */ + NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ = (6 * 8) + NV_BOARD_PARAM_START, /* Default: 33000 */ + NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ = (7 * 8) + NV_BOARD_PARAM_START, /* Default: 33000 */ + NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ = (8 * 8) + NV_BOARD_PARAM_START, /* Default: 10000 */ + NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ = (9 * 8) + NV_BOARD_PARAM_START, /* Default: 10000 */ + NV_SI_RO_BOARD_TPM_LOC = (10 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_I2C0_FREQ_KHZ = (11 * 8) + NV_BOARD_PARAM_START, /* Default: 400 */ + NV_SI_RO_BOARD_I2C1_FREQ_KHZ = (12 * 8) + NV_BOARD_PARAM_START, /* Default: 400 */ + NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ = (13 * 8) + NV_BOARD_PARAM_START, /* Default: 400 */ + NV_SI_RO_BOARD_I2C3_FREQ_KHZ = (14 * 8) + NV_BOARD_PARAM_START, /* Default: 400 */ + NV_SI_RO_BOARD_I2C9_FREQ_KHZ = (15 * 8) + NV_BOARD_PARAM_START, /* Default: 400 */ + NV_SI_RO_BOARD_2P_CFG = (16 * 8) + NV_BOARD_PARAM_START, /* Default: 0xFFFFFF01 */ + NV_SI_RO_BOARD_S0_RCA0_CFG = (17 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA1_CFG = (18 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA2_CFG = (19 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000004 */ + NV_SI_RO_BOARD_S0_RCA3_CFG = (20 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000004 */ + NV_SI_RO_BOARD_S0_RCB0_LO_CFG = (21 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S0_RCB0_HI_CFG = (22 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S0_RCB1_LO_CFG = (23 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S0_RCB1_HI_CFG = (24 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S0_RCB2_LO_CFG = (25 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S0_RCB2_HI_CFG = (26 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000003 */ + NV_SI_RO_BOARD_S0_RCB3_LO_CFG = (27 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000003 */ + NV_SI_RO_BOARD_S0_RCB3_HI_CFG = (28 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S1_RCA0_CFG = (29 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA1_CFG = (30 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA2_CFG = (31 * 8) + NV_BOARD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S1_RCA3_CFG = (32 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00030003 */ + NV_SI_RO_BOARD_S1_RCB0_LO_CFG = (33 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000003 */ + NV_SI_RO_BOARD_S1_RCB0_HI_CFG = (34 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S1_RCB1_LO_CFG = (35 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S1_RCB1_HI_CFG = (36 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000003 */ + NV_SI_RO_BOARD_S1_RCB2_LO_CFG = (37 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S1_RCB2_HI_CFG = (38 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S1_RCB3_LO_CFG = (39 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_S1_RCB3_HI_CFG = (40 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00020002 */ + NV_SI_RO_BOARD_T_LTLM_DELTA_P0 = (41 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000001 */ + NV_SI_RO_BOARD_T_LTLM_DELTA_P1 = (42 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000002 */ + NV_SI_RO_BOARD_T_LTLM_DELTA_P2 = (43 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000003 */ + NV_SI_RO_BOARD_T_LTLM_DELTA_P3 = (44 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000004 */ + NV_SI_RO_BOARD_T_LTLM_DELTA_M1 = (45 * 8) + NV_BOARD_PARAM_START, /* Default: 0xFFFFFFFF */ + NV_SI_RO_BOARD_T_LTLM_DELTA_M2 = (46 * 8) + NV_BOARD_PARAM_START, /* Default: 0xFFFFFFFE */ + NV_SI_RO_BOARD_T_LTLM_DELTA_M3 = (47 * 8) + NV_BOARD_PARAM_START, /* Default: 0xFFFFFFFD */ + NV_SI_RO_BOARD_P_LM_PID_P = (48 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_P_LM_PID_I = (49 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_P_LM_PID_I_L_THOLD = (50 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_P_LM_PID_I_H_THOLD = (51 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_P_LM_PID_D = (52 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST = (53 * 8) + NV_BOARD_PARAM_START, + /* + * NV_SI_RO_BOARD_TPM_ALG_ID: 0=Default to SHA256, 1=SHA1, 2=SHA256 + * Any other value will lead to default digest. + */ + NV_SI_RO_BOARD_TPM_ALG_ID = (54 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000002 */ + NV_SI_RO_BOARD_DDR_SPEED_GRADE = (55 * 8) + NV_BOARD_PARAM_START, /* Default: 3200 */ + NV_SI_RO_BOARD_DDR_S0_RTT_WR = (56 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_DDR_S1_RTT_WR = (57 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_DDR_S0_RTT_NOM = (58 * 8) + NV_BOARD_PARAM_START, /* Default: 0xFF010107 */ + NV_SI_RO_BOARD_DDR_S1_RTT_NOM = (59 * 8) + NV_BOARD_PARAM_START, /* Default: 0xFF010107 */ + NV_SI_RO_BOARD_DDR_S0_RTT_PARK = (60 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00010000 */ + NV_SI_RO_BOARD_DDR_S1_RTT_PARK = (61 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00010000 */ + NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_1DPC = (62 * 8) + NV_BOARD_PARAM_START, /* Default: 0x000000 */ + NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_1DPC = (63 * 8) + NV_BOARD_PARAM_START, /* Default: 0x000000 */ + NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_1DPC = (64 * 8) + NV_BOARD_PARAM_START, /* Default: 0x000000 */ + NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_1DPC = (65 * 8) + NV_BOARD_PARAM_START, /* Default: 0x000000 */ + NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_2DPC = (66 * 8) + NV_BOARD_PARAM_START, /* Default: 0x0C0CCC */ + NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_2DPC = (67 * 8) + NV_BOARD_PARAM_START, /* Default: 0x0C0CCC */ + NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_2DPC = (68 * 8) + NV_BOARD_PARAM_START, /* Default: 0x030333 */ + NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_2DPC = (69 * 8) + NV_BOARD_PARAM_START, /* Default: 0x030333 */ + NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_1DPC = (70 * 8) + NV_BOARD_PARAM_START, /* Default: 0x030333 */ + NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_1DPC = (71 * 8) + NV_BOARD_PARAM_START, /* Default: 0x030333 */ + NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_1DPC = (72 * 8) + NV_BOARD_PARAM_START, /* Default: 0x030333 */ + NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_1DPC = (73 * 8) + NV_BOARD_PARAM_START, /* Default: 0x030333 */ + NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_2DPC = (74 * 8) + NV_BOARD_PARAM_START, /* Default: 0x0D0DDD */ + NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_2DPC = (75 * 8) + NV_BOARD_PARAM_START, /* Default: 0x0E0EEE */ + NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_2DPC = (76 * 8) + NV_BOARD_PARAM_START, /* Default: 0x070777 */ + NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_2DPC = (77 * 8) + NV_BOARD_PARAM_START, /* Default: 0x0B0BBB */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_1DPC = (78 * 8) + NV_BOARD_PARAM_START, /* Default: 0x5 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_1DPC = (79 * 8) + NV_BOARD_PARAM_START, /* Default: 0x90DD90 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_1DPC = (80 * 8) + NV_BOARD_PARAM_START, /* Default: 0x5 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_1DPC = (81 * 8) + NV_BOARD_PARAM_START, /* Default: 0x90DD90 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_2DPC = (82 * 8) + NV_BOARD_PARAM_START, /* Default: 0x5 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_2DPC = (83 * 8) + NV_BOARD_PARAM_START, /* Default: 0x90DD90 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_2DPC = (84 * 8) + NV_BOARD_PARAM_START, /* Default: 0x5 */ + NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_2DPC = (85 * 8) + NV_BOARD_PARAM_START, /* Default: 0x90DD90 */ + NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_1DPC = (86 * 8) + NV_BOARD_PARAM_START, /* Default: 0x24 */ + NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_1DPC = (87 * 8) + NV_BOARD_PARAM_START, /* Default: 0x1A */ + NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_2DPC = (88 * 8) + NV_BOARD_PARAM_START, /* Default: 0x5B */ + NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_2DPC = (89 * 8) + NV_BOARD_PARAM_START, /* Default: 0x24 */ + NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_DEFAULT = (90 * 8) + NV_BOARD_PARAM_START, /* Default: 0x02800280 */ + NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_DEFAULT = (91 * 8) + NV_BOARD_PARAM_START, /* Default: 0x90909090 */ + NV_SI_RO_BOARD_DDR_WRDQS_SHIFT_DEFAULT = (92 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_DDR_ADCMD_DLY_DEFAULT = (93 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00C000C0 */ + NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_ADJ = (94 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_ADJ = (95 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_DDR_PHY_VREF_ADJ = (96 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_DDR_DRAM_VREF_ADJ = (97 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_DDR_WR_PREAMBLE_CYCLE = (98 * 8) + NV_BOARD_PARAM_START, /* Default: 0x02010201 */ + NV_SI_RO_BOARD_DDR_ADCMD_2T_MODE = (99 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00010000 */ + NV_SI_RO_BOARD_I2C_VRD_CONFIG_INFO = (100 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_DDR_PHY_FEATURE_CTRL = (101 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000000 */ + NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_ACCESS = (102 * 8) + NV_BOARD_PARAM_START, /* Default: 0x01050106 */ + NV_SI_RO_BOARD_DIMM_TEMP_THRESHOLD = (103 * 8) + NV_BOARD_PARAM_START, /* Default: 0x554 */ + NV_SI_RO_BOARD_DIMM_SPD_COMPARE_DISABLE = (104 * 8) + NV_BOARD_PARAM_START, /* Default: 0x0 */ + NV_SI_RO_BOARD_S0_PCIE_CLK_CFG = (105 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA4_CFG = (106 * 8) + NV_BOARD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S0_RCA5_CFG = (107 * 8) + NV_BOARD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S0_RCA6_CFG = (108 * 8) + NV_BOARD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S0_RCA7_CFG = (109 * 8) + NV_BOARD_PARAM_START, /* Default: 0x02020003 */ + NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET = (110 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET = (111 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET = (112 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET = (113 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET = (114 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET = (115 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET = (116 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB1B_TXRX_G3PRESET = (117 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB2A_TXRX_G3PRESET = (118 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET = (119 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET = (120 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET = (121 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET = (122 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET = (123 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET = (124 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET = (125 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET = (126 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET = (127 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET = (128 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA3_TXRX_G4PRESET = (129 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB0A_TXRX_G4PRESET = (130 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB0B_TXRX_G4PRESET = (131 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB1A_TXRX_G4PRESET = (132 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB1B_TXRX_G4PRESET = (133 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB2A_TXRX_G4PRESET = (134 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB2B_TXRX_G4PRESET = (135 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB3A_TXRX_G4PRESET = (136 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCB3B_TXRX_G4PRESET = (137 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA4_TXRX_G4PRESET = (138 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA5_TXRX_G4PRESET = (139 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA6_TXRX_G4PRESET = (140 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S0_RCA7_TXRX_G4PRESET = (141 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_PCIE_CLK_CFG = (142 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA4_CFG = (143 * 8) + NV_BOARD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S1_RCA5_CFG = (144 * 8) + NV_BOARD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S1_RCA6_CFG = (145 * 8) + NV_BOARD_PARAM_START, /* Default: 0x02020202 */ + NV_SI_RO_BOARD_S1_RCA7_CFG = (146 * 8) + NV_BOARD_PARAM_START, /* Default: 0x02020003 */ + NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET = (147 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA3_TXRX_G3PRESET = (148 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET = (149 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB0B_TXRX_G3PRESET = (150 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB1A_TXRX_G3PRESET = (151 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB1B_TXRX_G3PRESET = (152 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB2A_TXRX_G3PRESET = (153 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB2B_TXRX_G3PRESET = (154 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB3A_TXRX_G3PRESET = (155 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCB3B_TXRX_G3PRESET = (156 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA4_TXRX_G3PRESET = (157 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA5_TXRX_G3PRESET = (158 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA6_TXRX_G3PRESET = (159 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA7_TXRX_G3PRESET = (160 * 8) + NV_BOARD_PARAM_START, + NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET = (161 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCA3_TXRX_G4PRESET = (162 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB0A_TXRX_G4PRESET = (163 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB0B_TXRX_G4PRESET = (164 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB1A_TXRX_G4PRESET = (165 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB1B_TXRX_G4PRESET = (166 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB2A_TXRX_G4PRESET = (167 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB2B_TXRX_G4PRESET = (168 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB3A_TXRX_G4PRESET = (169 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCB3B_TXRX_G4PRESET = (170 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCA4_TXRX_G4PRESET = (171 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCA5_TXRX_G4PRESET = (172 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCA6_TXRX_G4PRESET = (173 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_S1_RCA7_TXRX_G4PRESET = (174 * 8) + NV_BOARD_PARAM_START, /* Default: 0x57575757 */ + NV_SI_RO_BOARD_2P_CE_MASK_THRESHOLD = (175 * 8) + NV_BOARD_PARAM_START, /* Default: 0x00000002 */ + NV_SI_RO_BOARD_2P_CE_MASK_INTERVAL = (176 * 8) + NV_BOARD_PARAM_START, /* Default: 0x000001A4 */ + NV_SI_RO_BOARD_SX_PHY_CFG_SETTING = (177 * 8) + NV_BOARD_PARAM_START, + NV_PMPRO_REGION4_LOAD_END = NV_SI_RO_BOARD_SX_PHY_CFG_SETTING, + /* NOTE: Add before NV_BOARD_PARAM_MAX and increase its value */ + NV_BOARD_PARAM_MAX = (177 * 8) + NV_BOARD_PARAM_START, +} NVPARAM; + +#endif /* _NVPARAMDEF_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h b/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h new file mode 100644 index 000000000000..7bf5adb91082 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h @@ -0,0 +1,182 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PLATFORM_AC01_H_ +#define __PLATFORM_AC01_H_ + +/* Number of supported sockets in the platform */ +#define PLATFORM_CPU_MAX_SOCKET 2 + +/* Maximum number of CPMs in the chip. */ +#define PLATFORM_CPU_MAX_CPM (FixedPcdGet32 (PcdClusterCount)) + +/* Number of cores per CPM. */ +#define PLATFORM_CPU_NUM_CORES_PER_CPM (FixedPcdGet32(PcdCoreCount) / PLATFORM_CPU_MAX_CPM) + +/* Socket bit offset of core UID. */ +#define PLATFORM_SOCKET_UID_BIT_OFFSET 16 + +/* CPM bit offset of core UID. */ +#define PLATFORM_CPM_UID_BIT_OFFSET 8 + +/* Maximum number of system locality supported. */ +#define PLATFORM_MAX_NUM_ACPI_SYSTEM_LOCALITIES 2 + +/* Default turbo frequency. */ +#define TURBO_DEFAULT_FREQ 3350000000 + +/* Maximum number of cores supported. */ +#define PLATFORM_CPU_MAX_NUM_CORES (PLATFORM_CPU_MAX_SOCKET * PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM) + +/* Maximum number of memory region */ +#define PLATFORM_DRAM_INFO_MAX_REGION 16 + +/* Maximum number of DDR slots supported */ +#define PLATFORM_DIMM_INFO_MAX_SLOT 32 + +/* Maximum number of memory supported. */ +#define PLATFORM_MAX_MEMORY_REGION 4 + +/* Maximum number of GIC ITS supported. */ +#define PLATFORM_MAX_NUM_GIC_ITS 1 + +/* The first SPI interrupt number of the Slave socket */ +#define PLATFORM_SLAVE_SOCKET_SPI_INTERRUPT_START 352 + +/* **PORTING NEEDED** Total number of Super IO serial ports present. */ +#define TOTAL_SIO_SERIAL_PORTS 1 + +#define SerialIo_SUPPORT 0 + +/* The base register of AHBC */ +#define AHBC_REGISTER_BASE 0x1f10c000 + +/* The base address of UART0 Register */ +#define UART0_REGISTER_BASE 0x12600000 + +/* The base address of UART1 Register */ +#define UART1_REGISTER_BASE 0x12610000 + +/* PCC Configuration */ +#define SMPRO_MAX_DB 8 +#define SMPRO_DB0_IRQ_NUM 40 + +#define PMPRO_MAX_DB 8 +#define PMPRO_DB0_IRQ_NUM 56 + +/* Non-secure Doorbell Mailbox to use between ARMv8 and SMpro */ +//#define SMPRO_NS_MAILBOX_INDEX 1 + +/* Non-secure Doorbell Mailbox to use between ARMv8 and SMpro */ +#define SMPRO_NS_RNG_MAILBOX_INDEX 6 + +#define PCC_MAX_SUBSPACES_PER_SOCKET (SMPRO_MAX_DB + PMPRO_MAX_DB) + +#define DB_OUT 0x00000010 +#define DB_OUT0 0x00000014 +#define DB_OUT1 0x00000018 +#define DB_STATUS 0x00000020 +#define DB_STATUSMASK 0x00000024 +#define DB_AVAIL_MASK 0x00010000 +#define DBx_BASE_OFFSET 0x00001000 + +/* Doorbell to use between ARMv8 and SMpro */ +#define SMPRO_DB 0 +#define PMPRO_DB 1 +#define SMPRO_DB_BASE_REG (FixedPcdGet64 (PcdSmproDbBaseReg)) +#define PMPRO_DB_BASE_REG (FixedPcdGet64 (PcdPmproDbBaseReg)) +#define SMPRO_EFUSE_SHADOW0 (FixedPcdGet64 (PcdSmproEfuseShadow0)) +#define SMPRO_NS_MAILBOX_INDEX (FixedPcdGet32 (PcdSmproNsMailboxIndex)) +#define SMPRO_I2C_BMC_BUS_ADDR (FixedPcdGet32 (PcdSmproI2cBmcBusAddr)) + +#define SOCKET_BASE_OFFSET 0x400000000000 +#define SMPRO_DBx_REG(socket, db, reg) \ + ((socket) * SOCKET_BASE_OFFSET + SMPRO_DB_BASE_REG + DBx_BASE_OFFSET * (db) + reg) + +#define PMPRO_DBx_REG(socket, db, reg) \ + ((socket) * SOCKET_BASE_OFFSET + PMPRO_DB_BASE_REG + DBx_BASE_OFFSET * (db) + reg) + +#define PCC_MAX_SUBSPACES ((SMPRO_MAX_DB + PMPRO_MAX_DB) * PLATFORM_CPU_MAX_SOCKET) +#define PCC_SUBSPACE_SHARED_MEM_SIZE 0x4000 + +#define PCC_NOMINAL_LATENCY 10000 /* 10 ms */ +#define PCC_CPPC_NOMINAL_LATENCY 1000 /* 1 ms */ +#define PCC_MAX_PERIOD_ACCESS 0 /* unlimited */ +#define PCC_MIN_REQ_TURNAROUND_TIME 0 /* unlimited */ +#define PCC_CMD_POLL_UDELAY 10 /* us */ +#define PCC_CPPC_MIN_REQ_TURNAROUND_TIME 110 /* 110 us */ + +#define PCC_SIGNATURE_MASK 0x50424300 +#define PCC_CPPC_SUBSPACE 2 /* Doorbell 2 of PMPro */ +#define PCC_MSG 0x53000040 +#define PCC_CPPC_MSG 0x00000100 +#define PCC_CPPC_URG_MSG 0x00800000 +#define PCC_256_ALIGN_ADDR 0x00000040 +#define PCC_MSG_SIZE 12 /* Num of Bytes */ +#define PCP_MSG_UPPER_ADDR_MASK 0xF + + +/* The Array of Soc Gpio Base Address */ +#define GPIO_DWAPB_BASE_ADDR 0x1000026f0000,0x1000026e0000,0x1000027b0000,0x1000026d0000,0x5000026f0000,0x5000026e0000,0x5000027b0000,0x5000026d0000 + +/* The Array of Soc Gpi Base Address */ +#define GPI_DWAPB_BASE_ADDR 0x1000026d0000,0x5000026d0000 + +/* Number of Pins Per Each Contoller */ +#define GPIO_DWAPB_PINS_PER_CONTROLLER 8 + +/* Number of Pins Each Socket */ +#define GPIO_DWAPB_PINS_PER_SOCKET 32 + +/* The maximum number of I2C bus */ +#define MAX_PLATFORM_I2C_BUS_NUM 2 + +/* The base address of DW I2C */ +#define PLATFORM_I2C_REGISTER_BASE 0x1000026B0000ULL, 0x100002750000ULL + +/* Offset of failsafe testing feature */ +#define NV_UEFI_FAILURE_FAILSAFE_OFFSET 0x1F8 + +/* Maximum number of nvdimm device supported */ +#define PLATFORM_MAX_NUM_NVDIMM_DEVICE 0x4 + +/* The base address of master socket GIC redistributor registers */ +#define GICR_MASTER_BASE_REG 0x100100140000 + +/* The base address of GIC distributor registers */ +#define GICD_BASE_REG 0x100100000000 + +/* The base address of slave socket GIC redistributor registers */ +#define GICR_SLAVE_BASE_REG 0x500100140000 + +/* The base address of slave socket GIC distributor registers */ +#define GICD_SLAVE_BASE_REG 0x500100000000 + +/* Socket 0 first RC */ +#define SOCKET0_FIRST_RC 2 + +/* Socket 0 last RC */ +#define SOCKET0_LAST_RC 7 + +/* Socket 1 first RC */ +#define SOCKET1_FIRST_RC 10 + +/* Socket 1 last RC */ +#define SOCKET1_LAST_RC 15 + +// +// Offset from SMPRO_EFUSE_SHADOW0 +// +#define CFG2P_OFFSET 0x200 + +// +// Slave Socket Present_N in CFG2P_OFFSET +// +#define SLAVE_PRESENT_N 0x2 + +#endif /* __PLATFORM_AC01_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/PlatformInfoHob.h b/Silicon/Ampere/AmpereAltraPkg/Include/PlatformInfoHob.h new file mode 100755 index 000000000000..7b4c0d93895d --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Include/PlatformInfoHob.h @@ -0,0 +1,202 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_INFO_HOB_H_ +#define _PLATFORM_INFO_HOB_H_ + +#include + +#define PLATFORM_INFO_HOB_GUID \ + { \ + 0xa39d5143, 0x964a, 0x4ebe, { 0xb1, 0xa0, 0xcd, 0xd4, 0xa6, 0xf2, 0x18, 0x3a } \ + } + +#define PLATFORM_INFO_HOB_GUID_V2 \ + { \ + 0x7f73e372, 0x7183, 0x4022, { 0xb3, 0x76, 0x78, 0x30, 0x32, 0x6d, 0x79, 0xb4} \ + } + +/* DIMM type */ +enum { + UDIMM, + RDIMM, + SODIMM, + RSODIMM, + LRDIMM, +}; + +/* DIMM status */ +enum { + DIMM_NOT_INSTALLED = 0, + DIMM_INSTALLED_OPERATIONAL, /* installed and operational */ + DIMM_INSTALLED_NONOPERATIONAL, /* installed and non-operational */ + DIMM_INSTALLED_FAILED /* installed and failed */ +}; + +typedef struct { + UINT32 NumRegion; + UINT64 TotalSize; + UINT64 Base[PLATFORM_DRAM_INFO_MAX_REGION]; + UINT64 Size[PLATFORM_DRAM_INFO_MAX_REGION]; + UINT32 CurrentSpeed; +} PlatformDramInfo; + +typedef struct { + UINT32 NumRegion; + UINT64 TotalSize; + UINT64 Base[PLATFORM_DRAM_INFO_MAX_REGION]; + UINT64 Size[PLATFORM_DRAM_INFO_MAX_REGION]; + UINT64 Node[PLATFORM_DRAM_INFO_MAX_REGION]; + UINT64 Socket[PLATFORM_DRAM_INFO_MAX_REGION]; + UINT32 MaxSpeed; + UINT32 McuMask[PLATFORM_CPU_MAX_SOCKET]; + UINT32 NvdRegion[PLATFORM_DRAM_INFO_MAX_REGION]; + UINT32 Reserved[2]; +} PlatformDramInfoV2; + +typedef struct { + CHAR8 PartNumber[32]; + UINT64 DimmSize; + UINT8 DimmNrRank; + UINT8 DimmType; + UINT8 DimmStatus; + UINT16 DimmMfcId; + UINT8 DimmDevType; +} PlatformDimmInfo; + +typedef struct { + CHAR8 PartNumber[32]; + UINT64 DimmSize; + UINT16 DimmMfcId; + UINT16 Reserved; + UINT8 DimmNrRank; + UINT8 DimmType; + UINT8 DimmStatus; + UINT8 DimmDevType; +} PlatformDimmInfoV2; + +/* Raw memory SPD Data structure */ +typedef struct { + /* Memory Type */ + UINT8 Byte2; + /* Attribute, Total Width, Data Width (DDR2&3) */ + UINT8 Byte5To8[9 - 5]; + /* ECC Data Width, Data Width (DDR4) */ + UINT8 Byte11To14[15 - 11]; + /* Manufacturer (DDR2) */ + UINT8 Byte64To71[72 - 64]; + /* Part Number (DDR2) */ + UINT8 Byte73To90[91 - 73]; + /* Serial Number (DDR2) */ + UINT8 Byte95To98[99 - 95]; + /* Manufacturer (DDR3) */ + UINT8 Byte117To118[119 - 117]; + /* Serial Number (DDR3) */ + UINT8 Byte122To125[126 - 122]; + /* Part Number (DDR3) */ + UINT8 Byte128To145[146 - 128]; + /* Manufacturer (DDR4) */ + UINT8 Byte320To321[322 - 320]; + /* Serial Number (DDR4) */ + UINT8 Byte325To328[329 - 325]; + /* Part Number (DDR4) */ + UINT8 Byte329To348[349 - 329]; +} PlatformDimmSpdData; + +typedef struct { + UINT8 Data[512]; +} PlatformDimmSpdDataV2; + +typedef struct { + PlatformDimmInfo Info; + PlatformDimmSpdData SpdData; +} PlatformDimm; + +typedef struct { + PlatformDimmInfoV2 Info; + PlatformDimmSpdDataV2 SpdData; + UINT32 NodeId; +} PlatformDimmV2; + +typedef struct { + UINT32 NumSlot; + PlatformDimm Dimm[PLATFORM_DIMM_INFO_MAX_SLOT]; +} PlatformDimmList; + +typedef struct { + UINT32 BoardDimmSlots; + PlatformDimmV2 Dimm[PLATFORM_DIMM_INFO_MAX_SLOT]; +} PlatformDimmListV2; + +typedef struct { + UINT32 EnableMask[4]; +} PlatformClusterEn; + +typedef struct { + UINT64 PcpClk; + UINT64 PmdClk; + UINT64 SocClk; + UINT64 AhbClk; + UINT64 AxiClk; + UINT64 ApbClk; + UINT64 IobaxiClk; + UINT8 CpuInfo[128]; + UINT8 CpuVer[32]; + UINT8 SmPmProVer[32]; + UINT8 SmPmProBuild[32]; + PlatformDramInfo DramInfo; + PlatformDimmList DimmList; +} PlatformInfoHob; + +typedef struct { + UINT8 MajorNumber; + UINT8 MinorNumber; + UINT64 PcpClk; + UINT64 CpuClk; + UINT64 SocClk; + UINT64 AhbClk; + UINT64 SysClk; + UINT8 CpuInfo[128]; + UINT8 CpuVer[32]; + UINT8 SmPmProVer[32]; + UINT8 SmPmProBuild[32]; + PlatformDramInfoV2 DramInfo; + PlatformDimmListV2 DimmList; + PlatformClusterEn ClusterEn[2]; + UINT32 FailSafeStatus; + UINT32 RcDisableMask[2]; + UINT8 ResetStatus; + UINT16 CoreVoltage[2]; + UINT16 SocVoltage[2]; + UINT16 Dimm1Voltage[2]; + UINT16 Dimm2Voltage[2]; + + /* Chip information */ + UINT32 ScuProductId[2]; + UINT8 MaxNumOfCore[2]; + UINT8 Warranty[2]; + UINT8 SubNumaMode[2]; + UINT8 AvsEnable[2]; + UINT32 AvsVoltageMV[2]; + UINT8 TurboCapability[2]; + UINT32 TurboFrequency[2]; + + UINT8 SkuMaxTurbo[2]; + UINT8 SkuMaxCore[2]; + UINT32 AHBCId[2]; + + /* TPM2 Info */ + UINT8 TpmHob[60]; + + /* 2P link info for RCA0/RCA1 */ + UINT8 Link2PSpeed[2]; + UINT8 Link2PWidth[2]; + +} PlatformInfoHob_V2; + +#endif /* _PLATFORM_INFO_HOB_H_ */ diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.c new file mode 100755 index 000000000000..baabc6c842d5 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemoryInitPeim/MemoryInitPeim.c @@ -0,0 +1,145 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +/* + * The protocols, PPI and GUID defintions for this module + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ); + +VOID +BuildMemoryTypeInformationHob ( + VOID + ) +{ + EFI_MEMORY_TYPE_INFORMATION Info[10]; + + Info[0].Type = EfiACPIReclaimMemory; + Info[0].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiACPIReclaimMemory); + Info[1].Type = EfiACPIMemoryNVS; + Info[1].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiACPIMemoryNVS); + Info[2].Type = EfiReservedMemoryType; + Info[2].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiReservedMemoryType); + Info[3].Type = EfiRuntimeServicesData; + Info[3].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiRuntimeServicesData); + Info[4].Type = EfiRuntimeServicesCode; + Info[4].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiRuntimeServicesCode); + Info[5].Type = EfiBootServicesCode; + Info[5].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiBootServicesCode); + Info[6].Type = EfiBootServicesData; + Info[6].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiBootServicesData); + Info[7].Type = EfiLoaderCode; + Info[7].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiLoaderCode); + Info[8].Type = EfiLoaderData; + Info[8].NumberOfPages = PcdGet32 (PcdMemoryTypeEfiLoaderData); + + /* Terminator for the list */ + Info[9].Type = EfiMaxMemoryType; + Info[9].NumberOfPages = 0; + + BuildGuidDataHob (&gEfiMemoryTypeInformationGuid, &Info, sizeof (Info)); +} + +EFI_STATUS +EFIAPI +InitializeMemory ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + UINTN SystemMemoryBase; + UINTN SystemMemoryTop; + UINTN FdBase; + UINTN FdTop; + UINTN UefiMemoryBase; + UINTN Index; + VOID *Hob; + PlatformInfoHob_V2 *PlatformHob; + CONST EFI_GUID PlatformHobGuid = PLATFORM_INFO_HOB_GUID_V2; + + DEBUG ((DEBUG_INFO, "Memory Init PEIM Loaded\n")); + + Hob = GetFirstGuidHob (&PlatformHobGuid); + if (Hob == NULL) { + return EFI_DEVICE_ERROR; + } + + PlatformHob = (PlatformInfoHob_V2 *) GET_GUID_HOB_DATA (Hob); + + /* Find system memory top of the first node */ + SystemMemoryTop = 0; + for (Index = 0; Index < PlatformHob->DramInfo.NumRegion; Index++) { + if (SystemMemoryTop <= PlatformHob->DramInfo.Base[Index] && + PlatformHob->DramInfo.Node[Index] == 0 && + (PlatformHob->DramInfo.Base[Index] + PlatformHob->DramInfo.Size[Index] - 1) <= 0xFFFFFFFF) { + SystemMemoryTop = PlatformHob->DramInfo.Base[Index] + PlatformHob->DramInfo.Size[Index]; + } + } + + DEBUG ((DEBUG_INFO, "PEIM memory configuration.\n")); + + SystemMemoryBase = (UINTN) FixedPcdGet64 (PcdSystemMemoryBase); + FdBase = (UINTN) PcdGet64 (PcdFdBaseAddress); + FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize); + + // In case the firmware has been shadowed in the System Memory + if ((FdBase >= SystemMemoryBase) && (FdTop <= SystemMemoryTop)) { + // + //Check if there is enough space between the top of the system memory and the top of the + // firmware to place the UEFI memory (for PEI & DXE phases) + // + if (SystemMemoryTop - FdTop >= FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)) { + UefiMemoryBase = SystemMemoryTop - FixedPcdGet32 (PcdSystemMemoryUefiRegionSize); + } else { + // Check there is enough space for the UEFI memory + ASSERT (SystemMemoryBase + FixedPcdGet32 (PcdSystemMemoryUefiRegionSize) <= FdBase); + + UefiMemoryBase = FdBase - FixedPcdGet32 (PcdSystemMemoryUefiRegionSize); + } + } else { + // Check the Firmware does not overlapped with the system memory + ASSERT ((FdBase < SystemMemoryBase) || (FdBase >= SystemMemoryTop)); + ASSERT ((FdTop <= SystemMemoryBase) || (FdTop > SystemMemoryTop)); + + UefiMemoryBase = SystemMemoryTop - FixedPcdGet32 (PcdSystemMemoryUefiRegionSize); + } + + Status = PeiServicesInstallPeiMemory (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Failed to install Pei Memory\n")); + } else { + DEBUG ((DEBUG_INFO, "Info: Installed Pei Memory\n")); + } + ASSERT_EFI_ERROR (Status); + + // Initialize MMU and Memory HOBs (Resource Descriptor HOBs) + Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Failed to initialize MMU and Memory HOBS\n")); + } + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.c new file mode 100644 index 000000000000..99d729b6cc46 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationDxe/MmCommunication.c @@ -0,0 +1,424 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC + Copyright (c) 2016-2018, ARM Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "MmCommunicate.h" + +#define MM_EARLY_MEM_ALLOCATE 1 + +// +// Address, Length of the pre-allocated buffer for communication with the secure +// world. +// +STATIC ARM_MEMORY_REGION_DESCRIPTOR mNsCommBuffMemRegion; + +// Notification event when virtual address map is set. +STATIC EFI_EVENT mSetVirtualAddressMapEvent; + +// +// Handle to install the MM Communication Protocol +// +STATIC EFI_HANDLE mMmCommunicateHandle; + +/** + Communicates with a registered handler. + + This function provides an interface to send and receive messages to the + Standalone MM environment on behalf of UEFI services. This function is part + of the MM Communication Protocol that may be called in physical mode prior to + SetVirtualAddressMap() and in virtual mode after SetVirtualAddressMap(). + + @param[in] This The EFI_MM_COMMUNICATION_PROTOCOL + instance. + @param[in, out] CommBuffer A pointer to the buffer to convey + into MMRAM. + @param[in, out] CommSize The size of the data buffer being + passed in. This is optional. + + @retval EFI_SUCCESS The message was successfully posted. + @retval EFI_INVALID_PARAMETER The CommBuffer was NULL. + @retval EFI_BAD_BUFFER_SIZE The buffer size is incorrect for the MM + implementation. If this error is + returned, the MessageLength field in + the CommBuffer header or the integer + pointed by CommSize are updated to reflect + the maximum payload size the + implementation can accommodate. + @retval EFI_ACCESS_DENIED The CommunicateBuffer parameter + or CommSize parameter, if not omitted, + are in address range that cannot be + accessed by the MM environment +**/ +STATIC +EFI_STATUS +EFIAPI +MmCommunicationCommunicate ( + IN CONST EFI_MM_COMMUNICATION_PROTOCOL *This, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommSize OPTIONAL + ) +{ + EFI_MM_COMMUNICATE_HEADER *CommunicateHeader; + ARM_SMC_ARGS CommunicateSmcArgs; + EFI_STATUS Status; + UINTN BufferSize; + + Status = EFI_ACCESS_DENIED; + BufferSize = 0; + + ZeroMem (&CommunicateSmcArgs, sizeof (ARM_SMC_ARGS)); + + // + // Check parameters + // + if (CommBuffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + CommunicateHeader = CommBuffer; + // CommBuffer is a mandatory parameter. Hence, Rely on + // MessageLength + Header to ascertain the + // total size of the communication payload rather than + // rely on optional CommSize parameter + BufferSize = CommunicateHeader->MessageLength + + sizeof (CommunicateHeader->HeaderGuid) + + sizeof (CommunicateHeader->MessageLength); + + // If the length of the CommBuffer is 0 then return the expected length. + if (CommSize != NULL) { + // This case can be used by the consumer of this driver to find out the + // max size that can be used for allocating CommBuffer. + if ((*CommSize == 0) || + (*CommSize > mNsCommBuffMemRegion.Length)) { + *CommSize = mNsCommBuffMemRegion.Length; + return EFI_BAD_BUFFER_SIZE; + } + // + // CommSize must match MessageLength + sizeof (EFI_MM_COMMUNICATE_HEADER); + // + if (*CommSize != BufferSize) { + return EFI_INVALID_PARAMETER; + } + } + + // + // If the buffer size is 0 or greater than what can be tolerated by the MM + // environment then return the expected size. + // + if ((BufferSize == 0) || + (BufferSize > mNsCommBuffMemRegion.Length)) { + CommunicateHeader->MessageLength = mNsCommBuffMemRegion.Length - + sizeof (CommunicateHeader->HeaderGuid) - + sizeof (CommunicateHeader->MessageLength); + return EFI_BAD_BUFFER_SIZE; + } + + // SMC Function ID + CommunicateSmcArgs.Arg0 = ARM_SMC_ID_MM_COMMUNICATE_AARCH64; + + // Cookie + CommunicateSmcArgs.Arg1 = 0; + + // Copy Communication Payload + CopyMem ((VOID *)mNsCommBuffMemRegion.VirtualBase, CommBuffer, BufferSize); + + // comm_buffer_address (64-bit physical address) + CommunicateSmcArgs.Arg2 = (UINTN)mNsCommBuffMemRegion.PhysicalBase; + + // comm_size_address (not used, indicated by setting to zero) + CommunicateSmcArgs.Arg3 = 0; + + // Call the Standalone MM environment. + ArmCallSmc (&CommunicateSmcArgs); + + switch (CommunicateSmcArgs.Arg0) { + case ARM_SMC_MM_RET_SUCCESS: + ZeroMem (CommBuffer, BufferSize); + // On successful return, the size of data being returned is inferred from + // MessageLength + Header. + CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase; + BufferSize = CommunicateHeader->MessageLength + + sizeof (CommunicateHeader->HeaderGuid) + + sizeof (CommunicateHeader->MessageLength); + + CopyMem ( + CommBuffer, + (VOID *)mNsCommBuffMemRegion.VirtualBase, + BufferSize + ); + Status = EFI_SUCCESS; + break; + + case ARM_SMC_MM_RET_INVALID_PARAMS: + Status = EFI_INVALID_PARAMETER; + break; + + case ARM_SMC_MM_RET_DENIED: + Status = EFI_ACCESS_DENIED; + break; + + case ARM_SMC_MM_RET_NO_MEMORY: + // Unexpected error since the CommSize was checked for zero length + // prior to issuing the SMC + Status = EFI_OUT_OF_RESOURCES; + ASSERT (0); + break; + + default: + Status = EFI_ACCESS_DENIED; + ASSERT (0); + } + + return Status; +} + +// +// MM Communication Protocol instance +// +EFI_MM_COMMUNICATION_PROTOCOL mMmCommunication = { + MmCommunicationCommunicate +}; + +/** + Notification callback on SetVirtualAddressMap event. + + This function notifies the MM communication protocol interface on + SetVirtualAddressMap event and converts pointers used in this driver + from physical to virtual address. + + @param Event SetVirtualAddressMap event. + @param Context A context when the SetVirtualAddressMap triggered. + + @retval EFI_SUCCESS The function executed successfully. + @retval Other Some error occurred when executing this function. + +**/ +STATIC +VOID +EFIAPI +NotifySetVirtualAddressMap ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + + Status = gRT->ConvertPointer ( + EFI_OPTIONAL_PTR, + (VOID **)&mNsCommBuffMemRegion.VirtualBase + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Unable to convert MM runtime pointer. Status:0x%r\n", + __FUNCTION__, Status)); + } + +} + +STATIC +EFI_STATUS +GetMmCompatibility () +{ + EFI_STATUS Status; + UINT32 MmVersion; + ARM_SMC_ARGS MmVersionArgs; + + // MM_VERSION uses SMC32 calling conventions + MmVersionArgs.Arg0 = ARM_SMC_ID_MM_VERSION_AARCH32; + + ArmCallSmc (&MmVersionArgs); + + MmVersion = MmVersionArgs.Arg0; + + if ((MM_MAJOR_VER (MmVersion) == MM_CALLER_MAJOR_VER) && + (MM_MINOR_VER (MmVersion) >= MM_CALLER_MINOR_VER)) { + DEBUG ((DEBUG_INFO, "MM Version: Major=0x%x, Minor=0x%x\n", + MM_MAJOR_VER (MmVersion), MM_MINOR_VER (MmVersion))); + Status = EFI_SUCCESS; + } else { + DEBUG ((DEBUG_ERROR, "Incompatible MM Versions.\n Current Version: Major=0x%x, Minor=0x%x.\n Expected: Major=0x%x, Minor>=0x%x.\n", + MM_MAJOR_VER (MmVersion), MM_MINOR_VER (MmVersion), MM_CALLER_MAJOR_VER, MM_CALLER_MINOR_VER)); + Status = EFI_UNSUPPORTED; + } + + return Status; +} + +STATIC EFI_GUID* CONST mGuidedEventGuid[] = { + &gEfiEndOfDxeEventGroupGuid, + &gEfiEventExitBootServicesGuid, + &gEfiEventReadyToBootGuid, +}; + +STATIC EFI_EVENT mGuidedEvent[ARRAY_SIZE (mGuidedEventGuid)]; + +/** + Event notification that is fired when GUIDed Event Group is signaled. + + @param Event The Event that is being processed, not used. + @param Context Event Context, not used. + +**/ +STATIC +VOID +EFIAPI +MmGuidedEventNotify ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_MM_COMMUNICATE_HEADER Header; + UINTN Size; + + // + // Use Guid to initialize EFI_SMM_COMMUNICATE_HEADER structure + // + CopyGuid (&Header.HeaderGuid, Context); + Header.MessageLength = 1; + Header.Data[0] = 0; + + Size = sizeof (Header); + MmCommunicationCommunicate (&mMmCommunication, &Header, &Size); +} + +/** + The Entry Point for MM Communication + + This function installs the MM communication protocol interface and finds out + what type of buffer management will be required prior to invoking the + communication SMC. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The entry point is executed successfully. + @retval Other Some error occurred when executing this entry point. + +**/ +EFI_STATUS +EFIAPI +MmCommunicationInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINTN Index; + + // Check if we can make the MM call + Status = GetMmCompatibility (); + if (EFI_ERROR (Status)) { + goto ReturnErrorStatus; + } + + mNsCommBuffMemRegion.PhysicalBase = PcdGet64 (PcdMmBufferBase); + // During boot , Virtual and Physical are same + mNsCommBuffMemRegion.VirtualBase = mNsCommBuffMemRegion.PhysicalBase; + mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize); + + ASSERT (mNsCommBuffMemRegion.PhysicalBase != 0); + + ASSERT (mNsCommBuffMemRegion.Length != 0); + +#if !defined(MM_EARLY_MEM_ALLOCATE) + Status = gDS->AddMemorySpace ( + EfiGcdMemoryTypeReserved, + mNsCommBuffMemRegion.PhysicalBase, + mNsCommBuffMemRegion.Length, + EFI_MEMORY_WB | + EFI_MEMORY_XP | + EFI_MEMORY_RUNTIME + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to add MM-NS Buffer Memory Space\n", + __FUNCTION__)); + goto ReturnErrorStatus; + } + + Status = gDS->SetMemorySpaceAttributes ( + mNsCommBuffMemRegion.PhysicalBase, + mNsCommBuffMemRegion.Length, + EFI_MEMORY_WB | EFI_MEMORY_XP | EFI_MEMORY_RUNTIME + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to set MM-NS Buffer Memory attributes\n", + __FUNCTION__)); + goto CleanAddedMemorySpace; + } +#endif + + // Install the communication protocol + Status = gBS->InstallProtocolInterface ( + &mMmCommunicateHandle, + &gEfiMmCommunicationProtocolGuid, + EFI_NATIVE_INTERFACE, + &mMmCommunication + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: Failed to install MM communication protocol\n", + __FUNCTION__)); + goto CleanAddedMemorySpace; + } + + // Register notification callback when virtual address is associated + // with the physical address. + // Create a Set Virtual Address Map event. + Status = gBS->CreateEvent ( + EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE, + TPL_NOTIFY, + NotifySetVirtualAddressMap, + NULL, + &mSetVirtualAddressMapEvent + ); + ASSERT_EFI_ERROR (Status); + + for (Index = 0; Index < ARRAY_SIZE (mGuidedEventGuid); Index++) { + Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, TPL_CALLBACK, + MmGuidedEventNotify, mGuidedEventGuid[Index], + mGuidedEventGuid[Index], &mGuidedEvent[Index]); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + while (Index-- > 0) { + gBS->CloseEvent (mGuidedEvent[Index]); + } + goto UninstallProtocol; + } + } + return EFI_SUCCESS; + +UninstallProtocol: + gBS->UninstallProtocolInterface ( + mMmCommunicateHandle, + &gEfiMmCommunicationProtocolGuid, + &mMmCommunication + ); + +CleanAddedMemorySpace: +#if !defined(MM_EARLY_MEM_ALLOCATE) + gDS->RemoveMemorySpace ( + mNsCommBuffMemRegion.PhysicalBase, + mNsCommBuffMemRegion.Length + ); +#endif + +ReturnErrorStatus: + return EFI_INVALID_PARAMETER; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.c new file mode 100755 index 000000000000..c39770ecba24 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MmCommunicationPei/MmCommunicationPei.c @@ -0,0 +1,36 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +EFIAPI +MmCommunicationPeiEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_PHYSICAL_ADDRESS MmBufferBase = PcdGet64 (PcdMmBufferBase); + UINT64 MmBufferSize = PcdGet64 (PcdMmBufferSize); + + BuildMemoryAllocationHob (MmBufferBase, MmBufferSize, EfiRuntimeServicesData); + + return EFI_SUCCESS; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c new file mode 100644 index 000000000000..19b904818b4d --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c @@ -0,0 +1,641 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MONOLITIC_NUM_OF_REGION 1 +#define HEMISPHERE_NUM_OF_REGION 2 +#define QUADRANT_NUM_OF_REGION 4 +#define SUBNUMA_CPM_REGION_SIZE 4 +#define NUM_OF_CPM_PER_MESH_ROW 8 + +STATIC PlatformInfoHob_V2* +GetPlatformHob (VOID) +{ + VOID *Hob; + CONST EFI_GUID PlatformHobGuid = PLATFORM_INFO_HOB_GUID_V2; + + Hob = GetFirstGuidHob (&PlatformHobGuid); + if (Hob == NULL) { + return NULL; + } + + return (PlatformInfoHob_V2 *) GET_GUID_HOB_DATA (Hob); +} + +/** + Get the SubNUMA mode. + + @return UINT8 The SubNUMA mode. + +**/ +UINT8 +EFIAPI +CPUGetSubNumaMode (VOID) +{ + PlatformInfoHob_V2 *PlatformHob; + + PlatformHob = GetPlatformHob (); + if (PlatformHob == NULL) { + return SUBNUMA_MODE_MONOLITHIC; + } + + return PlatformHob->SubNumaMode[0]; +} + +/** + Get the number of SubNUMA region. + + @return UINT8 The number of SubNUMA region. + +**/ +UINT8 +EFIAPI +CPUGetNumOfSubNuma (VOID) +{ + UINT8 SubNumaMode = CPUGetSubNumaMode(); + + switch (SubNumaMode) { + case SUBNUMA_MODE_MONOLITHIC: + return MONOLITIC_NUM_OF_REGION; + case SUBNUMA_MODE_HEMISPHERE: + return HEMISPHERE_NUM_OF_REGION; + case SUBNUMA_MODE_QUADRANT: + return QUADRANT_NUM_OF_REGION; + } + + return QUADRANT_NUM_OF_REGION; +} + +/** + Get the SubNUMA node of a CPM. + + @param SocketId Socket index. + @param Cpm CPM index. + @return UINT8 The SubNUMA node of a CPM. + +**/ +UINT8 +EFIAPI +CPUGetSubNumNode ( + UINT8 SocketId, + UINT32 Cpm + ) +{ + UINT8 MaxNumOfCPM = GetMaximumNumberCPMs(); + UINT8 SubNumaMode = CPUGetSubNumaMode(); + INTN Ret = 0; + UINT8 AsymMesh = 0; + UINT8 AsymMeshRow = 0; + + switch (SubNumaMode) { + case SUBNUMA_MODE_MONOLITHIC: + if (SocketId == 0) { + Ret = 0; + } else { + Ret = 1; + } + break; + + case SUBNUMA_MODE_HEMISPHERE: + if (((Cpm % NUM_OF_CPM_PER_MESH_ROW) / SUBNUMA_CPM_REGION_SIZE) != 0) { + Ret = 1; + } else { + Ret = 0; + } + if (SocketId == 1) { + Ret += HEMISPHERE_NUM_OF_REGION; + } + break; + + case SUBNUMA_MODE_QUADRANT: + // For asymmetric mesh, the CPM at the middle row is distributed + // equally to each node. As each mesh row has 8 CPMs, + // First pair of CPMs: Node 0 + // Second pair of CPMs: Node 1 + // Third pair of CPMs: Node 3 + // Forth paif of CPMs: Node 2 + AsymMesh = (MaxNumOfCPM / NUM_OF_CPM_PER_MESH_ROW) % 2; + if (AsymMesh != 0) { + AsymMeshRow = (MaxNumOfCPM / NUM_OF_CPM_PER_MESH_ROW) / 2; + } + if ((AsymMesh != 0) && ((Cpm / NUM_OF_CPM_PER_MESH_ROW) == AsymMeshRow)) { + switch ((Cpm % NUM_OF_CPM_PER_MESH_ROW) / 2) { + case 0: + Ret = 0; + break; + case 1: + Ret = 1; + break; + case 2: + Ret = 3; + break; + case 3: + Ret = 2; + break; + } + } else { + if (Cpm < (MaxNumOfCPM / 2)) { + if (((Cpm % NUM_OF_CPM_PER_MESH_ROW) / SUBNUMA_CPM_REGION_SIZE) != 0) { + Ret = 2; + } else { + Ret = 0; + } + } else { + if (((Cpm % NUM_OF_CPM_PER_MESH_ROW) / SUBNUMA_CPM_REGION_SIZE) != 0) { + Ret = 3; + } else { + Ret = 1; + } + } + } + + if (SocketId == 1) { + Ret += QUADRANT_NUM_OF_REGION; + } + break; + } + + return Ret; +} + +/** + Get the value of CLIDR register. + + @return UINT64 The value of CLIDR register. + +**/ +UINT64 +EFIAPI +AArch64ReadCLIDRReg (VOID) +{ + UINT64 Value; + + asm volatile("mrs %x0, clidr_el1 " : "=r" (Value)); + + return Value; +} + +/** + Get the value of CCSID register. + + @param Level Cache level. + @return UINT64 The value of CCSID register. + +**/ +UINT64 +EFIAPI +AArch64ReadCCSIDRReg ( + UINT64 Level + ) +{ + UINT64 Value; + + asm volatile("msr csselr_el1, %x0 " : : "rZ" (Level)); + asm volatile("mrs %x0, ccsidr_el1 " : "=r" (Value)); + + return Value; +} + +/** + Get the associativity of cache. + + @param Level Cache level. + @return UINT32 Associativity of cache. + +**/ +UINT32 +EFIAPI +CpuGetAssociativity ( + UINTN Level + ) +{ + UINT64 CacheCCSIDR; + UINT64 CacheCLIDR = AArch64ReadCLIDRReg (); + UINT32 Value = 0x2; /* Unknown Set-Associativity */ + + if (!CLIDR_CTYPE (CacheCLIDR, Level)) { + return Value; + } + + CacheCCSIDR = AArch64ReadCCSIDRReg (Level); + switch (CCSIDR_ASSOCIATIVITY (CacheCCSIDR)) { + case 0: + /* Direct mapped */ + Value = 0x3; + break; + case 1: + /* 2-way Set-Associativity */ + Value = 0x4; + break; + case 3: + /* 4-way Set-Associativity */ + Value = 0x5; + break; + case 7: + /* 8-way Set-Associativity */ + Value = 0x7; + break; + case 15: + /* 16-way Set-Associativity */ + Value = 0x8; + break; + case 11: + /* 12-way Set-Associativity */ + Value = 0x9; + break; + case 23: + /* 24-way Set-Associativity */ + Value = 0xA; + break; + case 31: + /* 32-way Set-Associativity */ + Value = 0xB; + break; + case 47: + /* 48-way Set-Associativity */ + Value = 0xC; + break; + case 63: + /* 64-way Set-Associativity */ + Value = 0xD; + break; + case 19: + /* 20-way Set-Associativity */ + Value = 0xE; + break; + } + + return Value; +} + +/** + Get the cache size. + + @param Level Cache level. + @return UINT32 Cache size. + +**/ +UINT32 +EFIAPI +CpuGetCacheSize ( + UINTN Level + ) +{ + UINT32 CacheLineSize; + UINT32 Count; + UINT64 CacheCCSIDR; + UINT64 CacheCLIDR = AArch64ReadCLIDRReg (); + + if (!CLIDR_CTYPE (CacheCLIDR, Level)) { + return 0; + } + + CacheCCSIDR = AArch64ReadCCSIDRReg (Level); + CacheLineSize = 1; + Count = CCSIDR_LINE_SIZE (CacheCCSIDR) + 4; + while (Count-- > 0) { + CacheLineSize *= 2; + } + + return ((CCSIDR_NUMSETS (CacheCCSIDR) + 1) * + (CCSIDR_ASSOCIATIVITY (CacheCCSIDR) + 1) * + CacheLineSize); +} + +/** + Get the number of supported socket. + + @return UINT32 Number of supported socket. + +**/ +UINT32 +EFIAPI +GetNumberSupportedSockets (VOID) +{ + PlatformInfoHob_V2 *PlatformHob; + + PlatformHob = GetPlatformHob (); + if (PlatformHob == NULL) { + return 0; + } + + return (sizeof (PlatformHob->ClusterEn) / sizeof (PlatformClusterEn)); +} + +/** + Get the number of active socket. + + @return UINT32 Number of active socket. + +**/ +UINT32 +EFIAPI +GetNumberActiveSockets (VOID) +{ + UINTN NumberActiveSockets, Count, Index, Index1; + PlatformClusterEn *Socket; + PlatformInfoHob_V2 *PlatformHob; + + PlatformHob = GetPlatformHob (); + if (PlatformHob == NULL) { + return 0; + } + + NumberActiveSockets = 0; + + for (Index = 0; Index < GetNumberSupportedSockets (); Index++) { + Socket = &PlatformHob->ClusterEn[Index]; + Count = sizeof (Socket->EnableMask) / sizeof (Socket->EnableMask[0]); + for (Index1 = 0; Index1 < Count; Index1++) { + if (Socket->EnableMask[Index1]) { + NumberActiveSockets++; + break; + } + } + } + + return NumberActiveSockets; +} + +/** + Get the number of active CPM per socket. + + @param SocketId Socket index. + @return UINT32 Number of CPM. + +**/ +UINT32 +EFIAPI +GetNumberActiveCPMsPerSocket ( + UINT32 SocketId + ) +{ + UINTN NumberCPMs, Count, Index; + UINT32 Val32; + PlatformClusterEn *Socket; + PlatformInfoHob_V2 *PlatformHob; + + PlatformHob = GetPlatformHob (); + if (PlatformHob == NULL) { + return 0; + } + + if (SocketId >= GetNumberSupportedSockets ()) { + return 0; + } + + NumberCPMs = 0; + Socket = &PlatformHob->ClusterEn[SocketId]; + Count = sizeof (Socket->EnableMask) / sizeof (Socket->EnableMask[0]); + for (Index = 0; Index < Count; Index++) { + Val32 = Socket->EnableMask[Index]; + while (Val32) { + if (Val32 & 0x1) { + NumberCPMs++; + } + Val32 >>= 1; + } + } + + return NumberCPMs; +} + +/** + Get the configured number of CPM per socket. This number + should be the same for all sockets. + + @param SocketId Socket index. + @return UINT32 Configured number of CPM. + +**/ +UINT32 +EFIAPI +GetConfiguredNumberCPMs ( + UINTN SocketId + ) +{ + EFI_STATUS Status; + UINT32 Value; + UINT32 Param, ParamStart, ParamEnd; + INTN Count; + + Count = 0; + ParamStart = NV_SI_S0_PCP_ACTIVECPM_0_31 + SocketId * NV_PARAM_ENTRYSIZE * (PLATFORM_CPU_MAX_CPM / 32); + ParamEnd = ParamStart + NV_PARAM_ENTRYSIZE * (PLATFORM_CPU_MAX_CPM / 32); + for (Param = ParamStart; Param < ParamEnd; Param += NV_PARAM_ENTRYSIZE) { + Status = NVParamGet ( + Param, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + &Value + ); + if (EFI_ERROR (Status)) { + break; + } + while (Value) { + if (Value & 1) { + Count++; + } + Value >>= 1; + } + } + + return Count; +} + +/** + Set the configured number of CPM per socket. + + @param SocketId Socket index. + @param Number Number of CPM to be configured. + @return EFI_SUCCESS Operation succeeded. + @return Others An error has occurred. + +**/ +EFI_STATUS +EFIAPI +SetConfiguredNumberCPMs ( + UINTN Socket, + UINTN Number + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT32 Value; + UINT32 Param, ParamStart, ParamEnd; + BOOLEAN IsClear = FALSE; + + if (Number == 0) { + IsClear = TRUE; + } + + ParamStart = NV_SI_S0_PCP_ACTIVECPM_0_31 + Socket * NV_PARAM_ENTRYSIZE * (PLATFORM_CPU_MAX_CPM / 32); + ParamEnd = ParamStart + NV_PARAM_ENTRYSIZE * (PLATFORM_CPU_MAX_CPM / 32); + for (Param = ParamStart; Param < ParamEnd; Param += NV_PARAM_ENTRYSIZE) { + if (Number >= 32) { + Value = 0xffffffff; + Number -= 32; + } else { + Value = 0; + while (Number > 0) { + Value |= (1 << (--Number)); + } + } + if (IsClear) { + /* Clear this param */ + Status = NVParamClr ( + Param, + NV_PERM_BIOS | NV_PERM_MANU + ); + } else { + Status = NVParamSet ( + Param, + NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC, + NV_PERM_BIOS | NV_PERM_MANU, + Value + ); + } + } + + return Status; +} + +/** + Get the maximum number of core per socket. + + @return UINT32 Maximum number of core. + +**/ +UINT32 +EFIAPI +GetMaximumNumberOfCores (VOID) +{ + + PlatformInfoHob_V2 *PlatformHob; + + PlatformHob = GetPlatformHob (); + if (PlatformHob == NULL) { + return 0; + } + + return PlatformHob->MaxNumOfCore[0]; +} + +/** + Get the maximum number of CPM per socket. This number + should be the same for all sockets. + + @return UINT32 Maximum number of CPM. + +**/ +UINT32 +EFIAPI +GetMaximumNumberCPMs (VOID) +{ + return GetMaximumNumberOfCores() / PLATFORM_CPU_NUM_CORES_PER_CPM; +} + +/** + Get the number of active cores of a sockets. + + @param SocketId Socket Index. + @return UINT32 Number of active core. + +**/ +UINT32 +EFIAPI +GetNumberActiveCoresPerSocket ( + UINT32 SocketId + ) +{ + return GetNumberActiveCPMsPerSocket (SocketId) * PLATFORM_CPU_NUM_CORES_PER_CPM; +} + +/** + Get the number of active cores of all sockets. + + @return UINT32 Number of active core. + +**/ +UINT32 +EFIAPI +GetNumberActiveCores (VOID) +{ + UINTN NumberActiveCores; + UINTN Index; + + NumberActiveCores = 0; + + for (Index = 0; Index < GetNumberSupportedSockets (); Index++) { + NumberActiveCores += GetNumberActiveCoresPerSocket (Index); + } + + return NumberActiveCores; +} + +/** + Check if the logical CPU is enabled or not. + + @param CpuId The logical Cpu ID. Started from 0. + @return BOOLEAN TRUE if the Cpu enabled + FALSE if the Cpu disabled/ + +**/ +BOOLEAN +EFIAPI +IsCpuEnabled ( + UINTN CpuId + ) +{ + PlatformClusterEn *Socket; + PlatformInfoHob_V2 *PlatformHob; + UINT32 SocketId = CpuId / (PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM); + UINT32 ClusterId = (CpuId / PLATFORM_CPU_NUM_CORES_PER_CPM) % PLATFORM_CPU_MAX_CPM; + + PlatformHob = GetPlatformHob (); + if (PlatformHob == NULL) { + return FALSE; + } + + if (SocketId >= GetNumberSupportedSockets ()) { + return FALSE; + } + + Socket = &PlatformHob->ClusterEn[SocketId]; + if (Socket->EnableMask[ClusterId / 32] & (1 << (ClusterId % 32))) { + return TRUE; + } + + return FALSE; +} + +/** + Check if the slave socket is present + + @return BOOLEAN TRUE if the Slave Cpu present + FALSE if the Slave Cpu present + +**/ +BOOLEAN +EFIAPI +PlatSlaveSocketPresent (VOID) +{ + UINT32 Value; + + Value = MmioRead32 (SMPRO_EFUSE_SHADOW0 + CFG2P_OFFSET); + return (Value & SLAVE_PRESENT_N)? FALSE : TRUE; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c new file mode 100755 index 000000000000..a62fd8f1af72 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -0,0 +1,198 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +ARM_CORE_INFO mArmPlatformMpCoreInfoTable[PLATFORM_CPU_MAX_NUM_CORES]; + +STATIC +UINTN +ArmPlatformCpuIsEnabled(PlatformInfoHob_V2 *Hob, UINT32 Cpu) +{ + UINT32 ClusterID = Cpu / PLATFORM_CPU_NUM_CORES_PER_CPM; + UINT32 SocketID; + + SocketID = Cpu / (PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM); + if (SocketID == 1) { + ClusterID -= PLATFORM_CPU_MAX_CPM; + } + + if (Hob->ClusterEn[SocketID].EnableMask[ClusterID / 32] & (1 << (ClusterID % 32))) { + return 1; + } + + return 0; +} + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + RETURN_STATUS Status; + UINT64 BaudRate; + UINT32 ReceiveFifoDepth; + EFI_PARITY_TYPE Parity; + UINT8 DataBits; + EFI_STOP_BITS_TYPE StopBits; + + Status = RETURN_SUCCESS; + + if (FixedPcdGet64 (PcdSerialRegisterBase)) { + /* Debug port should use the same parameters with console */ + BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate); + ReceiveFifoDepth = FixedPcdGet32 (PcdUartDefaultReceiveFifoDepth); + Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity); + DataBits = FixedPcdGet8 (PcdUartDefaultDataBits); + StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits); + + /* Initialize uart debug port */ + Status = PL011UartInitializePort ( + (UINTN)FixedPcdGet64 (PcdSerialRegisterBase), + FixedPcdGet32 (PL011UartClkInHz), + &BaudRate, + &ReceiveFifoDepth, + &Parity, + &DataBits, + &StopBits + ); + } + + return Status; +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + CONST EFI_GUID PlatformHobGuid = PLATFORM_INFO_HOB_GUID_V2; + UINTN mArmPlatformCoreCount; + PlatformInfoHob_V2 *PlatformHob; + UINTN ClusterId; + UINTN SocketId; + UINTN Index; + VOID *Hob; + + ASSERT (CoreCount != NULL); + ASSERT (ArmCoreTable != NULL); + ASSERT (*ArmCoreTable != NULL); + + Hob = GetNextGuidHob (&PlatformHobGuid, + (CONST VOID *) FixedPcdGet64 (PcdSystemMemoryBase)); + if (!Hob) { + return EFI_UNSUPPORTED; + } + + PlatformHob = (PlatformInfoHob_V2 *) GET_GUID_HOB_DATA (Hob); + + mArmPlatformCoreCount = 0; + for (Index = 0; Index < PLATFORM_CPU_MAX_NUM_CORES; Index++) { + if (ArmPlatformCpuIsEnabled(PlatformHob, Index) == 0) { + continue; + } + SocketId = Index / (PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM); + ClusterId = Index / PLATFORM_CPU_NUM_CORES_PER_CPM; + if (SocketId) { + ClusterId -= PLATFORM_CPU_MAX_CPM; + } + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].ClusterId = SocketId; + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].CoreId = + (ClusterId << 8) | (Index % PLATFORM_CPU_NUM_CORES_PER_CPM); + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxClearAddress = 0; + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxClearValue = 0; + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxGetAddress = 0; + mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxSetAddress = 0; + mArmPlatformCoreCount++; + } + + *CoreCount = mArmPlatformCoreCount; + + *ArmCoreTable = mArmPlatformMpCoreInfoTable; + ASSERT(*ArmCoreTable); + + return EFI_SUCCESS; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + }, +}; + +/** + Return the Platform specific PPIs + + This function exposes the Platform Specific PPIs. They can be used by any PrePi modules or passed + to the PeiCore by PrePeiCore. + + @param[out] PpiListSize Size in Bytes of the Platform PPI List + @param[out] PpiList Platform PPI List + +**/ +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + ASSERT (PpiListSize != NULL); + ASSERT (PpiList != NULL); + ASSERT (*PpiList != NULL); + + if (ArmIsMpCore ()) { + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; + } else { + *PpiListSize = 0; + *PpiList = NULL; + } +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLibMemory.c b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLibMemory.c new file mode 100755 index 000000000000..50417ccb1128 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLibMemory.c @@ -0,0 +1,388 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +/* Number of Virtual Memory Map Descriptors */ +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 49 + +/* DDR attributes */ +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- + Virtual Memory mapping. This array must be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + OUT ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + UINT32 NumRegion; + UINTN Count; + VOID *Hob; + PlatformInfoHob_V2 *PlatformHob; + CONST EFI_GUID PlatformHobGuid = PLATFORM_INFO_HOB_GUID_V2; + + Hob = GetFirstGuidHob (&PlatformHobGuid); + if (!Hob) { + return; + } + + PlatformHob = (PlatformInfoHob_V2 *) GET_GUID_HOB_DATA (Hob); + + ASSERT(VirtualMemoryMap != NULL); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + /* For Address space 0x1000_0000_0000 to 0x1001_00FF_FFFF + * - Device memory + */ + VirtualMemoryTable[Index].PhysicalBase = 0x100000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x100000000000ULL; + VirtualMemoryTable[Index].Length = 0x102000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* For Address space 0x5000_0000_0000 to 0x5001_00FF_FFFF + * - Device memory + */ + if (PlatformHob->ClusterEn[1].EnableMask[0] || + PlatformHob->ClusterEn[1].EnableMask[1]) { + VirtualMemoryTable[++Index].PhysicalBase = 0x500000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x500000000000ULL; + VirtualMemoryTable[Index].Length = 0x101000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + } + + /* + * - PCIe RCA0 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x300000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x300000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket0 RCA0 32-bit Device memory + * - 1P/PCIe consolidated to RCB2 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x20000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x20000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCA1 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x340000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x340000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket0 RCA1 32-bit Device memory + * - 1P/PCIe consolidated to RCB2 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x28000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x28000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCA2 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x380000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x380000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket0 RCA2 32-bit Device memory + * - 1P/PCIe consolidated to RCB3 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x30000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x30000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCA3 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x3C0000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x3C0000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket0 RCA3 32-bit Device memory + * - 1P/PCIe consolidated to RCB3 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x38000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x38000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCB0 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x200000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x200000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket0 RCB0 32-bit Device memory + * - 1P/PCIe consolidated to RCB0 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x00000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x00000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCB1 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x240000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x240000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket0 RCB1 32-bit Device memory + * - 1P/PCIe consolidated to RCB0 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x08000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x08000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCB2 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x280000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x280000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket0 RCB2 32-bit Device memory + * - 1P/PCIe consolidated to RCB1 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x10000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x10000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCB3 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x2C0000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x2C0000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket0 RCB3 32-bit Device memory + * - 1P/PCIe consolidated to RCB1 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x18000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x18000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + if (GetNumberActiveSockets () == 2) { + // Slave socket exist + /* + * - PCIe RCA0 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x700000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x700000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCA1 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x740000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x740000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCA2 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x780000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x780000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCA3 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x7C0000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x7C0000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCB0 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x600000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x600000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCB1 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x640000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x640000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCB2 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x680000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x680000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - PCIe RCB3 Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x6C0000000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x6C0000000000ULL; + VirtualMemoryTable[Index].Length = 0x40000000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + } + + /* + * - 2P/PCIe Socket1 RCA0 32-bit Device memory + * - 1P/PCIe consolidated to RCA2 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x60000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x60000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket1 RCA1 32-bit Device memory + * - 1P/PCIe consolidated to RCA2 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x68000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x68000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket1 RCA2 32-bit Device memory + * - 1P/PCIe consolidated to RCA3 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x70000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x70000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket1 RCA3 32-bit Device memory + * - 1P/PCIe consolidated to RCA3 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x78000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x78000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket1 RCB0 32-bit Device memory + * - 1P/PCIe consolidated to RCA0 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x40000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x40000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket1 RCB1 32-bit Device memory + * - 1P/PCIe consolidated to RCA0 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x48000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x48000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket1 RCB2 32-bit Device memory + * - 1P/PCIe consolidated to RCA1 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x50000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x50000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - 2P/PCIe Socket1 RCB3 32-bit Device memory + * - 1P/PCIe consolidated to RCA1 32-bit Device memory + */ + VirtualMemoryTable[++Index].PhysicalBase = 0x58000000ULL; + VirtualMemoryTable[Index].VirtualBase = 0x58000000ULL; + VirtualMemoryTable[Index].Length = 0x8000000ULL; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + /* + * - DDR memory region + */ + NumRegion = PlatformHob->DramInfo.NumRegion; + Count = 0; + while (NumRegion-- > 0) { + if (PlatformHob->DramInfo.NvdRegion[Count]) { /* Skip NVDIMM Region */ + Count++; + continue; + } + + VirtualMemoryTable[++Index].PhysicalBase = PlatformHob->DramInfo.Base[Count]; + VirtualMemoryTable[Index].VirtualBase = PlatformHob->DramInfo.Base[Count]; + VirtualMemoryTable[Index].Length = PlatformHob->DramInfo.Size[Count]; + VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; + Count++; + } + + /* SPM MM NS Buffer for MmCommunicateDxe */ + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdMmBufferBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdMmBufferBase); + VirtualMemoryTable[Index].Length = PcdGet64 (PcdMmBufferSize); + VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; + + /* End of Table */ + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES) 0; + + ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap = VirtualMemoryTable; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.c new file mode 100755 index 000000000000..6ef12a71c374 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.c @@ -0,0 +1,90 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include +#include + +STATIC +VOID +InitMmu ( + IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable + ) +{ + VOID *TranslationTableBase; + UINTN TranslationTableSize; + RETURN_STATUS Status; + + // Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu() + // the MMU Page Table resides in DRAM (even at the top of DRAM as it is the first + // permanent memory allocation) + // + Status = ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Failed to enable MMU\n")); + } + + BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, + EFI_SIZE_TO_PAGES(TranslationTableSize) * EFI_PAGE_SIZE, EfiBootServicesData); +} + +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ) +{ + ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable; + UINTN Index; + + /* Get Virtual Memory Map from the Platform Library */ + ArmPlatformGetVirtualMemoryMap (&MemoryTable); + + Index = 0; + while (MemoryTable[Index].Length != 0) { + if (MemoryTable[Index].Attributes == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryTable[Index].PhysicalBase, + MemoryTable[Index].Length + ); + } else if (MemoryTable[Index].Attributes == ARM_MEMORY_REGION_ATTRIBUTE_DEVICE) { + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED, + MemoryTable[Index].PhysicalBase, + MemoryTable[Index].Length + ); + } + Index++; + } + + BuildMemoryAllocationHob ( + PcdGet64 (PcdFdBaseAddress), + PcdGet32 (PcdFdSize), + EfiRuntimeServicesData + ); + + InitMmu (MemoryTable); + + return EFI_SUCCESS; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.c new file mode 100755 index 000000000000..d6fd94962fe5 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.c @@ -0,0 +1,183 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +// +// Address, Length of the pre-allocated buffer for communication with the secure +// world. +// +STATIC ARM_MEMORY_REGION_DESCRIPTOR mNsCommBuffMemRegion; + +EFI_STATUS +EFIAPI +MmCommunicationLibConstructor ( + VOID + ) +{ + mNsCommBuffMemRegion.PhysicalBase = PcdGet64 (PcdMmBufferBase); + // During boot , Virtual and Physical are same + mNsCommBuffMemRegion.VirtualBase = mNsCommBuffMemRegion.PhysicalBase; + mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize); + + return EFI_SUCCESS; +} + +/** + Communicates with a registered handler. + + This function provides an interface to send and receive messages to the + Standalone MM environment in UEFI PEI phase. + + @param[in, out] CommBuffer A pointer to the buffer to convey + into MMRAM. + @param[in, out] CommSize The size of the data buffer being + passed in. This is optional. + + @retval EFI_SUCCESS The message was successfully posted. + @retval EFI_INVALID_PARAMETER The CommBuffer was NULL. + @retval EFI_BAD_BUFFER_SIZE The buffer size is incorrect for the MM + implementation. If this error is + returned, the MessageLength field in + the CommBuffer header or the integer + pointed by CommSize are updated to reflect + the maximum payload size the + implementation can accommodate. + @retval EFI_ACCESS_DENIED The CommunicateBuffer parameter + or CommSize parameter, if not omitted, + are in address range that cannot be + accessed by the MM environment +**/ +EFI_STATUS +EFIAPI +MmCommunicationCommunicate ( + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommSize OPTIONAL + ) +{ + EFI_MM_COMMUNICATE_HEADER *CommunicateHeader; + ARM_SMC_ARGS CommunicateSmcArgs; + EFI_STATUS Status; + UINTN BufferSize; + + Status = EFI_ACCESS_DENIED; + BufferSize = 0; + + ZeroMem (&CommunicateSmcArgs, sizeof (ARM_SMC_ARGS)); + + // + // Check parameters + // + if (CommBuffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + CommunicateHeader = CommBuffer; + // CommBuffer is a mandatory parameter. Hence, Rely on + // MessageLength + Header to ascertain the + // total size of the communication payload rather than + // rely on optional CommSize parameter + BufferSize = CommunicateHeader->MessageLength + + sizeof (CommunicateHeader->HeaderGuid) + + sizeof (CommunicateHeader->MessageLength); + + // If the length of the CommBuffer is 0 then return the expected length. + if (CommSize != NULL) { + // This case can be used by the consumer of this driver to find out the + // max size that can be used for allocating CommBuffer. + if ((*CommSize == 0) || + (*CommSize > mNsCommBuffMemRegion.Length)) { + *CommSize = mNsCommBuffMemRegion.Length; + return EFI_BAD_BUFFER_SIZE; + } + // + // CommSize must match MessageLength + sizeof (EFI_MM_COMMUNICATE_HEADER); + // + if (*CommSize != BufferSize) { + return EFI_INVALID_PARAMETER; + } + } + + // + // If the buffer size is 0 or greater than what can be tolerated by the MM + // environment then return the expected size. + // + if ((BufferSize == 0) || + (BufferSize > mNsCommBuffMemRegion.Length)) { + CommunicateHeader->MessageLength = mNsCommBuffMemRegion.Length - + sizeof (CommunicateHeader->HeaderGuid) - + sizeof (CommunicateHeader->MessageLength); + return EFI_BAD_BUFFER_SIZE; + } + + // SMC Function ID + CommunicateSmcArgs.Arg0 = ARM_SMC_ID_MM_COMMUNICATE_AARCH64; + + // Cookie + CommunicateSmcArgs.Arg1 = 0; + + // Copy Communication Payload + CopyMem ((VOID *)mNsCommBuffMemRegion.VirtualBase, CommBuffer, BufferSize); + + // comm_buffer_address (64-bit physical address) + CommunicateSmcArgs.Arg2 = (UINTN)mNsCommBuffMemRegion.PhysicalBase; + + // comm_size_address (not used, indicated by setting to zero) + CommunicateSmcArgs.Arg3 = 0; + + // Call the Standalone MM environment. + ArmCallSmc (&CommunicateSmcArgs); + + switch (CommunicateSmcArgs.Arg0) { + case ARM_SMC_MM_RET_SUCCESS: + ZeroMem (CommBuffer, BufferSize); + // On successful return, the size of data being returned is inferred from + // MessageLength + Header. + CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase; + BufferSize = CommunicateHeader->MessageLength + + sizeof (CommunicateHeader->HeaderGuid) + + sizeof (CommunicateHeader->MessageLength); + + CopyMem ( + CommBuffer, + (VOID *)mNsCommBuffMemRegion.VirtualBase, + BufferSize + ); + Status = EFI_SUCCESS; + break; + + case ARM_SMC_MM_RET_INVALID_PARAMS: + Status = EFI_INVALID_PARAMETER; + break; + + case ARM_SMC_MM_RET_DENIED: + Status = EFI_ACCESS_DENIED; + break; + + case ARM_SMC_MM_RET_NO_MEMORY: + // Unexpected error since the CommSize was checked for zero length + // prior to issuing the SMC + Status = EFI_OUT_OF_RESOURCES; + ASSERT (0); + break; + + default: + Status = EFI_ACCESS_DENIED; + ASSERT (0); + } + + return Status; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamDxeLib/NVParamDxeLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamDxeLib/NVParamDxeLib.c new file mode 100644 index 000000000000..5bf20a4430f8 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamDxeLib/NVParamDxeLib.c @@ -0,0 +1,295 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +STATIC EFI_MM_COMMUNICATION_PROTOCOL *mNVParamMmCommProtocol = NULL; +STATIC EFI_MM_COMM_REQUEST *mCommBuffer = NULL; + +/** + This is a notification function registered on EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE + event. It converts a pointer to a new virtual address. + + @param Event Event whose notification function is being invoked. + @param Context Pointer to the notification function's context + +**/ +VOID +EFIAPI +RuntimeAddressChangeEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + gRT->ConvertPointer (0, (VOID**)&mNVParamMmCommProtocol); + gRT->ConvertPointer (0, (VOID**)&mCommBuffer); +} + +EFI_STATUS +EFIAPI +NVParamLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_EVENT VirtualAddressChangeEvent = NULL; + EFI_STATUS Status = EFI_SUCCESS; + + mCommBuffer = AllocateRuntimeZeroPool (sizeof (EFI_MM_COMM_REQUEST)); + ASSERT (mCommBuffer != NULL); + + Status = gBS->LocateProtocol ( + &gEfiMmCommunicationProtocolGuid, + NULL, + (VOID **)&mNVParamMmCommProtocol + ); + ASSERT_EFI_ERROR (Status); + + Status = gBS->CreateEvent ( + EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE, + TPL_CALLBACK, + RuntimeAddressChangeEvent, + NULL, + &VirtualAddressChangeEvent + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +STATIC EFI_STATUS +NvParamMmCommunicate ( + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommSize + ) +{ + if (mNVParamMmCommProtocol == NULL) { + return EFI_INVALID_PARAMETER; + } + + return mNVParamMmCommProtocol->Communicate ( + mNVParamMmCommProtocol, + CommBuffer, + CommSize + ); +} + +STATIC EFI_STATUS +UefiMmCreateNVParamReq ( + IN VOID *Data, + IN UINT64 Size + ) +{ + if (mCommBuffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + CopyGuid (&mCommBuffer->EfiMmHdr.HeaderGuid, &gNVParamMmGuid); + mCommBuffer->EfiMmHdr.MsgLength = Size; + + if (Size != 0) { + ASSERT (Data); + ASSERT (Size <= EFI_MM_MAX_PAYLOAD_SIZE); + + CopyMem (mCommBuffer->PayLoad.Data, Data, Size); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +NVParamGet ( + IN UINT32 Param, + IN UINT16 ACLRd, + OUT UINT32 *Val + ) +{ + EFI_STATUS Status; + EFI_MM_COMMUNICATE_NVPARAM_RES *MmNVParamRes; + UINT64 MmData[5]; + UINTN Size; + + MmData[0] = MM_NVPARAM_FUNC_READ; + MmData[1] = Param; + MmData[2] = (UINT64)ACLRd; + + Status = UefiMmCreateNVParamReq ((VOID *)&MmData, sizeof(MmData)); + if (EFI_ERROR(Status)) { + return Status; + } + + Size = sizeof(EFI_MM_COMM_HEADER_NOPAYLOAD) + sizeof(MmData); + Status = NvParamMmCommunicate ( + mCommBuffer, + &Size + ); + if (EFI_ERROR(Status)) { + return Status; + } + + MmNVParamRes = (EFI_MM_COMMUNICATE_NVPARAM_RES *)&mCommBuffer->PayLoad; + switch (MmNVParamRes->Status) { + case MM_NVPARAM_RES_SUCCESS: + *Val = (UINT32)MmNVParamRes->Value; + return EFI_SUCCESS; + + case MM_NVPARAM_RES_NOT_SET: + return EFI_NOT_FOUND; + + case MM_NVPARAM_RES_NO_PERM: + return EFI_ACCESS_DENIED; + + case MM_NVPARAM_RES_FAIL: + return EFI_DEVICE_ERROR; + + default: + return EFI_INVALID_PARAMETER; + } +} + +EFI_STATUS +NVParamSet ( + IN UINT32 Param, + IN UINT16 ACLRd, + IN UINT16 ACLWr, + IN UINT32 Val + ) +{ + EFI_STATUS Status; + EFI_MM_COMMUNICATE_NVPARAM_RES *MmNVParamRes; + UINT64 MmData[5]; + UINTN Size; + + MmData[0] = MM_NVPARAM_FUNC_WRITE; + MmData[1] = Param; + MmData[2] = (UINT64)ACLRd; + MmData[3] = (UINT64)ACLWr; + MmData[4] = (UINT64)Val; + + Status = UefiMmCreateNVParamReq ((VOID *)&MmData, sizeof(MmData)); + if (EFI_ERROR(Status)) { + return Status; + } + + Size = sizeof(EFI_MM_COMM_HEADER_NOPAYLOAD) + sizeof(MmData); + Status = NvParamMmCommunicate ( + mCommBuffer, + &Size + ); + if (EFI_ERROR(Status)) { + return Status; + } + + MmNVParamRes = (EFI_MM_COMMUNICATE_NVPARAM_RES *)&mCommBuffer->PayLoad; + switch (MmNVParamRes->Status) { + case MM_NVPARAM_RES_SUCCESS: + return EFI_SUCCESS; + + case MM_NVPARAM_RES_NO_PERM: + return EFI_ACCESS_DENIED; + + case MM_NVPARAM_RES_FAIL: + return EFI_DEVICE_ERROR; + + default: + return EFI_INVALID_PARAMETER; + } +} + +EFI_STATUS +NVParamClr ( + IN UINT32 Param, + IN UINT16 ACLWr + ) +{ + EFI_STATUS Status; + EFI_MM_COMMUNICATE_NVPARAM_RES *MmNVParamRes; + UINT64 MmData[5]; + UINTN Size; + + MmData[0] = MM_NVPARAM_FUNC_CLEAR; + MmData[1] = Param; + MmData[2] = 0; + MmData[3] = (UINT64)ACLWr; + + Status = UefiMmCreateNVParamReq ((VOID *)&MmData, sizeof(MmData)); + if (EFI_ERROR(Status)) { + return Status; + } + + Size = sizeof(EFI_MM_COMM_HEADER_NOPAYLOAD) + sizeof(MmData); + Status = NvParamMmCommunicate ( + mCommBuffer, + &Size + ); + if (EFI_ERROR(Status)) { + return Status; + } + + MmNVParamRes = (EFI_MM_COMMUNICATE_NVPARAM_RES *)&mCommBuffer->PayLoad; + switch (MmNVParamRes->Status) { + case MM_NVPARAM_RES_SUCCESS: + return EFI_SUCCESS; + + case MM_NVPARAM_RES_NO_PERM: + return EFI_ACCESS_DENIED; + + case MM_NVPARAM_RES_FAIL: + return EFI_DEVICE_ERROR; + + default: + return EFI_INVALID_PARAMETER; + } +} + +EFI_STATUS +NVParamClrAll (VOID) +{ + EFI_STATUS Status; + EFI_MM_COMMUNICATE_NVPARAM_RES *MmNVParamRes; + UINT64 MmData[5]; + UINTN Size; + + MmData[0] = MM_NVPARAM_FUNC_CLEAR_ALL; + + Status = UefiMmCreateNVParamReq ((VOID *)&MmData, sizeof(MmData)); + if (EFI_ERROR(Status)) { + return Status; + } + + Size = sizeof(EFI_MM_COMM_HEADER_NOPAYLOAD) + sizeof(MmData); + Status = NvParamMmCommunicate ( + mCommBuffer, + &Size + ); + if (EFI_ERROR(Status)) { + return Status; + } + + MmNVParamRes = (EFI_MM_COMMUNICATE_NVPARAM_RES *)&mCommBuffer->PayLoad; + switch (MmNVParamRes->Status) { + case MM_NVPARAM_RES_SUCCESS: + return EFI_SUCCESS; + + case MM_NVPARAM_RES_FAIL: + return EFI_DEVICE_ERROR; + + default: + return EFI_INVALID_PARAMETER; + } +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c new file mode 100755 index 000000000000..8028b6e3e73f --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c @@ -0,0 +1,200 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +EFI_MM_COMM_REQUEST mCommBuffer; + +STATIC VOID +UefiMmCreateNVParamReq ( + IN VOID *Data, + IN UINT64 Size + ) +{ + CopyGuid (&mCommBuffer.EfiMmHdr.HeaderGuid, &gNVParamMmGuid); + mCommBuffer.EfiMmHdr.MsgLength = Size; + + if (Size != 0) { + ASSERT(Data); + ASSERT(Size <= EFI_MM_MAX_PAYLOAD_SIZE); + + CopyMem (mCommBuffer.PayLoad.Data, Data, Size); + } +} + +EFI_STATUS +NVParamGet ( + IN UINT32 Param, + IN UINT16 ACLRd, + OUT UINT32 *Val + ) +{ + EFI_STATUS Status; + EFI_MM_COMMUNICATE_NVPARAM_RES *MmNVParamRes; + UINT64 MmData[5]; + UINTN Size; + + MmData[0] = MM_NVPARAM_FUNC_READ; + MmData[1] = Param; + MmData[2] = (UINT64)ACLRd; + + UefiMmCreateNVParamReq ((VOID *)&MmData, sizeof(MmData)); + + Size = sizeof(EFI_MM_COMM_HEADER_NOPAYLOAD) + sizeof(MmData); + Status = MmCommunicationCommunicate ( + (VOID *) &mCommBuffer, + &Size + ); + if (EFI_ERROR(Status)) { + return Status; + } + + MmNVParamRes = (EFI_MM_COMMUNICATE_NVPARAM_RES *)&mCommBuffer.PayLoad; + switch (MmNVParamRes->Status) { + case MM_NVPARAM_RES_SUCCESS: + *Val = (UINT32)MmNVParamRes->Value; + return EFI_SUCCESS; + + case MM_NVPARAM_RES_NOT_SET: + return EFI_NOT_FOUND; + + case MM_NVPARAM_RES_NO_PERM: + return EFI_ACCESS_DENIED; + + case MM_NVPARAM_RES_FAIL: + return EFI_DEVICE_ERROR; + + default: + return EFI_INVALID_PARAMETER; + } +} + +EFI_STATUS +NVParamSet ( + IN UINT32 Param, + IN UINT16 ACLRd, + IN UINT16 ACLWr, + IN UINT32 Val + ) +{ + EFI_STATUS Status; + EFI_MM_COMMUNICATE_NVPARAM_RES *MmNVParamRes; + UINT64 MmData[5]; + UINTN Size; + + MmData[0] = MM_NVPARAM_FUNC_WRITE; + MmData[1] = Param; + MmData[2] = (UINT64)ACLRd; + MmData[3] = (UINT64)ACLWr; + MmData[4] = (UINT64)Val; + + UefiMmCreateNVParamReq ((VOID *)&MmData, sizeof(MmData)); + Size = sizeof(EFI_MM_COMM_HEADER_NOPAYLOAD) + sizeof(MmData); + Status = MmCommunicationCommunicate ( + (VOID *) &mCommBuffer, + &Size + ); + if (EFI_ERROR(Status)) { + return Status; + } + + MmNVParamRes = (EFI_MM_COMMUNICATE_NVPARAM_RES *)&mCommBuffer.PayLoad; + switch (MmNVParamRes->Status) { + case MM_NVPARAM_RES_SUCCESS: + return EFI_SUCCESS; + + case MM_NVPARAM_RES_NO_PERM: + return EFI_ACCESS_DENIED; + + case MM_NVPARAM_RES_FAIL: + return EFI_DEVICE_ERROR; + + default: + return EFI_INVALID_PARAMETER; + } +} + +EFI_STATUS +NVParamClr ( + IN UINT32 Param, + IN UINT16 ACLWr + ) +{ + EFI_STATUS Status; + EFI_MM_COMMUNICATE_NVPARAM_RES *MmNVParamRes; + UINT64 MmData[5]; + UINTN Size; + + MmData[0] = MM_NVPARAM_FUNC_CLEAR; + MmData[1] = Param; + MmData[2] = 0; + MmData[3] = (UINT64)ACLWr; + + UefiMmCreateNVParamReq ((VOID *)&MmData, sizeof(MmData)); + Size = sizeof(EFI_MM_COMM_HEADER_NOPAYLOAD) + sizeof(MmData); + Status = MmCommunicationCommunicate ( + (VOID *) &mCommBuffer, + &Size + ); + if (EFI_ERROR(Status)) { + return Status; + } + + MmNVParamRes = (EFI_MM_COMMUNICATE_NVPARAM_RES *)&mCommBuffer.PayLoad; + switch (MmNVParamRes->Status) { + case MM_NVPARAM_RES_SUCCESS: + return EFI_SUCCESS; + + case MM_NVPARAM_RES_NO_PERM: + return EFI_ACCESS_DENIED; + + case MM_NVPARAM_RES_FAIL: + return EFI_DEVICE_ERROR; + + default: + return EFI_INVALID_PARAMETER; + } +} + +EFI_STATUS +NVParamClrAll (VOID) +{ + EFI_STATUS Status; + EFI_MM_COMMUNICATE_NVPARAM_RES *MmNVParamRes; + UINT64 MmData[5]; + UINTN Size; + + MmData[0] = MM_NVPARAM_FUNC_CLEAR_ALL; + + UefiMmCreateNVParamReq ((VOID *)&MmData, sizeof(MmData)); + Size = sizeof(EFI_MM_COMM_HEADER_NOPAYLOAD) + sizeof(MmData); + Status = MmCommunicationCommunicate ( + (VOID *) &mCommBuffer, + &Size + ); + if (EFI_ERROR(Status)) { + return Status; + } + + MmNVParamRes = (EFI_MM_COMMUNICATE_NVPARAM_RES *)&mCommBuffer.PayLoad; + switch (MmNVParamRes->Status) { + case MM_NVPARAM_RES_SUCCESS: + return EFI_SUCCESS; + + case MM_NVPARAM_RES_FAIL: + return EFI_DEVICE_ERROR; + + default: + return EFI_INVALID_PARAMETER; + } +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PMProLib/PMPro.c b/Silicon/Ampere/AmpereAltraPkg/Library/PMProLib/PMPro.c new file mode 100644 index 000000000000..96d716d5b474 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PMProLib/PMPro.c @@ -0,0 +1,209 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Mailbox Door Bell */ +#define DBMSG_REG_STRIDE 0x1000 +#define DB_STATUS_ADDR 0x00000020 +#define DB_DIN_ADDR 0x00000000 +#define DB_DIN0_ADDR 0x00000004 +#define DB_DIN1_ADDR 0x00000008 +#define DB_AVAIL_MASK 0x00010000 +#define DB_OUT_ADDR 0x00000010 +#define DB_DOUT0_ADDR 0x00000014 +#define DB_DOUT1_ADDR 0x00000018 +#define DB_ACK_MASK 0x00000001 + +#define DB_MSG_TYPE_SHIFT 28 +#define DB_MSG_CONTROL_BYTE_SHIFT 16 +#define DB_MSG_CONTROL_BYTE_MASK 0x00FF0000U + +/* User message */ +#define DB_USER_MSG 0x6 +#define DB_USER_MSG_HNDL_SHIFT 24 +#define DB_USER_MSG_HNDL_MASK 0x0F000000 +#define DB_MSG_CTRL_BYTE_SHIFT 16 +#define DB_MSG_CTRL_BYTE_MASK 0x00FF0000 +#define DB_USER_MSG_P0_SHIFT 8 +#define DB_USER_MSG_P0_MASK 0x0000FF00 +#define DB_USER_MSG_P1_MASK 0x000000FF +#define DB_ENCODE_USER_MSG(hndl, cb, p0, p1) \ + ((DB_USER_MSG << DB_MSG_TYPE_SHIFT) | \ + (((hndl) << DB_USER_MSG_HNDL_SHIFT) & DB_USER_MSG_HNDL_MASK) | \ + (((cb) << DB_MSG_CTRL_BYTE_SHIFT) & DB_MSG_CTRL_BYTE_MASK) | \ + (((p0) << DB_USER_MSG_P0_SHIFT) & DB_USER_MSG_P0_MASK) | \ + ((p1) & DB_USER_MSG_P1_MASK)) +#define DB_CONFIG_SET_HDLR 2 +#define DB_TURBO_CMD 20 +#define DB_TURBO_ENABLE_SUBCMD 0 + +#define DB_ACL_CMD 30 +#define DB_ACL_ADD4K_SUBCMD 2 +#define DB_ACL_RDWR_FLAG 4 +#define DB_ACL_LOCK_SUBCMD 1 +#define DB_ACL_ENCODE_CMD(cmd, flags) (((cmd) & 0xF) | (((flags) & 0xF)<< 4)) +#define DB_ACL_SET_HADDR(x) ((x << 12) | 1) + +/* Power management message */ +#define DB_PSCI 0x5 +#define DB_PWRMGMT_MSG 0x9 +#define DB_MSG_TYPE_MASK 0xF0000000 +#define DB_PWRMGMT_MSG_HNDL_MASK 0x0F000000 +#define DB_PWRMGMT_MSG_HNDL_SHIFT 24 +#define DB_PWRMGMT_PSCI_STA_SUBCMD 2 +#define DB_PWRMGMT_PSCI_CMD 2 +#define DB_ENCODE_PWRMGMT_MSG(hndl, cb, type) \ + ((DB_PWRMGMT_MSG << DB_MSG_TYPE_SHIFT) | \ + (((hndl) << DB_PWRMGMT_MSG_HNDL_SHIFT) & DB_PWRMGMT_MSG_HNDL_MASK) | \ + (((cb) << DB_MSG_CONTROL_BYTE_SHIFT) & DB_MSG_CONTROL_BYTE_MASK) | \ + (type)) + +#define MB_POLL_INTERVALus 1000 +#define MB_READ_DELAYus 1000 +#define MB_TIMEOUTus 10000000 + +STATIC +UINT64 +PMproGetDBBase ( + UINT8 Socket, + UINT64 Base + ) +{ + return Base + SOCKET_BASE_OFFSET * Socket; +} + +EFI_STATUS +EFIAPI +PMProDBWr ( + UINT8 Db, + UINT32 Data, + UINT32 Param, + UINT32 Param1, + UINT64 MsgReg + ) +{ + INTN TimeoutCnt = MB_TIMEOUTus / MB_POLL_INTERVALus; + UINT32 IntStatOffset; + UINT32 PCodeOffset; + UINT32 ScratchOffset; + UINT32 Scratch1Offset; + + ScratchOffset = (Db * DBMSG_REG_STRIDE) + DB_DOUT0_ADDR; + Scratch1Offset = (Db *DBMSG_REG_STRIDE) + DB_DOUT1_ADDR; + PCodeOffset = (Db * DBMSG_REG_STRIDE) + DB_OUT_ADDR; + IntStatOffset = (Db * DBMSG_REG_STRIDE) + DB_STATUS_ADDR; + + /* Clear previous pending ack if any */ + if ((MmioRead32 ((MsgReg + IntStatOffset)) & DB_ACK_MASK) != 0) { + MmioWrite32 ((MsgReg + IntStatOffset), DB_ACK_MASK); + } + + /* Send message */ + MmioWrite32 ((MsgReg + ScratchOffset), Param); + MmioWrite32 ((MsgReg + Scratch1Offset), Param1); + MmioWrite32 ((MsgReg + PCodeOffset), Data); + + /* Wait for ack */ + while ((MmioRead32 (MsgReg + IntStatOffset) & DB_ACK_MASK) == 0) { + MicroSecondDelay (MB_POLL_INTERVALus); + if (--TimeoutCnt == 0) + return EFI_TIMEOUT; + } + + /* Clear iPP ack */ + MmioWrite32 (MsgReg + IntStatOffset, DB_ACK_MASK); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +PMProTurboEnable ( + UINT8 Socket, + UINT8 Enable + ) +{ + UINT32 Msg; + + Msg = DB_ENCODE_USER_MSG ( + DB_CONFIG_SET_HDLR, + 0, + DB_TURBO_CMD, + DB_TURBO_ENABLE_SUBCMD + ); + + return PMProDBWr ( + PMPRO_DB, + Msg, + Enable, + 0, + PMproGetDBBase (Socket, PMPRO_DB_BASE_REG) + ); +} + +EFI_STATUS +EFIAPI +PMProAclAdd ( + UINT8 Socket, + UINT32 AdrHi, + UINT32 AdrLo + ) +{ + UINT32 Msg; + + Msg = DB_ENCODE_USER_MSG ( + DB_CONFIG_SET_HDLR, + 0, + DB_ACL_CMD, + DB_ACL_ENCODE_CMD (DB_ACL_ADD4K_SUBCMD, DB_ACL_RDWR_FLAG) + ); + + AdrHi = DB_ACL_SET_HADDR (AdrHi); + + return PMProDBWr ( + PMPRO_DB, + Msg, + AdrHi, + AdrLo, + PMproGetDBBase (Socket, PMPRO_DB_BASE_REG) + ); +} + +EFI_STATUS +EFIAPI +PMProSendPSCIAddr ( + UINT8 Socket, + UINT32 AdrHi, + UINT32 AdrLo + ) +{ + UINT32 Msg; + + Msg = DB_ENCODE_PWRMGMT_MSG ( + DB_PWRMGMT_PSCI_CMD, + DB_PWRMGMT_PSCI_STA_SUBCMD, + 0 + ); + + return PMProDBWr ( + DB_PSCI, + Msg, + AdrHi, + AdrLo, + PMproGetDBBase (Socket, PMPRO_DB_BASE_REG) + ); +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.c new file mode 100644 index 000000000000..a54a6539e8ce --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PlatformPeiLib/PlatformPeiLib.c @@ -0,0 +1,46 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +PlatformPeim ( + VOID + ) +{ + UINT64 FvMainBase; + UINT32 FvMainSize; + + ASSERT (FixedPcdGet32 (PcdFvMainCoreSize) != 0); + + // Build FV_MAIN Hand-off block (HOB) to let DXE IPL pick up correctly + FvMainBase = FixedPcdGet64 (PcdFvMainCoreBaseAddress); + FvMainSize = FixedPcdGet32 (PcdFvMainCoreSize); + BuildFvHob (FvMainBase, FvMainSize); + PeiServicesInstallFvInfoPpi ( + &(((EFI_FIRMWARE_VOLUME_HEADER*) ReadUnaligned64 (&FvMainBase)))->FileSystemGuid, + (VOID*) (UINTN) ReadUnaligned64 (&FvMainBase), + FvMainSize, + NULL, + NULL + ); + + return EFI_SUCCESS; +} diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/SMProLib/SMPro.c b/Silicon/Ampere/AmpereAltraPkg/Library/SMProLib/SMPro.c new file mode 100644 index 000000000000..a111c5dd83b2 --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/SMProLib/SMPro.c @@ -0,0 +1,263 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Mailbox Door Bell */ +#define DBMSG_REG_STRIDE 0x1000 +#define DB_STATUS_ADDR 0x00000020 +#define DB_DIN_ADDR 0x00000000 +#define DB_DIN0_ADDR 0x00000004 +#define DB_DIN1_ADDR 0x00000008 +#define DB_AVAIL_MASK 0x00010000 +#define DB_OUT_ADDR 0x00000010 +#define DB_DOUT0_ADDR 0x00000014 +#define DB_DOUT1_ADDR 0x00000018 +#define DB_ACK_MASK 0x00000001 + +/* RAS message */ +#define IPP_RAS_MSG_HNDL_MASK 0x0F000000U +#define IPP_RAS_MSG_HNDL_SHIFT 24 +#define IPP_RAS_MSG_CMD_MASK 0x00F00000U +#define IPP_RAS_MSG_CMD_SHIFT 20 +#define IPP_RAS_MSG_HDLR 1 +#define IPP_RAS_MSG 0xB +#define IPP_RAS_MSG_HDLR 1 +#define IPP_RAS_MSG_SETUP_CHECK 1 /* Setup RAS check polling */ +#define IPP_RAS_MSG_START 2 /* Start RAS polling */ +#define IPP_RAS_MSG_STOP 3 /* Stop RAS polling */ + +#define IPP_MSG_TYPE_SHIFT 28 +#define IPP_MSG_CONTROL_BYTE_SHIFT 16 +#define IPP_MSG_CONTROL_BYTE_MASK 0x00FF0000U + +#define IPP_ENCODE_RAS_MSG(cmd, cb) \ + (((UINT32) (IPP_RAS_MSG) << IPP_MSG_TYPE_SHIFT) | \ + ((IPP_RAS_MSG_HDLR << IPP_RAS_MSG_HNDL_SHIFT) & IPP_RAS_MSG_HNDL_MASK) | \ + (((cb) << IPP_MSG_CONTROL_BYTE_SHIFT) & IPP_MSG_CONTROL_BYTE_MASK) | \ + (((cmd) << IPP_RAS_MSG_CMD_SHIFT) & IPP_RAS_MSG_CMD_MASK)) +#define IPP_DECODE_RAS_MSG_HNDL(data) \ + (((data) & IPP_RAS_MSG_HNDL_MASK) >> IPP_RAS_MSG_HNDL_SHIFT) +#define IPP_DECODE_RAS_MSG_CMD(data) \ + (((data) & IPP_RAS_MSG_CMD_MASK) >> IPP_RAS_MSG_CMD_SHIFT) +#define IPP_DECODE_RAS_MSG_CB(cb) \ + (((cb) & IPP_MSG_CONTROL_BYTE_MASK) >> IPP_MSG_CONTROL_BYTE_SHIFT) + +#define MB_POLL_INTERVALus 1000 +#define MB_READ_DELAYus 1000 +#define MB_TIMEOUTus 10000000 + +UINT64 +SMProGetDBBase ( + UINT8 Socket, + UINT64 Base + ) +{ + return Base + SOCKET_BASE_OFFSET * Socket; +} + +/* + * Read a message from doorbell interface + */ +EFI_STATUS +EFIAPI +SMProDBRd ( + UINT8 Db, + UINT32 *Data, + UINT32 *Param, + UINT32 *Param1, + UINT64 MsgReg + ) +{ + INTN TimeoutCnt = MB_TIMEOUTus / MB_POLL_INTERVALus; + UINT32 DBBaseOffset = Db * DBMSG_REG_STRIDE; + + /* Wait for message since we don't operate in interrupt mode */ + while ((MmioRead32 ((MsgReg + DBBaseOffset + DB_STATUS_ADDR)) & DB_AVAIL_MASK) == 0) { + MicroSecondDelay (MB_POLL_INTERVALus); + if (--TimeoutCnt == 0) { + return EFI_TIMEOUT; + } + } + + /* Read iPP message */ + if (Param != NULL) { + *Param = MmioRead32 (MsgReg + DBBaseOffset + DB_DIN0_ADDR); + } + if (Param1 != NULL) { + *Param1 = MmioRead32 (MsgReg + DBBaseOffset + DB_DIN1_ADDR); + } + *Data = MmioRead32 (MsgReg + DBBaseOffset + DB_DIN_ADDR); + + /* Send acknowledgment */ + MmioWrite32 (MsgReg + DBBaseOffset + DB_STATUS_ADDR, DB_AVAIL_MASK); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SMProDBWr ( + UINT8 Db, + UINT32 Data, + UINT32 Param, + UINT32 Param1, + UINT64 MsgReg + ) +{ + INTN TimeoutCnt = MB_TIMEOUTus / MB_POLL_INTERVALus; + UINT32 IntStatOffset; + UINT32 PCodeOffset; + UINT32 ScratchOffset; + UINT32 Scratch1Offset; + + ScratchOffset = (Db * DBMSG_REG_STRIDE) + DB_DOUT0_ADDR; + Scratch1Offset = (Db *DBMSG_REG_STRIDE) + DB_DOUT1_ADDR; + PCodeOffset = (Db * DBMSG_REG_STRIDE) + DB_OUT_ADDR; + IntStatOffset = (Db * DBMSG_REG_STRIDE) + DB_STATUS_ADDR; + + /* Clear previous pending ack if any */ + if ((MmioRead32 ((MsgReg + IntStatOffset)) & DB_ACK_MASK) != 0) { + MmioWrite32 ((MsgReg + IntStatOffset), DB_ACK_MASK); + } + + /* Send message */ + MmioWrite32 ((MsgReg + ScratchOffset), Param); + MmioWrite32 ((MsgReg + Scratch1Offset), Param1); + MmioWrite32 ((MsgReg + PCodeOffset), Data); + + /* Wait for ack */ + while ((MmioRead32 (MsgReg + IntStatOffset) & DB_ACK_MASK) == 0) { + MicroSecondDelay (MB_POLL_INTERVALus); + if (--TimeoutCnt == 0) + return EFI_TIMEOUT; + } + + /* Clear iPP ack */ + MmioWrite32 (MsgReg + IntStatOffset, DB_ACK_MASK); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SMProAPEISetupCheck ( + UINT32 UAddress, + UINT32 LAddress + ) +{ + UINT32 Msg = IPP_ENCODE_RAS_MSG (IPP_RAS_MSG_SETUP_CHECK, 0); + return SMProDBWr (SMPRO_DB, Msg, UAddress, LAddress, SMPRO_DB_BASE_REG); +} + +EFI_STATUS +EFIAPI +SMProAPEIEnable ( + UINT8 Enable + ) +{ + UINT32 Msg; + + if (Enable != 0) { + Msg = IPP_ENCODE_RAS_MSG (IPP_RAS_MSG_START, 0); + } else { + Msg = IPP_ENCODE_RAS_MSG (IPP_RAS_MSG_STOP, 0); + } + return SMProDBWr (SMPRO_DB, Msg, 0, 0, SMPRO_DB_BASE_REG); +} + +EFI_STATUS +EFIAPI +SMProRegRd ( + UINT8 Socket, + UINT64 Addr, + UINT32 *Value + ) +{ + UINT32 Data0 = (UINT32) Addr; + UINT32 Upper = (UINT32) (Addr >> 32); + UINT32 Data1 = 0; + UINT32 Msg; + EFI_STATUS Status; + + Msg = IPP_ENCODE_DEBUG_MSG ( + IPP_DBG_SUBTYPE_REGREAD, + 0, + (Upper >> 8) & 0xFF, + Upper & 0xFF + ); + Status = SMProDBWr ( + SMPRO_DB, + Msg, + Data0, + Data1, + SMProGetDBBase (Socket, SMPRO_DB_BASE_REG) + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = SMProDBRd ( + SMPRO_DB, + &Msg, + &Data0, + &Data1, + SMProGetDBBase (Socket, SMPRO_DB_BASE_REG) + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((Msg & IPP_DBGMSG_P0_MASK) == 0) { + return EFI_UNSUPPORTED; + } + + if (Value != NULL) { + *Value = Data0; + } + + return Status; +} + +EFI_STATUS +EFIAPI +SMProRegWr ( + UINT8 Socket, + UINT64 Addr, + UINT32 Value + ) +{ + UINT32 Data0 = (UINT32) Addr; + UINT32 Upper = (UINT32) (Addr >> 32); + UINT32 Data1 = Value; + UINT32 Msg; + + Msg = IPP_ENCODE_DEBUG_MSG ( + IPP_DBG_SUBTYPE_REGWRITE, + 0, + (Upper >> 8) & 0xFF, + Upper & 0xFF + ); + + return SMProDBWr ( + SMPRO_DB, + Msg, + Data0, + Data1, + SMProGetDBBase (Socket, SMPRO_DB_BASE_REG) + ); +} diff --git a/Silicon/Ampere/Drivers/ATFHobPei/ATFHobPeim.c b/Silicon/Ampere/Drivers/ATFHobPei/ATFHobPeim.c new file mode 100644 index 000000000000..994b3c675952 --- /dev/null +++ b/Silicon/Ampere/Drivers/ATFHobPei/ATFHobPeim.c @@ -0,0 +1,52 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +STATIC CONST EFI_GUID PlatformInfoHobGUID = PLATFORM_INFO_HOB_GUID; +STATIC CONST EFI_GUID PlatformInfoHobGUID_V2 = PLATFORM_INFO_HOB_GUID_V2; + +VOID +BuildPlatformInformationHob ( + VOID + ) +{ + VOID *Hob; + + /* The ATF HOB handoff base is at PcdSystemMemoryBase */ + Hob = GetNextGuidHob (&PlatformInfoHobGUID, (CONST VOID *) FixedPcdGet64 (PcdSystemMemoryBase)); + /* Build a GUID to pass them Platform HOB data to DXE phase */ + if (Hob) { + BuildGuidDataHob (&PlatformInfoHobGUID, GET_GUID_HOB_DATA (Hob), GET_GUID_HOB_DATA_SIZE (Hob)); + } + + Hob = GetNextGuidHob (&PlatformInfoHobGUID_V2, (CONST VOID *) FixedPcdGet64 (PcdSystemMemoryBase)); + if (Hob) { + BuildGuidDataHob (&PlatformInfoHobGUID_V2, GET_GUID_HOB_DATA (Hob), GET_GUID_HOB_DATA_SIZE (Hob)); + } +} + +EFI_STATUS +EFIAPI +InitializeATFHobPeim ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + BuildPlatformInformationHob (); + + return EFI_SUCCESS; +} diff --git a/Platform/Ampere/FvRules.fdf.inc b/Platform/Ampere/FvRules.fdf.inc new file mode 100644 index 000000000000..6fd3062c8716 --- /dev/null +++ b/Platform/Ampere/FvRules.fdf.inc @@ -0,0 +1,176 @@ +## @file +# +# Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Rules are used with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED { + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) FIXED { + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) FIXED { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.Binary] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional |.depex + TE TE Align = Auto |.efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + COMPRESS PI_STD { + GUIDED { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + COMPRESS PI_STD { + GUIDED { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + COMPRESS PI_STD { + GUIDED { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + } + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + COMPRESS PI_STD { + GUIDED { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + } + +[Rule.Common.DXE_RUNTIME_DRIVER.Binary] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + COMPRESS PI_STD { + GUIDED { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + } + } + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + COMPRESS PI_STD { + GUIDED { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + } + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + COMPRESS PI_STD { + GUIDED { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + } + } + +[Rule.Common.UEFI_DRIVER.Binary] + FILE DRIVER = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } + +[Rule.Common.PEIM.FMP_IMAGE_DESC] + FILE PEIM = $(NAMED_GUID) { + RAW BIN |.acpi + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } diff --git a/Platform/Ampere/JadePkg/TestKeys/Dbb_AmpereTest.cer.pem b/Platform/Ampere/JadePkg/TestKeys/Dbb_AmpereTest.cer.pem new file mode 100644 index 000000000000..cb0646619fdc --- /dev/null +++ b/Platform/Ampere/JadePkg/TestKeys/Dbb_AmpereTest.cer.pem @@ -0,0 +1,19 @@ +-----BEGIN CERTIFICATE----- +MIIDCTCCAfGgAwIBAgIUGEgg1mVptfRS+09lJJMIwVbFNUAwDQYJKoZIhvcNAQEL +BQAwFDESMBAGA1UEAwwJQW1wZXJlIFBLMB4XDTIwMDcxNDE3MTY1NloXDTMwMDcx +MjE3MTY1NlowFDESMBAGA1UEAwwJQW1wZXJlIFBLMIIBIjANBgkqhkiG9w0BAQEF +AAOCAQ8AMIIBCgKCAQEAsbqKyJyzDIa2y7krGD2nPncKzRDZzRl9LGr8hGBf62Ok +v58GZLCT9O2LCtEsZ0oe3LvfPFIw2N09r66KSl7ZD6wswl9gZChZ3WZy6k912LRx +VlFFjb7t7VbP4GETrHUcq07bPfnwFN/g8rQxACxpJzcGFiAuwg9elml2bIbvfPgj +qoS7uB8maJFuyP2JFeHJk3moiwguMjwQKJP8cDfb9MRz+fdgPjvCmGkkTRa86iNu +k0PY0ZsOT4hm/DYZY/5hnt8icHd4KLGdStgIM5nsjy2hxR9CWmUX2YSgbIA+LBAA +TsYFx8Y2ZLkNF4n7aOeOAzy3kp7JQ1VLAwtETnen8QIDAQABo1MwUTAdBgNVHQ4E +FgQUgGP/5BA3EezlW2drnfIYJ4Jrp4UwHwYDVR0jBBgwFoAUgGP/5BA3EezlW2dr +nfIYJ4Jrp4UwDwYDVR0TAQH/BAUwAwEB/zANBgkqhkiG9w0BAQsFAAOCAQEAJgLU +dRWjrXg+rVa1lKjLuuwM6X6CHwMuRcBtB6uHrsjkx7+3efjziu01wjvBPB+Z0Cl5 +FcdkmNAo+ApIOb1fLEaikw/xyh+vucBSg8IXV8fL1a823PB3zbA1zKpBl8afTplW +QF1bHczU4GcckDTgQo/B4uvp6CCTN6jivx76kpV4/9zhOacWh4c5SIgOPCClVMOm +QtkXWLNwpGtSDZl0VHDX+JZ54N5yjqrCFq5vXM8NHncbF0vqNZxKbpze0RkjRtPl +iW5V2cz0EWTESw7sspDvL85IsV/9vQNAyS5VuO2f6ldgirHHUPLq1NqzJmWDyc0T +tY3Mu2Vaozm6FUyGDg== +-----END CERTIFICATE----- diff --git a/Platform/Ampere/JadePkg/TestKeys/Dbb_AmpereTest.priv.pem b/Platform/Ampere/JadePkg/TestKeys/Dbb_AmpereTest.priv.pem new file mode 100644 index 000000000000..d09aedc7e582 --- /dev/null +++ b/Platform/Ampere/JadePkg/TestKeys/Dbb_AmpereTest.priv.pem @@ -0,0 +1,28 @@ +-----BEGIN PRIVATE KEY----- +MIIEvAIBADANBgkqhkiG9w0BAQEFAASCBKYwggSiAgEAAoIBAQCxuorInLMMhrbL +uSsYPac+dwrNENnNGX0savyEYF/rY6S/nwZksJP07YsK0SxnSh7cu988UjDY3T2v +ropKXtkPrCzCX2BkKFndZnLqT3XYtHFWUUWNvu3tVs/gYROsdRyrTts9+fAU3+Dy +tDEALGknNwYWIC7CD16WaXZshu98+COqhLu4HyZokW7I/YkV4cmTeaiLCC4yPBAo +k/xwN9v0xHP592A+O8KYaSRNFrzqI26TQ9jRmw5PiGb8Nhlj/mGe3yJwd3gosZ1K +2AgzmeyPLaHFH0JaZRfZhKBsgD4sEABOxgXHxjZkuQ0Xifto544DPLeSnslDVUsD +C0ROd6fxAgMBAAECggEACF/RykIX7a8rTc4bybid+MODLsZsfM2GqGEiJNqlqmG3 +kY/crUHkttW6h3fzr6o+aggwLJdy1cUW8wA2Y+q0L5jdQwtbb1y3X0dEguXbl6po +7LhHnrYwX86HXPs2AhpCj4/XpMPyHAmwf78dz/RHwCFHmCNMELjIrC2r9tEk166F +WWMKUCP7UD6Mq/nz74vaGIbGjIDqsPGi5iAToMIIPlASYvGV50uCPFCpdek/26ao +srpjbgzuno3h5C5FQgHhpeGcyTykEDst7LoI7dJfOa0B+ue8p2QIbrT11f4NJxpC +Ay3jn4gXCFxXFt2wkHv40sGrd/GpI2xemai0pAlOQQKBgQDkm6h0ZdECRpxDXSAa +3fhPgfom/bvW062dnCfW3SJjHsiWR47oIhQvPdChr10viVW9kaxE1QIIYldMuiUu +AHo12Czg2M0MTk9DDwsEA+MefolQyWXUDRttS/k6rhdqcOwqCBCle5QWl4vdK+AZ +2ACBh4d1+J1B2bxXC0e2yQbXnwKBgQDHBjTXo1vIQkz4JQPndkWG+DlIPmuUOwwj +pWC6EKAAGkTC6x10uI4/I/jcRKEyxmXepyOrKaqK8XYKK4DiFKpVlAWZkECH96DY +6jqkCE+Wrsx4Hrt1AZ/mA8/+s3nPUxCC7IUPmXvcHc8OfoAlXXWH8jdknjkmKXjz +d9JI0TeWbwKBgCUFRBldZ6R7tNB/4zQWoCCYBt+LlYCrlOECKb104B23HXqgqfbT +lfs0gnW8hVWuYtEpJwGakRK0gjitqFmzwBa6JEJhOYt1nwZYCEulKYGFskz/4Fqf +qMJhXEHxcV9OXCBOYAu8YHXsIr01Xrwwq5xOS1SCZ00DqqlZ7Uofcdk3AoGAYQbH +kDEVt8WK3Ja/FoJ0Vt6AnpW/wJ4gxugDBfLA7gvgZd5Vl+e5gVK6KjhTFfvfAfMd +0n4XpHEfCMo4pP9KIzpsmHbY3vB8PAPE3t8mXeGN0Sm6XcqS94H4TsWUptxp+knw +fLBoz+DAZuKI+q5bdBFDrAvu9InXa2qI2/MTVIUCgYBO+SO94KQ8h5uHrdXsHB+M +mVOq+Nsas8yvRRv5ESJ7FN3pLA2BK4McH3x0ZrzYPMZZGKguZiy9CawUhxu362qg +TtpKjhAs3Lm5CKTuJBFiWc2pTeT+8/gwmphzwhoCWJUqztB2iR4G/YGWlc+3/VEB +IVFzgDUaH++/RS7c7XNKRg== +-----END PRIVATE KEY----- diff --git a/Platform/Ampere/JadePkg/jade_board_setting.txt b/Platform/Ampere/JadePkg/jade_board_setting.txt new file mode 100644 index 000000000000..8ed7e06c4102 --- /dev/null +++ b/Platform/Ampere/JadePkg/jade_board_setting.txt @@ -0,0 +1,187 @@ +# Sample board setting +# +# This is a sample board setting as used for the +# Ampere eMAG2 reference design. +# +# Name, offset (hex), value +# value can be hex or decimal +# + +NV_SI_RO_BOARD_VENDOR, 0x0000, 0x0000CD3A +NV_SI_RO_BOARD_TYPE, 0x0008, 0x00000000 +NV_SI_RO_BOARD_REV, 0x0010, 0x00000000 +NV_SI_RO_BOARD_CFG, 0x0018, 0x00000000 +NV_SI_RO_BOARD_S0_DIMM_AVAIL, 0x0020, 0x0000FFFF +NV_SI_RO_BOARD_S1_DIMM_AVAIL, 0x0028, 0x0000FFFF +NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ, 0x0030, 0x000080E8 +NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ, 0x0038, 0x000080E8 +NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ, 0x0040, 0x00002710 +NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ, 0x0048, 0x00002710 +NV_SI_RO_BOARD_TPM_LOC, 0x0050, 0x00000000 +NV_SI_RO_BOARD_I2C0_FREQ_KHZ, 0x0058, 0x00000190 +NV_SI_RO_BOARD_I2C1_FREQ_KHZ, 0x0060, 0x00000190 +NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ, 0x0068, 0x00000190 +NV_SI_RO_BOARD_I2C3_FREQ_KHZ, 0x0070, 0x00000190 +NV_SI_RO_BOARD_I2C9_FREQ_KHZ, 0x0078, 0x00000190 +NV_SI_RO_BOARD_2P_CFG, 0x0080, 0xFFFFFF01 +NV_SI_RO_BOARD_S0_RCA0_CFG, 0x0088, 0x00000000 +NV_SI_RO_BOARD_S0_RCA1_CFG, 0x0090, 0x00000000 +NV_SI_RO_BOARD_S0_RCA2_CFG, 0x0098, 0x00000004 +NV_SI_RO_BOARD_S0_RCA3_CFG, 0x00A0, 0x00000004 +NV_SI_RO_BOARD_S0_RCB0_LO_CFG, 0x00A8, 0x00020002 +NV_SI_RO_BOARD_S0_RCB0_HI_CFG, 0x00B0, 0x00020002 +NV_SI_RO_BOARD_S0_RCB1_LO_CFG, 0x00B8, 0x00020002 +NV_SI_RO_BOARD_S0_RCB1_HI_CFG, 0x00C0, 0x00020002 +NV_SI_RO_BOARD_S0_RCB2_LO_CFG, 0x00C8, 0x00020002 +NV_SI_RO_BOARD_S0_RCB2_HI_CFG, 0x00D0, 0x00000003 +NV_SI_RO_BOARD_S0_RCB3_LO_CFG, 0x00D8, 0x00000003 +NV_SI_RO_BOARD_S0_RCB3_HI_CFG, 0x00E0, 0x00020002 +NV_SI_RO_BOARD_S1_RCA0_CFG, 0x00E8, 0x00000000 +NV_SI_RO_BOARD_S1_RCA1_CFG, 0x00F0, 0x00000000 +NV_SI_RO_BOARD_S1_RCA2_CFG, 0x00F8, 0x02020202 +NV_SI_RO_BOARD_S1_RCA3_CFG, 0x0100, 0x00030003 +NV_SI_RO_BOARD_S1_RCB0_LO_CFG, 0x0108, 0x00000003 +NV_SI_RO_BOARD_S1_RCB0_HI_CFG, 0x0110, 0x00020002 +NV_SI_RO_BOARD_S1_RCB1_LO_CFG, 0x0118, 0x00020002 +NV_SI_RO_BOARD_S1_RCB1_HI_CFG, 0x0120, 0x00000003 +NV_SI_RO_BOARD_S1_RCB2_LO_CFG, 0x0128, 0x00020002 +NV_SI_RO_BOARD_S1_RCB2_HI_CFG, 0x0130, 0x00020002 +NV_SI_RO_BOARD_S1_RCB3_LO_CFG, 0x0138, 0x00020002 +NV_SI_RO_BOARD_S1_RCB3_HI_CFG, 0x0140, 0x00020002 +NV_SI_RO_BOARD_T_LTLM_DELTA_P0, 0x0148, 0x00000001 +NV_SI_RO_BOARD_T_LTLM_DELTA_P1, 0x0150, 0x00000002 +NV_SI_RO_BOARD_T_LTLM_DELTA_P2, 0x0158, 0x00000003 +NV_SI_RO_BOARD_T_LTLM_DELTA_P3, 0x0160, 0x00000004 +NV_SI_RO_BOARD_T_LTLM_DELTA_M1, 0x0168, 0xFFFFFFFF +NV_SI_RO_BOARD_T_LTLM_DELTA_M2, 0x0170, 0xFFFFFFFE +NV_SI_RO_BOARD_T_LTLM_DELTA_M3, 0x0178, 0xFFFFFFFD +NV_SI_RO_BOARD_P_LM_PID_P, 0x0180, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_I, 0x0188, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_I_L_THOLD, 0x0190, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_I_H_THOLD, 0x0198, 0x00000000 +NV_SI_RO_BOARD_P_LM_PID_D, 0x01A0, 0x00000000 +NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST, 0x01A8, 0x00000000 +NV_SI_RO_BOARD_TPM_ALG_ID, 0x01B0, 0x00000002 +NV_SI_RO_BOARD_DDR_SPEED_GRADE, 0x01B8, 0x00000C80 +NV_SI_RO_BOARD_DDR_S0_RTT_WR, 0x01C0, 0x00000000 +NV_SI_RO_BOARD_DDR_S1_RTT_WR, 0x01C8, 0x00000000 +NV_SI_RO_BOARD_DDR_S0_RTT_NOM, 0x01D0, 0xFF010107 +NV_SI_RO_BOARD_DDR_S1_RTT_NOM, 0x01D8, 0xFF010107 +NV_SI_RO_BOARD_DDR_S0_RTT_PARK, 0x01E0, 0x00010000 +NV_SI_RO_BOARD_DDR_S1_RTT_PARK, 0x01E8, 0x00010000 +NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_1DPC, 0x01F0, 0x00000000 +NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_1DPC, 0x01F8, 0x00000000 +NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_1DPC, 0x0200, 0x00000000 +NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_1DPC, 0x0208, 0x00000000 +NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_2DPC, 0x0210, 0x000C0CCC +NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_2DPC, 0x0218, 0x000C0CCC +NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_2DPC, 0x0220, 0x00030333 +NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_2DPC, 0x0228, 0x00030333 +NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_1DPC, 0x0230, 0x00030333 +NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_1DPC, 0x0238, 0x00030333 +NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_1DPC, 0x0240, 0x00030333 +NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_1DPC, 0x0248, 0x00030333 +NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_2DPC, 0x0250, 0x000D0DDD +NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_2DPC, 0x0258, 0x000E0EEE +NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_2DPC, 0x0260, 0x00070777 +NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_2DPC, 0x0268, 0x000B0BBB +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_1DPC, 0x0270, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_1DPC, 0x0278, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_1DPC, 0x0280, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_1DPC, 0x0288, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_2DPC, 0x0290, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_2DPC, 0x0298, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_2DPC, 0x02A0, 0x00000005 +NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_2DPC, 0x02A8, 0x0090DD90 +NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_1DPC, 0x02B0, 0x00000024 +NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_1DPC, 0x02B8, 0x0000001A +NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_2DPC, 0x02C0, 0x0000005B +NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_2DPC, 0x02C8, 0x00000024 +NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_DEFAULT, 0x02D0, 0x02800280 +NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_DEFAULT, 0x02D8, 0x90909090 +NV_SI_RO_BOARD_DDR_WRDQS_SHIFT_DEFAULT, 0x02E0, 0x00000000 +NV_SI_RO_BOARD_DDR_ADCMD_DLY_DEFAULT, 0x02E8, 0x00C000C0 +NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_ADJ, 0x02F0, 0x00000000 +NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_ADJ, 0x02F8, 0x00000000 +NV_SI_RO_BOARD_DDR_PHY_VREF_ADJ, 0x0300, 0x00000000 +NV_SI_RO_BOARD_DDR_DRAM_VREF_ADJ, 0x0308, 0x00000000 +NV_SI_RO_BOARD_DDR_WR_PREAMBLE_CYCLE, 0x0310, 0x02010201 +NV_SI_RO_BOARD_DDR_ADCMD_2T_MODE, 0x0318, 0x00010000 +NV_SI_RO_BOARD_I2C_VRD_CONFIG_INFO, 0x0320, 0x00000000 +NV_SI_RO_BOARD_DDR_PHY_FEATURE_CTRL, 0x0328, 0x00000000 +NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_ACCESS, 0x0330, 0x01050106 +NV_SI_RO_BOARD_DIMM_TEMP_THRESHOLD, 0x0338, 0x00000554 +NV_SI_RO_BOARD_DIMM_SPD_COMPARE_DISABLE, 0x0340, 0x00000000 +NV_SI_RO_BOARD_S0_PCIE_CLK_CFG, 0x0348, 0x00000000 +NV_SI_RO_BOARD_S0_RCA4_CFG, 0x0350, 0x02020202 +NV_SI_RO_BOARD_S0_RCA5_CFG, 0x0358, 0x02020202 +NV_SI_RO_BOARD_S0_RCA6_CFG, 0x0360, 0x02020202 +NV_SI_RO_BOARD_S0_RCA7_CFG, 0x0368, 0x02020003 +NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET, 0x0370, 0x00000000 +NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET, 0x0378, 0x00000000 +NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET, 0x0380, 0x00000000 +NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET, 0x0388, 0x00000000 +NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET, 0x0390, 0x00000000 +NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET, 0x0398, 0x00000000 +NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET, 0x03A0, 0x00000000 +NV_SI_RO_BOARD_S0_RCB1B_TXRX_G3PRESET, 0x03A8, 0x00000000 +NV_SI_RO_BOARD_S0_RCB2A_TXRX_G3PRESET, 0x03B0, 0x00000000 +NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET, 0x03B8, 0x00000000 +NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET, 0x03C0, 0x00000000 +NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET, 0x03C8, 0x00000000 +NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET, 0x03D0, 0x00000000 +NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET, 0x03D8, 0x00000000 +NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET, 0x03E0, 0x00000000 +NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET, 0x03E8, 0x00000000 +NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET, 0x03F0, 0x57575757 +NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET, 0x03F8, 0x57575757 +NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET, 0x0400, 0x57575757 +NV_SI_RO_BOARD_S0_RCA3_TXRX_G4PRESET, 0x0408, 0x57575757 +NV_SI_RO_BOARD_S0_RCB0A_TXRX_G4PRESET, 0x0410, 0x57575757 +NV_SI_RO_BOARD_S0_RCB0B_TXRX_G4PRESET, 0x0418, 0x57575757 +NV_SI_RO_BOARD_S0_RCB1A_TXRX_G4PRESET, 0x0420, 0x57575757 +NV_SI_RO_BOARD_S0_RCB1B_TXRX_G4PRESET, 0x0428, 0x57575757 +NV_SI_RO_BOARD_S0_RCB2A_TXRX_G4PRESET, 0x0430, 0x57575757 +NV_SI_RO_BOARD_S0_RCB2B_TXRX_G4PRESET, 0x0438, 0x57575757 +NV_SI_RO_BOARD_S0_RCB3A_TXRX_G4PRESET, 0x0440, 0x57575757 +NV_SI_RO_BOARD_S0_RCB3B_TXRX_G4PRESET, 0x0448, 0x57575757 +NV_SI_RO_BOARD_S0_RCA4_TXRX_G4PRESET, 0x0450, 0x57575757 +NV_SI_RO_BOARD_S0_RCA5_TXRX_G4PRESET, 0x0458, 0x57575757 +NV_SI_RO_BOARD_S0_RCA6_TXRX_G4PRESET, 0x0460, 0x57575757 +NV_SI_RO_BOARD_S0_RCA7_TXRX_G4PRESET, 0x0468, 0x57575757 +NV_SI_RO_BOARD_S1_PCIE_CLK_CFG, 0x0470, 0x00000000 +NV_SI_RO_BOARD_S1_RCA4_CFG, 0x0478, 0x02020202 +NV_SI_RO_BOARD_S1_RCA5_CFG, 0x0480, 0x02020202 +NV_SI_RO_BOARD_S1_RCA6_CFG, 0x0488, 0x02020202 +NV_SI_RO_BOARD_S1_RCA7_CFG, 0x0490, 0x02020003 +NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET, 0x0498, 0x00000000 +NV_SI_RO_BOARD_S1_RCA3_TXRX_G3PRESET, 0x04A0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET, 0x04A8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB0B_TXRX_G3PRESET, 0x04B0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB1A_TXRX_G3PRESET, 0x04B8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB1B_TXRX_G3PRESET, 0x04C0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB2A_TXRX_G3PRESET, 0x04C8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB2B_TXRX_G3PRESET, 0x04D0, 0x00000000 +NV_SI_RO_BOARD_S1_RCB3A_TXRX_G3PRESET, 0x04D8, 0x00000000 +NV_SI_RO_BOARD_S1_RCB3B_TXRX_G3PRESET, 0x04E0, 0x00000000 +NV_SI_RO_BOARD_S1_RCA4_TXRX_G3PRESET, 0x04E8, 0x00000000 +NV_SI_RO_BOARD_S1_RCA5_TXRX_G3PRESET, 0x04F0, 0x00000000 +NV_SI_RO_BOARD_S1_RCA6_TXRX_G3PRESET, 0x04F8, 0x00000000 +NV_SI_RO_BOARD_S1_RCA7_TXRX_G3PRESET, 0x0500, 0x00000000 +NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET, 0x0508, 0x57575757 +NV_SI_RO_BOARD_S1_RCA3_TXRX_G4PRESET, 0x0510, 0x57575757 +NV_SI_RO_BOARD_S1_RCB0A_TXRX_G4PRESET, 0x0518, 0x57575757 +NV_SI_RO_BOARD_S1_RCB0B_TXRX_G4PRESET, 0x0520, 0x57575757 +NV_SI_RO_BOARD_S1_RCB1A_TXRX_G4PRESET, 0x0528, 0x57575757 +NV_SI_RO_BOARD_S1_RCB1B_TXRX_G4PRESET, 0x0530, 0x57575757 +NV_SI_RO_BOARD_S1_RCB2A_TXRX_G4PRESET, 0x0538, 0x57575757 +NV_SI_RO_BOARD_S1_RCB2B_TXRX_G4PRESET, 0x0540, 0x57575757 +NV_SI_RO_BOARD_S1_RCB3A_TXRX_G4PRESET, 0x0548, 0x57575757 +NV_SI_RO_BOARD_S1_RCB3B_TXRX_G4PRESET, 0x0550, 0x57575757 +NV_SI_RO_BOARD_S1_RCA4_TXRX_G4PRESET, 0x0558, 0x57575757 +NV_SI_RO_BOARD_S1_RCA5_TXRX_G4PRESET, 0x0560, 0x57575757 +NV_SI_RO_BOARD_S1_RCA6_TXRX_G4PRESET, 0x0568, 0x57575757 +NV_SI_RO_BOARD_S1_RCA7_TXRX_G4PRESET, 0x0570, 0x57575757 +NV_SI_RO_BOARD_2P_CE_MASK_THRESHOLD, 0x0578, 0x00000002 +NV_SI_RO_BOARD_2P_CE_MASK_INTERVAL, 0x0580, 0x000001A4 +NV_SI_RO_BOARD_SX_PHY_CFG_SETTING, 0x0588, 0x00000000 diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformHelper.S b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformHelper.S new file mode 100755 index 000000000000..770aa9424eed --- /dev/null +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformHelper.S @@ -0,0 +1,45 @@ +/** @file + + Copyright (c) 2020, Ampere Computing LLC. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +/** + * Derived from edk2/ArmPlatformPkg/Library/ArmPlatformLibNull/AArch64/ArmPlatformHelper.S + **/ + +#include +#include + +ASM_FUNC(ArmPlatformPeiBootAction) + ret + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore)) + ret + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformIsPrimaryCore) + ldr x0, =0x1 + ret + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ASM_FUNC(ArmPlatformGetCorePosition) + and x1, x0, #ARM_CORE_MASK + and x0, x0, #ARM_CLUSTER_MASK + add x0, x1, x0, LSR #7 + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED -- 2.17.1