From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by mx.groups.io with SMTP id smtpd.web10.130.1608057779443400457 for ; Tue, 15 Dec 2020 10:42:59 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=wH3ETEYi; spf=pass (domain: nuviainc.com, ip: 209.85.221.66, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f66.google.com with SMTP id 91so20872193wrj.7 for ; Tue, 15 Dec 2020 10:42:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=9IbOiCUj3w17jHQzgwD2D2nPcqOhqm7oZsicpO32dRg=; b=wH3ETEYiPxN8Gu3pZKlwYPjGdeaGXI5sJ4+RPOxThUKG+2TiSitG/jCw1BiUDoEkMb e1k3jpnJO+5RmL3yN91Bmeo+e9+cvC9unvKmdymJWvEs/TiENG05O6CZjq2t6Uxdd5pi X+Nr4k3HZi147yqaXR+5bTrIz3Pi5DGeuyKJP4SHmLj1d+G0cbnxR5W+0+o8rfFpi+15 hc6hO8ppiXOohRDZBKREoaOuJ0bY3mHT3KadrdMs7DBwGW5a5AnbRE2zpIhcOVP2hLiF 66VXfj2d19tJK0sOP3MymzYbJz9nQHlFxQWFbcs5mxFGsQsuZKaQekFPYW3P3HC8jky2 yETg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=9IbOiCUj3w17jHQzgwD2D2nPcqOhqm7oZsicpO32dRg=; b=eWuuKDgppAKsX13w+ks4vTQYpqyh/io/hJFuSk7ZsFO7IARj3nNNQqDlj7Cu6O8oHb TF55l5sI3m/zKz7ovzm/5o1Q/7CVaJicC1L6/FQrCSlAcnd/gcPh1AwNdfpytfrnX8eL U3Cxz9CZTwYKkBJW4amaz4uupN1tq6giAKkeUoOSpgng/1PhNbKRa4VgOpDU9jzjU26q dmb89jri3cAOOyyEc2UpO1SPYWNfiQxyL/2IpcggjYJDZKzkjMtnbPH/qRuWjxrBtPQc /TdV2RmAe1UqDNnNT3G/t8eeGCEtgUuAQGDK6f1MNu0XfhZZ3bTKlxsju7Ez2vjrr5wt qcpQ== X-Gm-Message-State: AOAM530WUHfV9DC8ZrEsddyD9K5kPdhfXyDIB1zEVoy7VbJCqFhTuRBg F19FToTaaxYaDxZEfv6fVZ4+VA== X-Google-Smtp-Source: ABdhPJzS7SBMuSlBjjAzVZ1yidDJzQns9yrbsiw7y8x1G90MQOnXcq8TIcLXPO8ZDK4CBhvSxo+eEQ== X-Received: by 2002:adf:f684:: with SMTP id v4mr36106908wrp.387.1608057777881; Tue, 15 Dec 2020 10:42:57 -0800 (PST) Return-Path: Received: from vanye (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id v189sm39413127wmg.14.2020.12.15.10.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 10:42:57 -0800 (PST) Date: Tue, 15 Dec 2020 18:42:55 +0000 From: "Leif Lindholm" To: Rebecca Cran Cc: devel@edk2.groups.io, Ard Biesheuvel Subject: Re: [PATCH v4 03/10] ArmPkg: Add register encoding definition for MMFR2 Message-ID: <20201215184255.GC1664@vanye> References: <20201207175427.28712-1-rebecca@nuviainc.com> <20201207175427.28712-4-rebecca@nuviainc.com> MIME-Version: 1.0 In-Reply-To: <20201207175427.28712-4-rebecca@nuviainc.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Dec 07, 2020 at 10:54:20 -0700, Rebecca Cran wrote: > Add register encoding definition for Memory Model Feature Register 2. > We need to define it here because we build for ARMv8.0, which doesn't > have it. > > Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm > --- > ArmPkg/Include/Chipset/AArch64.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h > index 0ade5cce91c3..7c2b592f92ee 100644 > --- a/ArmPkg/Include/Chipset/AArch64.h > +++ b/ArmPkg/Include/Chipset/AArch64.h > @@ -112,6 +112,10 @@ > #define ARM_VECTOR_LOW_A32_FIQ 0x700 > #define ARM_VECTOR_LOW_A32_SERR 0x780 > > +// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we > +// build for ARMv8.0, we need to define the register here. > +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 > + > #define VECTOR_BASE(tbl) \ > .section .text.##tbl##,"ax"; \ > .align 11; \ > -- > 2.26.2 >