Re: [PATCH v4 08/10] ArmPkg: Update ArmLibPrivate.h with cache register definitions

["Leif Lindholm" <leif@nuviainc.com>]

On Mon, Dec 07, 2020 at 10:54:25 -0700, Rebecca Cran wrote:
> Update the cache definitions in ArmLibPrivate.h based on current
> ARMv8 documentation.
> 
> Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>

Reviewed-by: Leif Lindholm <leif@nuviainc.com>

> ---
>  ArmPkg/Library/ArmLib/ArmLibPrivate.h | 91 ++++++++++++++++++++
>  1 file changed, 91 insertions(+)
> 
> diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
> index 5eecbc0e1c43..fb1e2cc6b2ac 100644
> --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h
> +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
> @@ -1,5 +1,7 @@
>  /** @file
> +  ArmLibPrivate.h
>  
> +  Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>
>    Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
>  
>    SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -50,6 +52,95 @@
>  #define CACHE_ARCHITECTURE_UNIFIED            (0UL)
>  #define CACHE_ARCHITECTURE_SEPARATE           (1UL)
>  
> +
> +/// Defines the structure of the CSSELR (Cache Size Selection) register
> +typedef union {
> +  struct {
> +    UINT32    InD       :1;  ///< Instruction not Data bit
> +    UINT32    Level     :3;  ///< Cache level (zero based)
> +    UINT32    TnD       :1;  ///< Allocation not Data bit
> +    UINT32    Reserved  :27; ///< Reserved, RES0
> +  } Bits; ///< Bitfield definition of the register
> +  UINT32 Data; ///< The entire 32-bit value
> +} CSSELR_DATA;
> +
> +/// The cache type values for the InD field of the CSSELR register
> +typedef enum
> +{
> +  /// Select the data or unified cache
> +  CsselrCacheTypeDataOrUnified = 0,
> +  /// Select the instruction cache
> +  CsselrCacheTypeInstruction,
> +  CsselrCacheTypeMax
> +} CSSELR_CACHE_TYPE;
> +
> +/// Defines the structure of the CCSIDR (Current Cache Size ID) register
> +typedef union {
> +  struct {
> +    UINT64    LineSize           :3;  ///< Line size (Log2(Num bytes in cache) - 4)
> +    UINT64    Associativity      :10; ///< Associativity - 1
> +    UINT64    NumSets            :15; ///< Number of sets in the cache -1
> +    UINT64    Unknown            :4;  ///< Reserved, UNKNOWN
> +    UINT64    Reserved           :32; ///< Reserved, RES0
> +  } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
> +  struct {
> +    UINT64    LineSize           :3;  ///< Line size (Log2(Num bytes in cache) - 4)
> +    UINT64    Associativity      :21; ///< Associativity - 1
> +    UINT64    Reserved1          :8;  ///< Reserved, RES0
> +    UINT64    NumSets            :24; ///< Number of sets in the cache -1
> +    UINT64    Reserved2          :8;  ///< Reserved, RES0
> +  } BitsCcidx; ///< Bitfield definition of the register when FEAT_IDX is supported.
> +  UINT64 Data; ///< The entire 64-bit value
> +} CCSIDR_DATA;
> +
> +/// Defines the structure of the AARCH32 CCSIDR2 register.
> +typedef union {
> +  struct {
> +    UINT32 NumSets               :24; ///< Number of sets in the cache - 1
> +    UINT32 Reserved              :8;  ///< Reserved, RES0
> +  } Bits; ///< Bitfield definition of the register
> +  UINT32 Data; ///< The entire 32-bit value
> +} CSSIDR2_DATA;
> +
> +/** Defines the structure of the CLIDR (Cache Level ID) register.
> + *
> + * The lower 32 bits are the same for both AARCH32 and AARCH64
> + * so we can use the same structure for both.
> +**/
> +typedef union {
> +  struct {
> +    UINT32    Ctype1   : 3; ///< Level 1 cache type
> +    UINT32    Ctype2   : 3; ///< Level 2 cache type
> +    UINT32    Ctype3   : 3; ///< Level 3 cache type
> +    UINT32    Ctype4   : 3; ///< Level 4 cache type
> +    UINT32    Ctype5   : 3; ///< Level 5 cache type
> +    UINT32    Ctype6   : 3; ///< Level 6 cache type
> +    UINT32    Ctype7   : 3; ///< Level 7 cache type
> +    UINT32    LoUIS    : 3; ///< Level of Unification Inner Shareable
> +    UINT32    LoC      : 3; ///< Level of Coherency
> +    UINT32    LoUU     : 3; ///< Level of Unification Uniprocessor
> +    UINT32    Icb      : 3; ///< Inner Cache Boundary
> +  } Bits; ///< Bitfield definition of the register
> +  UINT32 Data; ///< The entire 32-bit value
> +} CLIDR_DATA;
> +
> +/// The cache types reported in the CLIDR register.
> +typedef enum {
> +  /// No cache is present
> +  ClidrCacheTypeNone = 0,
> +  /// There is only an instruction cache
> +  ClidrCacheTypeInstructionOnly,
> +  /// There is only a data cache
> +  ClidrCacheTypeDataOnly,
> +  /// There are separate data and instruction caches
> +  ClidrCacheTypeSeparate,
> +  /// There is a unified cache
> +  ClidrCacheTypeUnified,
> +  ClidrCacheTypeMax
> +} CLIDR_CACHE_TYPE;
> +
> +#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * level)) & 0b111)
> +
>  VOID
>  CPSRMaskInsert (
>    IN  UINT32  Mask,
> -- 
> 2.26.2
>