From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by mx.groups.io with SMTP id smtpd.web11.997.1608060457630232846 for ; Tue, 15 Dec 2020 11:27:37 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=nTmLW5qd; spf=pass (domain: nuviainc.com, ip: 209.85.128.67, mailfrom: leif@nuviainc.com) Received: by mail-wm1-f67.google.com with SMTP id g185so300071wmf.3 for ; Tue, 15 Dec 2020 11:27:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=+5/mQgNaDZ9MlNzgh2iGR4ZZobk44v7BXzVOsUWvz7k=; b=nTmLW5qduUGTPdcwecNoTGuNgrrHdYBU1AMsy+1AD29ZhQeiLjdI2LhVmzpyrhUx/E XEGRdwwTdqEkxot+z/1Jpndu27E0rTQ/aMHKwB8+sbRV0ahwTjNkocVZ9CAmpuVwjfKW sFTRG2izMAflnOKkTSf7eFPuD0B/XnbkvqL8xM5ZJbbr+B6/Zf1jSH3fJ8m8okZllJvU Jz7saZaEvUhouPD0AAYr6k6OmksykervftW3/O49CLifdIXzxAvxfeupI+keSpgvo5pf urUDq7L6jh/1i5Gs3AcJoHHUMWqLcnHJRGDyH8EWBfdR2b4OZVRS97uu8IKXG7H+FIWR PN+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=+5/mQgNaDZ9MlNzgh2iGR4ZZobk44v7BXzVOsUWvz7k=; b=JyYHCVdDuJeJWcnE4kEfsQg1Ay+R9TMpW+q1ilkDSlYMX0ZAACExJmEytmfn+6JxYs S8pszPLxSEMaPX05KEcoSWy+NG+aqJFeM3POC7NlCW3zltVSKlMeISg7yW+VUqBkhFw6 bYIPOhVeEwF+XngugVZ9p2rr5xXluQ0Iu7O6iRWAVEOhfuaNrZrSKU5Di41XpTh5Mfon PGvOaNcFQElchnZcPmpHNJwoiwgq9XqDEM+q9KHpwn+/qAhNaguVRzNOLmveYa8/ngHN 7wrhyo2dahv9hOAcpDXsbk2KvCFjXAwdb5dYHnXAhOqeJRwoqSoCgTLkaWUIunyFIwmT Tdkw== X-Gm-Message-State: AOAM533d4E89wkfcy/5idyGkPcQqh9felVtvXlaE+zd8hVmf2kwQJ6aP VF2AW5UIQ0yYQcMpTH+hU4HhWQ== X-Google-Smtp-Source: ABdhPJxxUpp+Isk6474kzox47smq9v53v01JLASogVHaHsB+gz82w2byrrTJkQgpPKjNKDsHSALndw== X-Received: by 2002:a1c:1dd4:: with SMTP id d203mr416252wmd.118.1608060456092; Tue, 15 Dec 2020 11:27:36 -0800 (PST) Return-Path: Received: from vanye (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id f9sm40918893wrw.81.2020.12.15.11.27.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 11:27:35 -0800 (PST) Date: Tue, 15 Dec 2020 19:27:33 +0000 From: "Leif Lindholm" To: Rebecca Cran Cc: devel@edk2.groups.io, Michael D Kinney , Liming Gao , Zhiguang Liu , Ard Biesheuvel Subject: Re: [PATCH v4 08/10] ArmPkg: Update ArmLibPrivate.h with cache register definitions Message-ID: <20201215192733.GF1664@vanye> References: <20201207175427.28712-1-rebecca@nuviainc.com> <20201207175427.28712-9-rebecca@nuviainc.com> MIME-Version: 1.0 In-Reply-To: <20201207175427.28712-9-rebecca@nuviainc.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Dec 07, 2020 at 10:54:25 -0700, Rebecca Cran wrote: > Update the cache definitions in ArmLibPrivate.h based on current > ARMv8 documentation. > > Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm > --- > ArmPkg/Library/ArmLib/ArmLibPrivate.h | 91 ++++++++++++++++++++ > 1 file changed, 91 insertions(+) > > diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h > index 5eecbc0e1c43..fb1e2cc6b2ac 100644 > --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h > +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h > @@ -1,5 +1,7 @@ > /** @file > + ArmLibPrivate.h > > + Copyright (c) 2020, NUVIA Inc. All rights reserved.
> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > @@ -50,6 +52,95 @@ > #define CACHE_ARCHITECTURE_UNIFIED (0UL) > #define CACHE_ARCHITECTURE_SEPARATE (1UL) > > + > +/// Defines the structure of the CSSELR (Cache Size Selection) register > +typedef union { > + struct { > + UINT32 InD :1; ///< Instruction not Data bit > + UINT32 Level :3; ///< Cache level (zero based) > + UINT32 TnD :1; ///< Allocation not Data bit > + UINT32 Reserved :27; ///< Reserved, RES0 > + } Bits; ///< Bitfield definition of the register > + UINT32 Data; ///< The entire 32-bit value > +} CSSELR_DATA; > + > +/// The cache type values for the InD field of the CSSELR register > +typedef enum > +{ > + /// Select the data or unified cache > + CsselrCacheTypeDataOrUnified = 0, > + /// Select the instruction cache > + CsselrCacheTypeInstruction, > + CsselrCacheTypeMax > +} CSSELR_CACHE_TYPE; > + > +/// Defines the structure of the CCSIDR (Current Cache Size ID) register > +typedef union { > + struct { > + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) > + UINT64 Associativity :10; ///< Associativity - 1 > + UINT64 NumSets :15; ///< Number of sets in the cache -1 > + UINT64 Unknown :4; ///< Reserved, UNKNOWN > + UINT64 Reserved :32; ///< Reserved, RES0 > + } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported. > + struct { > + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) > + UINT64 Associativity :21; ///< Associativity - 1 > + UINT64 Reserved1 :8; ///< Reserved, RES0 > + UINT64 NumSets :24; ///< Number of sets in the cache -1 > + UINT64 Reserved2 :8; ///< Reserved, RES0 > + } BitsCcidx; ///< Bitfield definition of the register when FEAT_IDX is supported. > + UINT64 Data; ///< The entire 64-bit value > +} CCSIDR_DATA; > + > +/// Defines the structure of the AARCH32 CCSIDR2 register. > +typedef union { > + struct { > + UINT32 NumSets :24; ///< Number of sets in the cache - 1 > + UINT32 Reserved :8; ///< Reserved, RES0 > + } Bits; ///< Bitfield definition of the register > + UINT32 Data; ///< The entire 32-bit value > +} CSSIDR2_DATA; > + > +/** Defines the structure of the CLIDR (Cache Level ID) register. > + * > + * The lower 32 bits are the same for both AARCH32 and AARCH64 > + * so we can use the same structure for both. > +**/ > +typedef union { > + struct { > + UINT32 Ctype1 : 3; ///< Level 1 cache type > + UINT32 Ctype2 : 3; ///< Level 2 cache type > + UINT32 Ctype3 : 3; ///< Level 3 cache type > + UINT32 Ctype4 : 3; ///< Level 4 cache type > + UINT32 Ctype5 : 3; ///< Level 5 cache type > + UINT32 Ctype6 : 3; ///< Level 6 cache type > + UINT32 Ctype7 : 3; ///< Level 7 cache type > + UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable > + UINT32 LoC : 3; ///< Level of Coherency > + UINT32 LoUU : 3; ///< Level of Unification Uniprocessor > + UINT32 Icb : 3; ///< Inner Cache Boundary > + } Bits; ///< Bitfield definition of the register > + UINT32 Data; ///< The entire 32-bit value > +} CLIDR_DATA; > + > +/// The cache types reported in the CLIDR register. > +typedef enum { > + /// No cache is present > + ClidrCacheTypeNone = 0, > + /// There is only an instruction cache > + ClidrCacheTypeInstructionOnly, > + /// There is only a data cache > + ClidrCacheTypeDataOnly, > + /// There are separate data and instruction caches > + ClidrCacheTypeSeparate, > + /// There is a unified cache > + ClidrCacheTypeUnified, > + ClidrCacheTypeMax > +} CLIDR_CACHE_TYPE; > + > +#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * level)) & 0b111) > + > VOID > CPSRMaskInsert ( > IN UINT32 Mask, > -- > 2.26.2 >