From: "Quan Nguyen" <quan@os.amperecomputing.com>
To: devel@edk2.groups.io
Cc: Leif Lindholm <leif@nuviainc.com>,
Ard Biesheuvel <ard.biesheuvel@arm.com>,
Victor Gallardo <Victor@os.amperecomputing.com>,
Open Source Submission <patches@amperecomputing.com>,
Quan Nguyen <quan@os.amperecomputing.com>
Subject: [PATCH v2 1/2] ArmPkg/ArmGicLib: Add ArmGicSetInterruptPriority() helper function
Date: Wed, 16 Dec 2020 20:25:20 +0700 [thread overview]
Message-ID: <20201216132521.5915-2-quan@os.amperecomputing.com> (raw)
In-Reply-To: <20201216132521.5915-1-quan@os.amperecomputing.com>
According to ARM IHI 0069F, section 11.9.18 GICD_IPRIORITYR<n>,
Interrupt Priority Registers, n = 0 - 254, when affinity routing is
enabled for the Security state of an interrupt, GICR_IPRIORITYR<n>
is used instead of GICD_IPRIORITYR<n> where n = 0 to 7 (that is, for
SGIs and PPIs).
As setting interrupt priority for SGIs and PPIs are handled using
difference registers depends on the mode, this patch instroduces
ArmGicSetInterruptPriority() helper function to handle the discrepancy.
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com>
---
ArmPkg/Drivers/ArmGic/ArmGicLib.c | 44 ++++++++++++++++++++++++++++++
ArmPkg/Include/Library/ArmGicLib.h | 9 ++++++
2 files changed, 53 insertions(+)
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 001e6b143104..8ef32b33a154 100644
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -199,6 +199,50 @@ ArmGicEndOfInterrupt (
}
}
+VOID
+EFIAPI
+ArmGicSetInterruptPriority (
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source,
+ IN UINTN Priority
+ )
+{
+ UINT32 RegOffset;
+ UINTN RegShift;
+ ARM_GIC_ARCH_REVISION Revision;
+ UINTN GicCpuRedistributorBase;
+
+ // Calculate register offset and bit position
+ RegOffset = Source / 4;
+ RegShift = (Source % 4) * 8;
+
+ Revision = ArmGicGetSupportedArchRevision ();
+ if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
+ FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
+ SourceIsSpi (Source)) {
+ MmioAndThenOr32 (
+ GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
+ ~(0xff << RegShift),
+ Priority << RegShift
+ );
+ } else {
+ GicCpuRedistributorBase = GicGetCpuRedistributorBase (
+ GicRedistributorBase,
+ Revision
+ );
+ if (GicCpuRedistributorBase == 0) {
+ return;
+ }
+
+ MmioAndThenOr32 (
+ GicCpuRedistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
+ ~(0xff << RegShift),
+ Priority << RegShift
+ );
+ }
+}
+
VOID
EFIAPI
ArmGicEnableInterrupt (
diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index 55093189638b..7bcfc001115b 100644
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -208,6 +208,15 @@ ArmGicSetPriorityMask (
IN INTN PriorityMask
);
+VOID
+EFIAPI
+ArmGicSetInterruptPriority (
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source,
+ IN UINTN Priority
+ );
+
VOID
EFIAPI
ArmGicEnableInterrupt (
--
2.28.0
next prev parent reply other threads:[~2020-12-16 13:26 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-16 13:25 [PATCH v2 0/2] ArmPkg/ArmGicV3Dxe: fix writes to GICD_IPRIORITYR<n> when ARE enable Quan Nguyen
2020-12-16 13:25 ` Quan Nguyen [this message]
2020-12-16 13:25 ` [PATCH v2 2/2] ArmPkg/ArmGicV3Dxe: Use ArmGicSetInterruptPriority() to set priority Quan Nguyen
2020-12-18 18:23 ` [PATCH v2 0/2] ArmPkg/ArmGicV3Dxe: fix writes to GICD_IPRIORITYR<n> when ARE enable Ard Biesheuvel
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