From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.53.1608139347071405895 for ; Wed, 16 Dec 2020 09:22:27 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pierre.gondois@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BF0541FB; Wed, 16 Dec 2020 09:22:26 -0800 (PST) Received: from e120189.arm.com (unknown [10.57.25.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9CE5E3F66E; Wed, 16 Dec 2020 09:22:25 -0800 (PST) From: "PierreGondois" To: devel@edk2.groups.io, ard.biesheuvel@arm.com, leif@nuviainc.com Cc: sami.mujawar@arm.com Subject: [PATCH v1 04/25] ArmPkg: Fix Ecc error 3002 in ArmMmuLib Date: Wed, 16 Dec 2020 17:21:39 +0000 Message-Id: <20201216172200.25846-5-Pierre.Gondois@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201216172200.25846-1-Pierre.Gondois@arm.com> References: <20201216172200.25846-1-Pierre.Gondois@arm.com> From: Pierre Gondois This patch fixes the following Ecc reported error: Non-Boolean comparisons should use a compare operator (==, !=, >, < >=, <=) Signed-off-by: Pierre Gondois --- The changes can be seen at: https://github.com/PierreARM/edk2/commits/1552_Ecc_ArmPkg_v1 .../Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 2 +- .../Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c | 30 +++++++++---------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 513a763e6e87..8c736d25bb80 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -294,7 +294,7 @@ UpdateRegionMapping ( { UINTN T0SZ; - if (((RegionStart | RegionLength) & EFI_PAGE_MASK)) { + if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) { return EFI_INVALID_PARAMETER; } diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c index 6f18604f799f..c7f2744c4fac 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c @@ -1,7 +1,7 @@ /** @file * File managing the MMU for ARMv7 architecture * -* Copyright (c) 2011-2016, ARM Limited. All rights reserved. +* Copyright (c) 2011-2020, Arm Limited. All rights reserved.
* * SPDX-License-Identifier: BSD-2-Clause-Patent * @@ -105,7 +105,7 @@ UpdatePageEntries ( // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone) // EntryValue: values at bit positions specified by EntryMask EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK; - if (Attributes & EFI_MEMORY_XP) { + if ((Attributes & EFI_MEMORY_XP) != 0) { EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN; } else { EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE; @@ -116,33 +116,33 @@ UpdatePageEntries ( // is irrelevant. If no memory attribute is specified, we preserve whatever // memory type is set in the page tables, and update the permission attributes // only. - if (Attributes & EFI_MEMORY_UC) { + if ((Attributes & EFI_MEMORY_UC) != 0) { // modify cacheability attributes EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; // map to strongly ordered EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 - } else if (Attributes & EFI_MEMORY_WC) { + } else if ((Attributes & EFI_MEMORY_WC) != 0) { // modify cacheability attributes EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; // map to normal non-cachable EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 - } else if (Attributes & EFI_MEMORY_WT) { + } else if ((Attributes & EFI_MEMORY_WT) != 0) { // modify cacheability attributes EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; // write through with no-allocate EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 - } else if (Attributes & EFI_MEMORY_WB) { + } else if ((Attributes & EFI_MEMORY_WB) != 0) { // modify cacheability attributes EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; // write back (with allocate) EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 - } else if (Attributes & CACHE_ATTRIBUTE_MASK) { + } else if ((Attributes & CACHE_ATTRIBUTE_MASK) != 0) { // catch unsupported memory type attributes ASSERT (FALSE); return EFI_UNSUPPORTED; } - if (Attributes & EFI_MEMORY_RO) { + if ((Attributes & EFI_MEMORY_RO) != 0) { EntryValue |= TT_DESCRIPTOR_PAGE_AP_RO_RO; } else { EntryValue |= TT_DESCRIPTOR_PAGE_AP_RW_RW; @@ -244,39 +244,39 @@ UpdateSectionEntries ( // is irrelevant. If no memory attribute is specified, we preserve whatever // memory type is set in the page tables, and update the permission attributes // only. - if (Attributes & EFI_MEMORY_UC) { + if ((Attributes & EFI_MEMORY_UC) != 0) { // modify cacheability attributes EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; // map to strongly ordered EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 - } else if (Attributes & EFI_MEMORY_WC) { + } else if ((Attributes & EFI_MEMORY_WC) != 0) { // modify cacheability attributes EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; // map to normal non-cachable EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 - } else if (Attributes & EFI_MEMORY_WT) { + } else if ((Attributes & EFI_MEMORY_WT) != 0) { // modify cacheability attributes EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; // write through with no-allocate EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 - } else if (Attributes & EFI_MEMORY_WB) { + } else if ((Attributes & EFI_MEMORY_WB) != 0) { // modify cacheability attributes EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; // write back (with allocate) EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 - } else if (Attributes & CACHE_ATTRIBUTE_MASK) { + } else if ((Attributes & CACHE_ATTRIBUTE_MASK) != 0) { // catch unsupported memory type attributes ASSERT (FALSE); return EFI_UNSUPPORTED; } - if (Attributes & EFI_MEMORY_RO) { + if ((Attributes & EFI_MEMORY_RO) != 0) { EntryValue |= TT_DESCRIPTOR_SECTION_AP_RO_RO; } else { EntryValue |= TT_DESCRIPTOR_SECTION_AP_RW_RW; } - if (Attributes & EFI_MEMORY_XP) { + if ((Attributes & EFI_MEMORY_XP) != 0) { EntryValue |= TT_DESCRIPTOR_SECTION_XN_MASK; } -- 2.17.1