* [PATCH][edk2-platforms 1/5] Platform/ARM/SgiPkg: Use PCD for base addresses
2020-12-18 14:07 [PATCH][edk2-platforms 0/5] Add support for RD-N2 platform Aditya Angadi
@ 2020-12-18 14:07 ` Aditya Angadi
2020-12-18 14:07 ` [PATCH][edk2-platforms 2/5] Platform/ARM/SgiPkg: remove the use of SMSC Lan91x controller Aditya Angadi
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Aditya Angadi @ 2020-12-18 14:07 UTC (permalink / raw)
To: devel
Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Thomas Abraham,
Vijayenthiran Subramaniam, Aditya Angadi
Certain base addresses have been specified using macros. But the
upcoming derivative platforms that have to be supported under the
SgiPkg have changes in some of those base addresses and so these
macros are not applicable on those upcoming platforms.
So convert the affected macros into PCDs and let the platform
description file choose the appropriate set of PCDs that is
applicable for the platform. In addition to this, use the PCDs
to replace existing uses of the macros that have been converted
into PCDs.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/SsdtRos.asl | 2 +-
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 32 -------------
Platform/ARM/SgiPkg/Library/NorFlashLib/NorFlashLib.c | 12 ++---
Platform/ARM/SgiPkg/Library/NorFlashLib/NorFlashLib.inf | 7 ++-
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 9 ++++
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 34 +++++++-------
Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc | 1 +
Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc | 1 +
Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc | 1 +
Platform/ARM/SgiPkg/RdV1/RdV1.dsc | 1 +
Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc | 1 +
Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc | 1 +
Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc | 49 ++++++++++++++++++++
Platform/ARM/SgiPkg/SgiPlatform.dec | 5 ++
Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 20 --------
15 files changed, 100 insertions(+), 76 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/SsdtRos.asl b/Platform/ARM/SgiPkg/AcpiTables/SsdtRos.asl
index 458a711cfd31..55a8ed04d5aa 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/SsdtRos.asl
+++ b/Platform/ARM/SgiPkg/AcpiTables/SsdtRos.asl
@@ -25,7 +25,7 @@ DefinitionBlock ("SsdtRosTable.aml", "SSDT", 1, "ARMLTD", "ARMSGI",
FixedPcdGet64 (PcdSerialDbgRegisterBase),
0x1000
)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 147 }
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { FixedPcdGet32 (PL011UartInterrupt) }
})
}
diff --git a/Platform/ARM/SgiPkg/Include/SgiPlatform.h b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
index f5174c12b89a..d6ab585cce80 100644
--- a/Platform/ARM/SgiPkg/Include/SgiPlatform.h
+++ b/Platform/ARM/SgiPkg/Include/SgiPlatform.h
@@ -13,26 +13,6 @@
// Platform Memory Map
************************************************************************************/
-// Expansion AXI - SMC Chip Select 0
-#define SGI_EXP_SMC_CS0_BASE 0x08000000
-#define SGI_EXP_SMC_CS0_SZ SIZE_64MB
-
-// Expansion AXI - SMC Chip Select 1
-#define SGI_EXP_SMC_CS1_BASE 0x0C000000
-#define SGI_EXP_SMC_CS1_SZ SIZE_64MB
-
-// Expansion AXI - SMSC 91C111 (Ethernet)
-#define SGI_EXP_SMSC91X_BASE 0x18000000
-#define SGI_EXP_SMSC91X_SZ SIZE_64MB
-
-// Expansion AXI - System peripherals
-#define SGI_EXP_SYS_PERIPH_BASE 0x1C000000
-#define SGI_EXP_SYS_PERIPH_SZ SIZE_2MB
-
-// Base address of system peripherals
-#define SGI_EXP_SYSPH_SYSTEM_REGISTERS 0x1C010000
-#define SGI_EXP_SYSPH_VIRTIO_BLOCK_BASE 0x1C130000
-
// Sub System Peripherals - UART0
#define SGI_SUBSYS_UART0_BASE 0x2A400000
#define SGI_SUBSYS_UART0_SZ 0x00010000
@@ -45,18 +25,6 @@
#define SGI_SUBSYS_GENERIC_WDOG_BASE 0x2A440000
#define SGI_SUBSYS_GENERIC_WDOG_SZ SIZE_128KB
-// Expansion AXI - Platform Peripherals - HDLCD1
-#define SGI_EXP_PLAT_PERIPH_HDLCD1_BASE 0x7FF60000
-#define SGI_EXP_PLAT_PERIPH_HDLCD1_SZ SIZE_64KB
-
-// Expansion AXI - Platform Peripherals - UART0
-#define SGI_EXP_PLAT_PERIPH_UART0_BASE 0x7FF70000
-#define SGI_EXP_PLAT_PERIPH_UART0_SZ SIZE_64KB
-
-// Expansion AXI - Platform Peripherals - UART1
-#define SGI_EXP_PLAT_PERIPH_UART1_BASE 0x7FF80000
-#define SGI_EXP_PLAT_PERIPH_UART1_SZ SIZE_64KB
-
// Register offsets into the System Registers Block
#define SGI_SYSPH_SYS_REG_FLASH 0x4C
#define SGI_SYSPH_SYS_REG_FLASH_RWEN 0x1
diff --git a/Platform/ARM/SgiPkg/Library/NorFlashLib/NorFlashLib.c b/Platform/ARM/SgiPkg/Library/NorFlashLib/NorFlashLib.c
index e3bf2726b557..b5dfae28d10a 100644
--- a/Platform/ARM/SgiPkg/Library/NorFlashLib/NorFlashLib.c
+++ b/Platform/ARM/SgiPkg/Library/NorFlashLib/NorFlashLib.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2018, ARM Ltd. All rights reserved.
+ Copyright (c) 2020, ARM Ltd. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -14,14 +14,14 @@
STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {
{
- SGI_EXP_SMC_CS0_BASE,
- SGI_EXP_SMC_CS0_BASE,
+ FixedPcdGet64 (PcdSmcCs0Base),
+ FixedPcdGet64 (PcdSmcCs0Base),
SIZE_256KB * 256,
SIZE_256KB,
},
{
- SGI_EXP_SMC_CS1_BASE,
- SGI_EXP_SMC_CS1_BASE,
+ FixedPcdGet64 (PcdSmcCs1Base),
+ FixedPcdGet64 (PcdSmcCs1Base),
SIZE_256KB * 256,
SIZE_256KB,
},
@@ -34,7 +34,7 @@ NorFlashPlatformInitialization (
{
UINT64 SysRegFlash;
- SysRegFlash = SGI_EXP_SYSPH_SYSTEM_REGISTERS + SGI_SYSPH_SYS_REG_FLASH;
+ SysRegFlash = FixedPcdGet64 (PcdSysPeriphSysRegBase) + SGI_SYSPH_SYS_REG_FLASH;
MmioOr32 (SysRegFlash, SGI_SYSPH_SYS_REG_FLASH_RWEN);
return EFI_SUCCESS;
}
diff --git a/Platform/ARM/SgiPkg/Library/NorFlashLib/NorFlashLib.inf b/Platform/ARM/SgiPkg/Library/NorFlashLib/NorFlashLib.inf
index a1439c10d1fa..74486eacd009 100644
--- a/Platform/ARM/SgiPkg/Library/NorFlashLib/NorFlashLib.inf
+++ b/Platform/ARM/SgiPkg/Library/NorFlashLib/NorFlashLib.inf
@@ -1,6 +1,6 @@
#/** @file
#
-# Copyright (c) 2018, ARM Ltd. All rights reserved.
+# Copyright (c) 2020, ARM Ltd. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -26,3 +26,8 @@ [LibraryClasses]
BaseLib
DebugLib
IoLib
+
+[FixedPcd]
+ gArmSgiTokenSpaceGuid.PcdSysPeriphSysRegBase
+ gArmSgiTokenSpaceGuid.PcdSmcCs0Base
+ gArmSgiTokenSpaceGuid.PcdSmcCs1Base
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
index 464a7cde4513..2ed0ff1fb62e 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
@@ -19,6 +19,7 @@ [Packages]
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
Platform/ARM/SgiPkg/SgiPlatform.dec
+ Platform/ARM/VExpressPkg/ArmVExpressPkg.dec
StandaloneMmPkg/StandaloneMmPkg.dec
[LibraryClasses]
@@ -39,6 +40,7 @@ [Sources.AARCH64]
[FixedPcd]
gArmPlatformTokenSpaceGuid.PcdClusterCount
gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase
gArmSgiTokenSpaceGuid.PcdDramBlock2Base
gArmSgiTokenSpaceGuid.PcdDramBlock2Size
@@ -63,8 +65,15 @@ [FixedPcd]
gArmTokenSpaceGuid.PcdMmBufferBase
gArmTokenSpaceGuid.PcdMmBufferSize
+ gArmSgiTokenSpaceGuid.PcdSmcCs0Base
+ gArmSgiTokenSpaceGuid.PcdSmcCs1Base
+ gArmSgiTokenSpaceGuid.PcdSysPeriphBase
+
+ gArmVExpressTokenSpaceGuid.PcdLan91xDxeBaseAddress
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
[Guids]
gArmSgiPlatformIdDescriptorGuid
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
index e30819c5cd55..ecca91e0f51b 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
@@ -106,27 +106,29 @@ ArmPlatformGetVirtualMemoryMap (
}
// Expansion AXI - SMC Chip Select 0 (NOR Flash)
- VirtualMemoryTable[Index].PhysicalBase = SGI_EXP_SMC_CS0_BASE;
- VirtualMemoryTable[Index].VirtualBase = SGI_EXP_SMC_CS0_BASE;
+ VirtualMemoryTable[Index].PhysicalBase = FixedPcdGet64 (PcdSmcCs0Base);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSmcCs0Base);
VirtualMemoryTable[Index].Length = SIZE_64MB;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// Expansion AXI - SMC Chip Select 1 (NOR Flash)
- VirtualMemoryTable[++Index].PhysicalBase = SGI_EXP_SMC_CS1_BASE;
- VirtualMemoryTable[Index].VirtualBase = SGI_EXP_SMC_CS1_BASE;
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdSmcCs1Base);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSmcCs1Base);
VirtualMemoryTable[Index].Length = SIZE_64MB;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+#if defined (EDK2_ENABLE_SMSC_91X)
// Expansion AXI - SMSC 91X (Ethernet)
- VirtualMemoryTable[++Index].PhysicalBase = SGI_EXP_SMSC91X_BASE;
- VirtualMemoryTable[Index].VirtualBase = SGI_EXP_SMSC91X_BASE;
- VirtualMemoryTable[Index].Length = SGI_EXP_SMSC91X_SZ;
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet32 (PcdLan91xDxeBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet32 (PcdLan91xDxeBaseAddress);
+ VirtualMemoryTable[Index].Length = SIZE_64MB;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+#endif
// Expansion AXI - System Peripherals
- VirtualMemoryTable[++Index].PhysicalBase = SGI_EXP_SYS_PERIPH_BASE;
- VirtualMemoryTable[Index].VirtualBase = SGI_EXP_SYS_PERIPH_BASE;
- VirtualMemoryTable[Index].Length = SGI_EXP_SYS_PERIPH_SZ;
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdSysPeriphBase);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSysPeriphBase);
+ VirtualMemoryTable[Index].Length = SIZE_32MB;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// Sub System Peripherals - Generic Watchdog
@@ -142,15 +144,15 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// Expansion AXI - Platform Peripherals - HDLCD1
- VirtualMemoryTable[++Index].PhysicalBase = SGI_EXP_PLAT_PERIPH_HDLCD1_BASE;
- VirtualMemoryTable[Index].VirtualBase = SGI_EXP_PLAT_PERIPH_HDLCD1_BASE;
- VirtualMemoryTable[Index].Length = SGI_EXP_PLAT_PERIPH_HDLCD1_SZ;
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet32 (PcdArmHdLcdBase);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet32 (PcdArmHdLcdBase);
+ VirtualMemoryTable[Index].Length = SIZE_64KB;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// Expansion AXI - Platform Peripherals - UART1
- VirtualMemoryTable[++Index].PhysicalBase = SGI_EXP_PLAT_PERIPH_UART1_BASE;
- VirtualMemoryTable[Index].VirtualBase = SGI_EXP_PLAT_PERIPH_UART1_BASE;
- VirtualMemoryTable[Index].Length = SGI_EXP_PLAT_PERIPH_UART1_SZ;
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdSerialRegisterBase);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdSerialRegisterBase);
+ VirtualMemoryTable[Index].Length = SIZE_64KB;
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
// DDR - (2GB - 16MB)
diff --git a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc
index a108b4eab0d8..26ab7e6ef6b8 100644
--- a/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc
+++ b/Platform/ARM/SgiPkg/RdE1Edge/RdE1Edge.dsc
@@ -24,6 +24,7 @@ [Defines]
# include common definitions from SgiPlatform.dsc
!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
################################################################################
#
diff --git a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc
index a59a6c5b8f3a..7d397438bfff 100644
--- a/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc
+++ b/Platform/ARM/SgiPkg/RdN1Edge/RdN1Edge.dsc
@@ -24,6 +24,7 @@ [Defines]
# include common definitions from SgiPlatform.dsc
!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
################################################################################
#
diff --git a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
index 1cb41d119e3e..5c87a0ca9b3c 100644
--- a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
+++ b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
@@ -24,6 +24,7 @@ [Defines]
# include common definitions from SgiPlatform.dsc
!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
################################################################################
#
diff --git a/Platform/ARM/SgiPkg/RdV1/RdV1.dsc b/Platform/ARM/SgiPkg/RdV1/RdV1.dsc
index 223f4815c122..e8ee0e8769a8 100644
--- a/Platform/ARM/SgiPkg/RdV1/RdV1.dsc
+++ b/Platform/ARM/SgiPkg/RdV1/RdV1.dsc
@@ -24,6 +24,7 @@ [Defines]
# include common definitions from SgiPlatform.dsc
!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
################################################################################
#
diff --git a/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc b/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc
index f138d4c43885..c2fcc0df4571 100644
--- a/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc
+++ b/Platform/ARM/SgiPkg/RdV1Mc/RdV1Mc.dsc
@@ -24,6 +24,7 @@ [Defines]
# include common definitions from SgiPlatform.dsc
!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
################################################################################
#
diff --git a/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc b/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc
index 60e2a88bb591..a8675368415b 100644
--- a/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc
+++ b/Platform/ARM/SgiPkg/Sgi575/Sgi575.dsc
@@ -24,6 +24,7 @@ [Defines]
# include common definitions from SgiPlatform.dsc
!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
################################################################################
#
diff --git a/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
new file mode 100644
index 000000000000..2549c3129b0f
--- /dev/null
+++ b/Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
@@ -0,0 +1,49 @@
+#
+# Copyright (c) 2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+[PcdsFixedAtBuild.common]
+ # System Peripherals
+ gArmSgiTokenSpaceGuid.PcdSmcCs0Base|0x08000000
+ gArmSgiTokenSpaceGuid.PcdSmcCs1Base|0x0C000000
+ gArmSgiTokenSpaceGuid.PcdSysPeriphBase|0x1C000000
+ gArmSgiTokenSpaceGuid.PcdSysPeriphSysRegBase|0x1C010000
+
+ # Non-Volatile variable storage
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0x0C000000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0x0D400000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0x0E800000
+
+ # PL011 - Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000
+
+ # PL370 - HDLCD1
+ gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x7FF60000
+
+ # PL011 - Serial Debug UART
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x7FF80000
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt|147
+
+ # PL031 RealTimeClock
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
+
+ # Virtio Disk
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x1C130000
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkSize|0x10000
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt|202
+
+ # Ethernet
+!ifdef EDK2_ENABLE_SMSC_91X
+ gArmVExpressTokenSpaceGuid.PcdLan91xDxeBaseAddress|0x18000000
+!endif
+ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress|0x1C150000
+ gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|204
+
+ # PCIe
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x70000000
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x07800000
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x5000000000
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x3000000000
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x60000000
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/SgiPlatform.dec
index dac7fdc308b1..3f0d38a013f2 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -52,5 +52,10 @@ [PcdsFixedAtBuild]
# GIC
gArmSgiTokenSpaceGuid.PcdGicSize|0|UINT64|0x0000000A
+ gArmSgiTokenSpaceGuid.PcdSmcCs0Base|0|UINT64|0x0000000C
+ gArmSgiTokenSpaceGuid.PcdSmcCs1Base|0|UINT64|0x0000000D
+ gArmSgiTokenSpaceGuid.PcdSysPeriphBase|0x00000000|UINT64|0x0000000E
+ gArmSgiTokenSpaceGuid.PcdSysPeriphSysRegBase|0x0|UINT64|0x0000000F
+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0x6f606eb3, 0x9123, 0x4e15, { 0xa8, 0x9b, 0x0f, 0xac, 0x66, 0xef, 0xd0, 0x17 } }
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
index f5f9f144eee9..2beab1f07278 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -93,11 +93,8 @@ [PcdsFixedAtBuild.common]
gArmSgiTokenSpaceGuid.PcdDramBlock2Size|0x180000000
# NV Storage PCDs. Use base of 0x08000000 for NOR0, 0xC0000000 for NOR 1
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0C000000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x01400000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0D400000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x01400000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0E800000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x01400000
# Stacks for MPCores in Normal World
@@ -117,17 +114,11 @@ [PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdPciIoBase|0x0
gArmTokenSpaceGuid.PcdPciIoSize|0x00800000
gArmTokenSpaceGuid.PcdPciIoTranslation|0x77800000
- gArmTokenSpaceGuid.PcdPciMmio32Base|0x70000000
- gArmTokenSpaceGuid.PcdPciMmio32Size|0x07800000
gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
- gArmTokenSpaceGuid.PcdPciMmio64Base|0x500000000
- gArmTokenSpaceGuid.PcdPciMmio64Size|0x300000000
gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x60000000
gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
## PL011 - Serial Terminal
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
gArmPlatformTokenSpaceGuid.PL011UartInteger|4
@@ -137,13 +128,9 @@ [PcdsFixedAtBuild.common]
gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x7FF60000
## PL011 - Serial Debug UART
- gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x7FF80000
gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|7372800
gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200
- gArmPlatformTokenSpaceGuid.PL011UartInterrupt|147
- ## PL031 RealTimeClock
- gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
# List of Device Paths that support BootMonFs
gArmBootMonFsTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L"VenHw(93E34C7E-B50E-11DF-9223-2443DFD72085,00)"
@@ -157,17 +144,10 @@ [PcdsFixedAtBuild.common]
gEmbeddedTokenSpaceGuid.PcdTimerPeriod|1000
# Virtio Disk
- gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress|0x1c130000
gArmSgiTokenSpaceGuid.PcdVirtioBlkSize|0x10000
- gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt|202
# Ethernet / Virtio Network
-!ifdef EDK2_ENABLE_SMSC_91X
- gArmVExpressTokenSpaceGuid.PcdLan91xDxeBaseAddress|0x18000000
-!endif
- gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress|0x1c150000
gArmSgiTokenSpaceGuid.PcdVirtioNetSize|0x10000
- gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt|204
#
# Set the base address and size of the buffer used
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH][edk2-platforms 4/5] Platform/ARM/SgiPkg: Add ACPI tables for RD-N2 platform
2020-12-18 14:07 [PATCH][edk2-platforms 0/5] Add support for RD-N2 platform Aditya Angadi
` (2 preceding siblings ...)
2020-12-18 14:07 ` [PATCH][edk2-platforms 3/5] Platform/ARM/SgiPkg: Define base address PCD for derivative platforms Aditya Angadi
@ 2020-12-18 14:07 ` Aditya Angadi
2020-12-18 14:07 ` [PATCH][edk2-platforms 5/5] Platform/ARM/SgiPkg: Add initial support " Aditya Angadi
2021-01-04 17:48 ` [PATCH][edk2-platforms 0/5] Add " Ard Biesheuvel
5 siblings, 0 replies; 7+ messages in thread
From: Aditya Angadi @ 2020-12-18 14:07 UTC (permalink / raw)
To: devel
Cc: Leif Lindholm, Ard Biesheuvel, Sami Mujawar, Thomas Abraham,
Vijayenthiran Subramaniam, Aditya Angadi
Add Madt and Dsdt ACPI tables that are specific for RD-N2 platform.
Reuse the rest of the shared ACPI tables in SgiPkg.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl | 112 ++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc | 137 ++++++++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 60 +++++++++
3 files changed, 309 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
new file mode 100644
index 000000000000..8688fd8d6b90
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Dsdt.asl
@@ -0,0 +1,112 @@
+/** @file
+* Differentiated System Description Table Fields (DSDT)
+*
+* Copyright (c) 2020, Arm Ltd. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARMSGI",
+ EFI_ACPI_ARM_OEM_REVISION) {
+ Scope (_SB) {
+ Device (CP00) { // Neoverse N2 core 0
+ Name (_HID, "ACPI0007")
+ Name (_UID, 0)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP01) { // Neoverse N2 core 1
+ Name (_HID, "ACPI0007")
+ Name (_UID, 1)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP02) { // Neoverse N2 core 2
+ Name (_HID, "ACPI0007")
+ Name (_UID, 2)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP03) { // Neoverse N2 core 3
+ Name (_HID, "ACPI0007")
+ Name (_UID, 3)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP04) { // Neoverse N2 core 4
+ Name (_HID, "ACPI0007")
+ Name (_UID, 4)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP05) { // Neoverse N2 core 5
+ Name (_HID, "ACPI0007")
+ Name (_UID, 5)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP06) { // Neoverse N2 core 6
+ Name (_HID, "ACPI0007")
+ Name (_UID, 6)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP07) { // Neoverse N2 core 7
+ Name (_HID, "ACPI0007")
+ Name (_UID, 7)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP08) { // Neoverse N2 core 8
+ Name (_HID, "ACPI0007")
+ Name (_UID, 8)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP09) { // Neoverse N2 core 9
+ Name (_HID, "ACPI0007")
+ Name (_UID, 9)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP10) { // Neoverse N2 core 10
+ Name (_HID, "ACPI0007")
+ Name (_UID, 10)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP11) { // Neoverse N2 core 11
+ Name (_HID, "ACPI0007")
+ Name (_UID, 11)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP12) { // Neoverse N2 core 12
+ Name (_HID, "ACPI0007")
+ Name (_UID, 12)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP13) { // Neoverse N2 core 13
+ Name (_HID, "ACPI0007")
+ Name (_UID, 13)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP14) { // Neoverse N2 core 14
+ Name (_HID, "ACPI0007")
+ Name (_UID, 14)
+ Name (_STA, 0xF)
+ }
+
+ Device (CP15) { // Neoverse N2 core 15
+ Name (_HID, "ACPI0007")
+ Name (_UID, 15)
+ Name (_STA, 0xF)
+ }
+ } // Scope(_SB)
+}
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
new file mode 100644
index 000000000000..dbb23683113a
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Madt.aslc
@@ -0,0 +1,137 @@
+/** @file
+* Multiple APIC Description Table (MADT)
+*
+* Copyright (c) 2020, Arm Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
+ FixedPcdGet32 (PcdCoreCount))
+
+// Multiple APIC Description Table
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[CORE_CNT];
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor;
+ EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[6];
+} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ // MADT specific fields
+ 0, // LocalApicAddress
+ 0 // Flags
+ },
+ {
+ // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags,
+ // PmuIrq, GicBase, GicVBase,
+ // GicHBase, GsivId, GicRBase,
+ // Efficiency)
+ // Note: The GIC Structure of the primary CPU must be the first entry
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core4
+ 0, 4, GET_MPID(0x400, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core5
+ 0, 5, GET_MPID(0x500, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core6
+ 0, 6, GET_MPID(0x600, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core7
+ 0, 7, GET_MPID(0x700, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core8
+ 0, 8, GET_MPID(0x800, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core9
+ 0, 9, GET_MPID(0x900, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core10
+ 0, 10, GET_MPID(0xa00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core11
+ 0, 11, GET_MPID(0xb00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core12
+ 0, 12, GET_MPID(0xc00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core13
+ 0, 13, GET_MPID(0xd00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core14
+ 0, 14, GET_MPID(0xe00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Neoverse N2 core15
+ 0, 15, GET_MPID(0xf00, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ FixedPcdGet32 (PcdGicDistributorBase),
+ 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ },
+ // GIC Distributor Entry
+ EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase),
+ 0, 3),
+ // GIC Redistributor
+ EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistributorsBase),
+ SIZE_16MB),
+ // GIC ITS
+ {
+ EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
+ EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
+ EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
+ EFI_ACPI_6_2_GIC_ITS_INIT(3, 0x30100000),
+ EFI_ACPI_6_2_GIC_ITS_INIT(4, 0x30140000),
+ EFI_ACPI_6_2_GIC_ITS_INIT(5, 0x30180000),
+ },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
new file mode 100644
index 000000000000..63fc249bb77b
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
@@ -0,0 +1,60 @@
+## @file
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2020, Arm Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = RdN2AcpiTables
+ FILE_GUID = c712719a-0aaf-438c-9cdd-35ab4d60207d # gArmSgiAcpiTablesGuid
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dbg2.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Iort.aslc
+ Mcfg.aslc
+ RdN2/Dsdt.asl
+ RdN2/Madt.aslc
+ Spcr.aslc
+ Ssdt.asl
+ SsdtRos.asl
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmPlatformTokenSpaceGuid.PcdClusterCount
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkSize
+ gArmSgiTokenSpaceGuid.PcdVirtioBlkInterrupt
+ gArmSgiTokenSpaceGuid.PcdVirtioNetBaseAddress
+ gArmSgiTokenSpaceGuid.PcdVirtioNetSize
+ gArmSgiTokenSpaceGuid.PcdVirtioNetInterrupt
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread