From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web10.34926.1608521801045282408 for ; Sun, 20 Dec 2020 19:36:41 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: w.sheng@intel.com) IronPort-SDR: ZbhL0lqpsFOHQ8YoxK0Tq9oIzIOzRlzmVZroUIqy/ZSgNK+3kjbEstdH6Vqd6ZuZ3FidgYYWa9 a4lgLWoCZX8Q== X-IronPort-AV: E=McAfee;i="6000,8403,9841"; a="260402823" X-IronPort-AV: E=Sophos;i="5.78,436,1599548400"; d="scan'208";a="260402823" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Dec 2020 19:36:40 -0800 IronPort-SDR: an2R3JV++En/Jg5+oV+GjrIL0YsUqn0GxnoC9Soa5W7jqn02eTMEFRcWET+ZqvSlqjITC/eW3j A2yvaPkvcRdw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,436,1599548400"; d="scan'208";a="390764117" Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.46]) by fmsmga002.fm.intel.com with ESMTP; 20 Dec 2020 19:36:36 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty Subject: [PATCH] IntelSiliconPkg/VTd: Fix build fail for add iommu 5 level paging support Date: Mon, 21 Dec 2020 11:35:57 +0800 Message-Id: <20201221033557.22868-1-w.sheng@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 Build fail is found in patch "IntelSiliconPkg/VTd: Add iommu 5 level paging support". Fix build fail in file TranslationTable.c and TranslationTableEx.c. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3067 Signed-off-by: Sheng Wei Cc: Ray Ni Cc: Rangasai V Chaganty --- .../Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c | 3 +-- .../Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c index ede6e0c5..58ff8550 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c @@ -133,8 +133,7 @@ CreateContextEntry ( mVtdUnitInformation[VtdIndex].Is5LevelPaging = TRUE; if ((mAcpiDmarTable->HostAddressWidth <= 48) && ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) != 0)) { - mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE; - } + mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE; } } else if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) { DEBUG((DEBUG_ERROR, "!!!! Page-table type is not supported on VTD %d !!!!\n", VtdIndex)); diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c index a4d66bc7..b8fa62fb 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTableEx.c @@ -83,8 +83,7 @@ CreateExtContextEntry ( mVtdUnitInformation[VtdIndex].Is5LevelPaging = TRUE; if ((mAcpiDmarTable->HostAddressWidth <= 48) && ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) != 0)) { - mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE; - } + mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE; } } else if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) { DEBUG((DEBUG_ERROR, "!!!! Page-table type is not supported on VTD %d !!!!\n", VtdIndex)); -- 2.16.2.windows.1