From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) by mx.groups.io with SMTP id smtpd.web09.9848.1608631236732269739 for ; Tue, 22 Dec 2020 02:00:37 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: huawei.com, ip: 45.249.212.190, mailfrom: cenjiahui@huawei.com) Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4D0Wz051kRzkv3L; Tue, 22 Dec 2020 17:59:40 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Tue, 22 Dec 2020 18:00:24 +0800 From: "Jiahui Cen" To: CC: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Rebecca Cran , Peter Grehan , Anthony Perard , Julien Grall , Leif Lindholm , Sami Mujawar , , , Jiahui Cen , Yubo Miao Subject: [PATCH v3 4/5] ArmVirtPkg: Add support for extra pci roots Date: Tue, 22 Dec 2020 17:59:43 +0800 Message-ID: <20201222095944.8686-5-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201222095944.8686-1-cenjiahui@huawei.com> References: <20201222095944.8686-1-cenjiahui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Content-Type: text/plain Content-Transfer-Encoding: quoted-printable Use utility functions in PciHostBridgeUtilityLib and some platform specif= ic functions to add support for extra pci roots in ArmVirtPkg. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3059 Cc: Laszlo Ersek Cc: Ard Biesheuvel Cc: Leif Lindholm Signed-off-by: Jiahui Cen Signed-off-by: Yubo Miao --- ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 138 +++++= +++++++++------ 1 file changed, 101 insertions(+), 37 deletions(-) diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c= b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c index d554479bf0de..a29dcecf7044 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c @@ -7,6 +7,7 @@ =20 **/ #include +#include #include #include #include @@ -302,7 +303,60 @@ ProcessPciHost ( return Status; } =20 -STATIC PCI_ROOT_BRIDGE mRootBridge; +EFI_STATUS +InitRootBridge ( + IN UINT64 Supports, + IN UINT64 Attributes, + IN UINT64 AllocAttributes, + IN UINT8 RootBusNumber, + IN UINT8 MaxSubBusNumber, + IN PCI_ROOT_BRIDGE_APERTURE *Io, + IN PCI_ROOT_BRIDGE_APERTURE *Mem, + IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G, + IN PCI_ROOT_BRIDGE_APERTURE *PMem, + IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G, + OUT PCI_ROOT_BRIDGE *RootBus + ) +{ + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath; + + // + // Be safe if other fields are added to PCI_ROOT_BRIDGE later. + // + ZeroMem (RootBus, sizeof *RootBus); + + RootBus->Segment =3D 0; + + RootBus->Supports =3D Supports; + RootBus->Attributes =3D Attributes; + + RootBus->DmaAbove4G =3D TRUE; + + RootBus->AllocationAttributes =3D AllocAttributes; + RootBus->Bus.Base =3D RootBusNumber; + RootBus->Bus.Limit =3D MaxSubBusNumber; + CopyMem (&RootBus->Io, Io, sizeof (*Io)); + CopyMem (&RootBus->Mem, Mem, sizeof (*Mem)); + CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G)); + CopyMem (&RootBus->PMem, PMem, sizeof (*PMem)); + CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G)); + + RootBus->NoExtendedConfigSpace =3D FALSE; + + DevicePath =3D AllocateCopyPool (sizeof mEfiPciRootBridgeDevicePath, + &mEfiPciRootBridgeDevicePath); + if (DevicePath =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES)= ); + return EFI_OUT_OF_RESOURCES; + } + DevicePath->AcpiDevicePath.UID =3D RootBusNumber; + RootBus->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)DevicePath; + + DEBUG ((DEBUG_INFO, + "%a: populated root bus %d, with room for %d subordinate bus(es)\n", + __FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber)); + return EFI_SUCCESS; +} =20 /** Return all the root bridge instances in an array. @@ -319,11 +373,18 @@ PciHostBridgeGetRootBridges ( UINTN *Count ) { - UINT64 IoBase, IoSize; - UINT64 Mmio32Base, Mmio32Size; - UINT64 Mmio64Base, Mmio64Size; - UINT32 BusMin, BusMax; - EFI_STATUS Status; + UINT64 IoBase, IoSize; + UINT64 Mmio32Base, Mmio32Size; + UINT64 Mmio64Base, Mmio64Size; + UINT32 BusMin, BusMax; + EFI_STATUS Status; + UINT64 Attributes; + UINT64 AllocationAttributes; + PCI_ROOT_BRIDGE_APERTURE Io; + PCI_ROOT_BRIDGE_APERTURE Mem; + PCI_ROOT_BRIDGE_APERTURE MemAbove4G; + PCI_ROOT_BRIDGE_APERTURE PMem; + PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; =20 if (PcdGet64 (PcdPciExpressBaseAddress) =3D=3D 0) { DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION_= _)); @@ -341,33 +402,27 @@ PciHostBridgeGetRootBridges ( return NULL; } =20 - *Count =3D 1; + ZeroMem (&Io, sizeof (Io)); + ZeroMem (&Mem, sizeof (Mem)); + ZeroMem (&MemAbove4G, sizeof (MemAbove4G)); =20 - mRootBridge.Segment =3D 0; - mRootBridge.Supports =3D EFI_PCI_ATTRIBUTE_ISA_IO_16 | - EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_= IO | - EFI_PCI_ATTRIBUTE_VGA_IO_16 | - EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_1= 6; - mRootBridge.Attributes =3D mRootBridge.Supports; + Attributes =3D EFI_PCI_ATTRIBUTE_ISA_IO_16 | + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | + EFI_PCI_ATTRIBUTE_VGA_IO_16 | + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; =20 - mRootBridge.DmaAbove4G =3D TRUE; - mRootBridge.NoExtendedConfigSpace =3D FALSE; - mRootBridge.ResourceAssigned =3D FALSE; + AllocationAttributes =3D EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM; =20 - mRootBridge.AllocationAttributes =3D EFI_PCI_HOST_BRIDGE_COMBINE_MEM_= PMEM; - - mRootBridge.Bus.Base =3D BusMin; - mRootBridge.Bus.Limit =3D BusMax; - mRootBridge.Io.Base =3D IoBase; - mRootBridge.Io.Limit =3D IoBase + IoSize - 1; - mRootBridge.Mem.Base =3D Mmio32Base; - mRootBridge.Mem.Limit =3D Mmio32Base + Mmio32Size - 1; + Io.Base =3D IoBase; + Io.Limit =3D IoBase + IoSize - 1; + Mem.Base =3D Mmio32Base; + Mem.Limit =3D Mmio32Base + Mmio32Size - 1; =20 if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { - mRootBridge.MemAbove4G.Base =3D Mmio64Base; - mRootBridge.MemAbove4G.Limit =3D Mmio64Base + Mmio64Size - 1; + MemAbove4G.Base =3D Mmio64Base; + MemAbove4G.Limit =3D Mmio64Base + Mmio64Size - 1; if (Mmio64Size > 0) { - mRootBridge.AllocationAttributes |=3D EFI_PCI_HOST_BRIDGE_MEM64_DE= CODE; + AllocationAttributes |=3D EFI_PCI_HOST_BRIDGE_MEM64_DECODE; } } else { // @@ -376,21 +431,30 @@ PciHostBridgeGetRootBridges ( // BARs unless they are allocated below 4 GB. So ignore the range ab= ove // 4 GB in this case. // - mRootBridge.MemAbove4G.Base =3D MAX_UINT64; - mRootBridge.MemAbove4G.Limit =3D 0; + MemAbove4G.Base =3D MAX_UINT64; + MemAbove4G.Limit =3D 0; } =20 // // No separate ranges for prefetchable and non-prefetchable BARs // - mRootBridge.PMem.Base =3D MAX_UINT64; - mRootBridge.PMem.Limit =3D 0; - mRootBridge.PMemAbove4G.Base =3D MAX_UINT64; - mRootBridge.PMemAbove4G.Limit =3D 0; + PMem.Base =3D MAX_UINT64; + PMem.Limit =3D 0; + PMemAbove4G.Base =3D MAX_UINT64; + PMemAbove4G.Limit =3D 0; =20 - mRootBridge.DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBri= dgeDevicePath; - - return &mRootBridge; + return PciHostBridgeUtilityExtraRoots ( + Count, + BusMin, + BusMax, + Attributes, + AllocationAttributes, + Io, + Mem, + MemAbove4G, + PMem, + PMemAbove4G + ); } =20 /** @@ -407,7 +471,7 @@ PciHostBridgeFreeRootBridges ( UINTN Count ) { - ASSERT (Count =3D=3D 1); + PciHostBridgeUtilityFreeRootBridges (Bridges, Count); } =20 /** --=20 2.28.0