From: "Heng Luo" <heng.luo@intel.com>
To: devel@edk2.groups.io
Cc: Ray Ni <ray.ni@intel.com>, Hao A Wu <hao.a.wu@intel.com>
Subject: [PATCH 2/2] MdeModulePkg/Bus/Pci/PciBusDxe: Support PCIe Resizable BAR Capability
Date: Mon, 28 Dec 2020 16:26:10 +0800 [thread overview]
Message-ID: <20201228082610.2565-2-heng.luo@intel.com> (raw)
In-Reply-To: <20201228082610.2565-1-heng.luo@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=313
Add PcdPcieResizableBarCapabilitySupport to enable/disable PCIe Resizable
BAR Capability fearture.
Program the Resizable BAR Register if the device suports PCIe Resizable
BAR Capability and PcdPcieResizableBarCapabilitySupport is TRUE.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---
MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 4 +++-
MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 3 ++-
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 27 ++++++++++++++++++++++++++-
MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h | 12 +++++++++++-
MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c | 185 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--------------
MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h | 22 +++++++++++++++++++++-
MdeModulePkg/MdeModulePkg.dec | 6 ++++++
7 files changed, 240 insertions(+), 19 deletions(-)
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
index d4113993c8..add1756d5c 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h
@@ -1,7 +1,7 @@
/** @file
Header files and data structures needed by PCI Bus module.
-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -280,6 +280,8 @@ struct _PCI_IO_DEVICE {
// This field is used to support this case.
//
UINT16 BridgeIoAlignment;
+ UINT32 ResizableBarOffset;
+ UINT32 ResizableBarNumber;
};
#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
index 9284998f36..b3e5213b92 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
@@ -2,7 +2,7 @@
# The PCI bus driver will probe all PCI devices and allocate MMIO and IO space for these devices.
# Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable hot plug supporting.
#
-# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -106,6 +106,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration ## SOMETIMES_CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarCapabilitySupport ## CONSUMES
[UserExtensions.TianoCore."ExtraFiles"]
PciBusDxeExtra.uni
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index 6c68a97d4e..d1d38241da 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -1,7 +1,7 @@
/** @file
PCI emumeration support functions implementation for PCI Bus module.
-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -2426,6 +2426,31 @@ CreatePciIoDevice (
}
}
+ PciIoDevice->ResizableBarOffset = 0;
+ if (PcdGetBool (PcdPcieResizableBarCapabilitySupport)) {
+ Status = LocatePciExpressCapabilityRegBlock (
+ PciIoDevice,
+ PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID,
+ &PciIoDevice->ResizableBarOffset,
+ NULL
+ );
+ if (!EFI_ERROR (Status)) {
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBarControl;
+ UINT32 Offset;
+ Offset = PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER)
+ + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY),
+ PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ Offset,
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL),
+ &ResizableBarControl
+ );
+ PciIoDevice->ResizableBarNumber = ResizableBarControl.Bits.ResizableBarNumber;
+ PciProgramResizableBar (PciIoDevice, PciResizableBarMax);
+ }
+ }
+
//
// Initialize the reserved resource list
//
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h
index d76606c7df..919d678e2f 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h
@@ -1,7 +1,7 @@
/** @file
PCI enumeration support functions declaration for PCI Bus module.
-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -467,4 +467,14 @@ DumpPpbPaddingResource (
IN PCI_BAR_TYPE ResourceType
);
+/**
+ Dump the PCI BAR information.
+
+ @param PciIoDevice PCI IO instance.
+**/
+VOID
+DumpPciBars (
+ IN PCI_IO_DEVICE *PciIoDevice
+ );
+
#endif
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
index 72690ab647..1a7ddb4455 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c
@@ -1,7 +1,7 @@
/** @file
Internal library implementation for PCI Bus module.
-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -377,6 +377,60 @@ DumpResourceMap (
}
}
+/**
+ Adjust the Devices' BAR size to minimum value if it support Resizeable BAR capability.
+
+ @param RootBridgeDev Pointer to instance of PCI_IO_DEVICE..
+
+ @return TRUE if BAR size is adjusted.
+
+**/
+BOOLEAN
+AdjustPciDeviceBarSize (
+ IN PCI_IO_DEVICE *RootBridgeDev
+ )
+{
+ PCI_IO_DEVICE *PciIoDevice;
+ LIST_ENTRY *CurrentLink;
+ BOOLEAN Adjusted;
+ UINTN Offset;
+ UINTN BarIndex;
+
+ Adjusted = FALSE;
+ CurrentLink = RootBridgeDev->ChildList.ForwardLink;
+
+ while (CurrentLink != NULL && CurrentLink != &RootBridgeDev->ChildList) {
+ PciIoDevice = PCI_IO_DEVICE_FROM_LINK (CurrentLink);
+
+ if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
+ if (AdjustPciDeviceBarSize (PciIoDevice)) {
+ Adjusted = TRUE;
+ }
+ } else {
+ if (PciIoDevice->ResizableBarOffset != 0) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "PciBus: [%02x|%02x|%02x] Adjust Pci Device Bar Size\n",
+ PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber
+ ));
+ PciProgramResizableBar (PciIoDevice, PciResizableBarMin);
+ //
+ // Start to parse the bars
+ //
+ for (Offset = 0x10, BarIndex = 0; Offset <= 0x24 && BarIndex < PCI_MAX_BAR; BarIndex++) {
+ Offset = PciParseBar (PciIoDevice, Offset, BarIndex);
+ }
+ Adjusted = TRUE;
+ DEBUG_CODE (DumpPciBars (PciIoDevice););
+ }
+ }
+
+ CurrentLink = CurrentLink->ForwardLink;
+ }
+
+ return Adjusted;
+}
+
/**
Submits the I/O and memory resource requirements for the specified PCI Host Bridge.
@@ -422,6 +476,10 @@ PciHostBridgeResourceAllocator (
PCI_RESOURCE_NODE PMem64Pool;
EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData;
EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;
+ BOOLEAN ResizableBarNeedAdjust;
+ BOOLEAN ResizableBarAdjusted;
+
+ ResizableBarNeedAdjust = PcdGetBool (PcdPcieResizableBarCapabilitySupport);
//
// It may try several times if the resource allocation fails
@@ -703,19 +761,30 @@ PciHostBridgeResourceAllocator (
sizeof (AllocFailExtendedData)
);
- Status = PciHostBridgeAdjustAllocation (
- &IoPool,
- &Mem32Pool,
- &PMem32Pool,
- &Mem64Pool,
- &PMem64Pool,
- IoResStatus,
- Mem32ResStatus,
- PMem32ResStatus,
- Mem64ResStatus,
- PMem64ResStatus
- );
-
+ //
+ // Try to adjust the Devices' BAR size to minimum value in first loop
+ // if enabling PCIe Resizable BAR Capability support.
+ // call PciHostBridgeAdjustAllocation() only if BAR size is not adjust.
+ //
+ ResizableBarAdjusted = FALSE;
+ if (ResizableBarNeedAdjust) {
+ ResizableBarAdjusted = AdjustPciDeviceBarSize (RootBridgeDev);
+ ResizableBarNeedAdjust = FALSE;
+ }
+ if (!ResizableBarAdjusted) {
+ Status = PciHostBridgeAdjustAllocation (
+ &IoPool,
+ &Mem32Pool,
+ &PMem32Pool,
+ &Mem64Pool,
+ &PMem64Pool,
+ IoResStatus,
+ Mem32ResStatus,
+ PMem32ResStatus,
+ Mem64ResStatus,
+ PMem64ResStatus
+ );
+ }
//
// Destroy all the resource tree
//
@@ -1651,3 +1720,91 @@ PciHostBridgeEnumerator (
return EFI_SUCCESS;
}
+
+/**
+ This function is used to program the Resizable BAR Register.
+
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.
+ @param ResizableBarCap PciResizableBarMax: Set BAR to max size
+ PciResizableBarMin: set BAR to min size.
+
+ @retval EFI_SUCCESS Successfully enumerated the host bridge.
+ @retval other Some error occurred when enumerating the host bridge.
+
+**/
+EFI_STATUS
+PciProgramResizableBar (
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN PCI_RESIZEABLE_BAR_CAP ResizableBarCap
+ )
+{
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT64 Capabilities;
+ UINT32 BarIndex;
+ UINT32 Offset;
+ INTN Bit;
+ UINTN ResizableBarNumber;
+ EFI_STATUS Status;
+ PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Entries[PCI_MAX_BAR];
+
+ ASSERT (PciIoDevice->ResizableBarOffset != 0);
+
+ DEBUG ((DEBUG_INFO, " Programs Resizable BAR register, offset: 0x%08x, number: %d\n",
+ PciIoDevice->ResizableBarOffset, PciIoDevice->ResizableBarNumber));
+
+ ResizableBarNumber = MIN (PciIoDevice->ResizableBarNumber, PCI_MAX_BAR);
+ PciIo = &PciIoDevice->PciIo;
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER),
+ sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY) * ResizableBarNumber,
+ (VOID *)(&Entries)
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ for (BarIndex = 0; BarIndex < ResizableBarNumber; BarIndex++) {
+
+ //
+ // When the bit of Capabilities Set, indicates that the Function supports
+ // operating with the BAR sized to (2^Bit) MB.
+ // Example:
+ // Bit 0 is set: supports operating with the BAR sized to 1 MB
+ // Bit 1 is set: supports operating with the BAR sized to 2 MB
+ // Bit n is set: supports operating with the BAR sized to (2^n) MB
+ //
+ Capabilities = Entries[BarIndex].ResizableBarControl.Bits.BarSizeCapability << 28
+ | Entries[BarIndex].ResizableBarCapability.Bits.BarSizeCapability;
+
+ if (ResizableBarCap == PciResizableBarMax) {
+ Bit = HighBitSet64(Capabilities);
+ } else if (ResizableBarCap == PciResizableBarMin) {
+ Bit = LowBitSet64(Capabilities);
+ } else {
+ ASSERT ((ResizableBarCap == PciResizableBarMax) || (ResizableBarCap == PciResizableBarMin));
+ }
+
+ ASSERT (Bit >= 0);
+
+ Offset = PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER)
+ + BarIndex * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY)
+ + OFFSET_OF (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY, ResizableBarControl);
+
+ Entries[BarIndex].ResizableBarControl.Bits.BarSize = (UINT32) Bit;
+ DEBUG ((
+ DEBUG_INFO,
+ " Resizable Bar: Offset = 0x%x, Bar Size Capability = 0x%016lx, New Bar Size = 0x%lx\n",
+ OFFSET_OF (PCI_TYPE00, Device.Bar[Entries[BarIndex].ResizableBarControl.Bits.BarIndex]),
+ Capabilities, LShiftU64 (SIZE_1MB, Bit)
+ ));
+ PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint32,
+ Offset,
+ 1,
+ &Entries[BarIndex].ResizableBarControl.Uint32
+ );
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h
index 10b435d146..94b20f18e8 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h
@@ -1,7 +1,7 @@
/** @file
Internal library declaration for PCI Bus module.
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -24,6 +24,10 @@ typedef struct {
UINT8 *AllocRes;
} EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD;
+typedef enum {
+ PciResizableBarMin = 0x00,
+ PciResizableBarMax = 0xFF
+} PCI_RESIZEABLE_BAR_CAP;
/**
Retrieve the PCI Card device BAR information via PciIo interface.
@@ -156,4 +160,20 @@ PciHostBridgeEnumerator (
IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
);
+/**
+ This function is used to program the Resizable BAR Register.
+
+ @param PciIoDevice A pointer to the PCI_IO_DEVICE.
+ @param ResizableBarCap PciResizableBarMax: Set BAR to max size
+ PciResizableBarMin: set BAR to min size.
+
+ @retval EFI_SUCCESS Successfully enumerated the host bridge.
+ @retval other Some error occurred when enumerating the host bridge.
+
+**/
+EFI_STATUS
+PciProgramResizableBar (
+ IN PCI_IO_DEVICE *PciIoDevice,
+ IN PCI_RESIZEABLE_BAR_CAP ResizableBarCap
+ );
#endif
diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index 9b52b34494..10c819ee39 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -2043,6 +2043,12 @@
# @Prompt Enable StatusCode via memory.
gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE|BOOLEAN|0x00010023
+ ## Indicates if the PCIe Resizable BAR Capability Supported.<BR><BR>
+ # TRUE - PCIe Resizable BAR Capability is supported.<BR>
+ # FALSE - PCIe Resizable BAR Capability is not supported.<BR>
+ # @Prompt Enable PCIe Resizable BAR Capability support.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarCapabilitySupport|TRUE|BOOLEAN|0x10000024
+
[PcdsPatchableInModule]
## Specify memory size with page number for PEI code when
# Loading Module at Fixed Address feature is enabled.
--
2.24.0.windows.2
next prev parent reply other threads:[~2020-12-28 8:27 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-28 8:26 [PATCH 1/2] MdePkg: Define structures for Resizable BAR Capability Heng Luo
2020-12-28 8:26 ` Heng Luo [this message]
2021-01-04 5:34 ` [edk2-devel] [PATCH 2/2] MdeModulePkg/Bus/Pci/PciBusDxe: Support PCIe " Ni, Ray
2021-01-04 6:39 ` Heng Luo
2020-12-29 1:45 ` 回复: [edk2-devel] [PATCH 1/2] MdePkg: Define structures for " gaoliming
2020-12-29 1:55 ` Heng Luo
2021-01-04 0:58 ` 回复: " gaoliming
2021-01-07 14:51 ` Cindy Roberts
2021-01-08 0:44 ` 回复: " gaoliming
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201228082610.2565-2-heng.luo@intel.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox