From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com []) by mx.groups.io with SMTP id smtpd.web09.10289.1609742898338421273 for ; Sun, 03 Jan 2021 22:48:19 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: D5WmCq3yWqqN3Ke1P140ShVdqb7hJ5jzc89bvFoPWQz5ujAgi5DtRjbil7p6HPyzgPSlgfXLMV YPZHWPcovI9g== X-IronPort-AV: E=McAfee;i="6000,8403,9853"; a="156112733" X-IronPort-AV: E=Sophos;i="5.78,473,1599548400"; d="scan'208";a="156112733" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jan 2021 22:48:18 -0800 IronPort-SDR: R4B6HEiTRaT2yAFcjQU493BHcAWnFljK8/HruLyMAL7pRMmJaS/xWBplf4TuRo0Gm2/qO90OYQ pMRZzgzYnVyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,473,1599548400"; d="scan'208";a="349786363" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 03 Jan 2021 22:48:17 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Ray Ni , Hao A Wu Subject: [Patch V2 2/2] MdeModulePkg/Bus/Pci/PciBusDxe: Support PCIe Resizable BAR Capability Date: Mon, 4 Jan 2021 14:46:08 +0800 Message-Id: <20210104064608.3727-2-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210104064608.3727-1-heng.luo@intel.com> References: <20210104064608.3727-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D313 Add PcdPcieResizableBarCapabilitySupport to enable/disable PCIe Resizable BAR Capability fearture. Program the Resizable BAR Register if the device suports PCIe Resizable BAR Capability and PcdPcieResizableBarCapabilitySupport is TRUE. Cc: Ray Ni Cc: Hao A Wu Signed-off-by: Heng Luo --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 4 +++- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 3 ++- MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 27 ++++++++++++++= ++++++++++++- MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h | 12 +++++++++++- MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c | 185 ++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++-------------- MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h | 22 ++++++++++++++= +++++++- MdeModulePkg/MdeModulePkg.dec | 8 +++++++- 7 files changed, 241 insertions(+), 20 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index d4113993c8..a619a68526 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -1,7 +1,7 @@ /** @file=0D Header files and data structures needed by PCI Bus module.=0D =0D -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -280,6 +280,8 @@ struct _PCI_IO_DEVICE { // This field is used to support this case.=0D //=0D UINT16 BridgeIoAlignment;=0D + UINT32 ResizableBarOffset;=0D + UINT32 ResizableBarNumber;=0D };=0D =0D #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bu= s/Pci/PciBusDxe/PciBusDxe.inf index 9284998f36..e317169d9c 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -2,7 +2,7 @@ # The PCI bus driver will probe all PCI devices and allocate MMIO and IO = space for these devices.=0D # Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable hot= plug supporting.=0D #=0D -# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
= =0D +# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -106,6 +106,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport ## CONSUME= S=0D gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport ## CONSUME= S=0D gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration ## SOMETIM= ES_CONSUMES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport ## CONSUME= S=0D =0D [UserExtensions.TianoCore."ExtraFiles"]=0D PciBusDxeExtra.uni=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeMod= ulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index 6c68a97d4e..1b64924b7b 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -1,7 +1,7 @@ /** @file=0D PCI emumeration support functions implementation for PCI Bus module.=0D =0D -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
=0D (C) Copyright 2015 Hewlett Packard Enterprise Development LP
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -2426,6 +2426,31 @@ CreatePciIoDevice ( }=0D }=0D =0D + PciIoDevice->ResizableBarOffset =3D 0;=0D + if (PcdGetBool (PcdPcieResizableBarSupport)) {=0D + Status =3D LocatePciExpressCapabilityRegBlock (=0D + PciIoDevice,=0D + PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID,=0D + &PciIoDevice->ResizableBarOffset,=0D + NULL=0D + );=0D + if (!EFI_ERROR (Status)) {=0D + PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL ResizableBar= Control;=0D + UINT32 Offset;=0D + Offset =3D PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXT= ENDED_CAPABILITIES_HEADER)=0D + + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_= CAPABILITY),=0D + PciIo->Pci.Read (=0D + PciIo,=0D + EfiPciIoWidthUint8,=0D + Offset,=0D + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONT= ROL),=0D + &ResizableBarControl=0D + );=0D + PciIoDevice->ResizableBarNumber =3D ResizableBarControl.Bits.Resizab= leBarNumber;=0D + PciProgramResizableBar (PciIoDevice, PciResizableBarMax);=0D + }=0D + }=0D +=0D //=0D // Initialize the reserved resource list=0D //=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h b/MdeMod= ulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h index d76606c7df..4581b270c9 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h @@ -1,7 +1,7 @@ /** @file=0D PCI enumeration support functions declaration for PCI Bus module.=0D =0D -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -467,4 +467,14 @@ DumpPpbPaddingResource ( IN PCI_BAR_TYPE ResourceType=0D );=0D =0D +/**=0D + Dump the PCI BAR information.=0D +=0D + @param PciIoDevice PCI IO instance.=0D +**/=0D +VOID=0D +DumpPciBars (=0D + IN PCI_IO_DEVICE *PciIoDevice=0D + );=0D +=0D #endif=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciLib.c index 72690ab647..6bba283671 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c @@ -1,7 +1,7 @@ /** @file=0D Internal library implementation for PCI Bus module.=0D =0D -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
=0D (C) Copyright 2015 Hewlett Packard Enterprise Development LP
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -377,6 +377,60 @@ DumpResourceMap ( }=0D }=0D =0D +/**=0D + Adjust the Devices' BAR size to minimum value if it support Resizeable B= AR capability.=0D +=0D + @param RootBridgeDev Pointer to instance of PCI_IO_DEVICE..=0D +=0D + @return TRUE if BAR size is adjusted.=0D +=0D +**/=0D +BOOLEAN=0D +AdjustPciDeviceBarSize (=0D + IN PCI_IO_DEVICE *RootBridgeDev=0D + )=0D +{=0D + PCI_IO_DEVICE *PciIoDevice;=0D + LIST_ENTRY *CurrentLink;=0D + BOOLEAN Adjusted;=0D + UINTN Offset;=0D + UINTN BarIndex;=0D +=0D + Adjusted =3D FALSE;=0D + CurrentLink =3D RootBridgeDev->ChildList.ForwardLink;=0D +=0D + while (CurrentLink !=3D NULL && CurrentLink !=3D &RootBridgeDev->ChildLi= st) {=0D + PciIoDevice =3D PCI_IO_DEVICE_FROM_LINK (CurrentLink);=0D +=0D + if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {=0D + if (AdjustPciDeviceBarSize (PciIoDevice)) {=0D + Adjusted =3D TRUE;=0D + }=0D + } else {=0D + if (PciIoDevice->ResizableBarOffset !=3D 0) {=0D + DEBUG ((=0D + DEBUG_ERROR,=0D + "PciBus: [%02x|%02x|%02x] Adjust Pci Device Bar Size\n",=0D + PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->= FunctionNumber=0D + ));=0D + PciProgramResizableBar (PciIoDevice, PciResizableBarMin);=0D + //=0D + // Start to parse the bars=0D + //=0D + for (Offset =3D 0x10, BarIndex =3D 0; Offset <=3D 0x24 && BarIndex= < PCI_MAX_BAR; BarIndex++) {=0D + Offset =3D PciParseBar (PciIoDevice, Offset, BarIndex);=0D + }=0D + Adjusted =3D TRUE;=0D + DEBUG_CODE (DumpPciBars (PciIoDevice););=0D + }=0D + }=0D +=0D + CurrentLink =3D CurrentLink->ForwardLink;=0D + }=0D +=0D + return Adjusted;=0D +}=0D +=0D /**=0D Submits the I/O and memory resource requirements for the specified PCI H= ost Bridge.=0D =0D @@ -422,6 +476,10 @@ PciHostBridgeResourceAllocator ( PCI_RESOURCE_NODE PMem64Pool;=0D EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData;=0D EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD AllocFailExtendedData;=0D + BOOLEAN ResizableBarNeedAdjust;=0D + BOOLEAN ResizableBarAdjusted;=0D +=0D + ResizableBarNeedAdjust =3D PcdGetBool (PcdPcieResizableBarSupport);=0D =0D //=0D // It may try several times if the resource allocation fails=0D @@ -703,19 +761,30 @@ PciHostBridgeResourceAllocator ( sizeof (AllocFailExtendedData)=0D );=0D =0D - Status =3D PciHostBridgeAdjustAllocation (=0D - &IoPool,=0D - &Mem32Pool,=0D - &PMem32Pool,=0D - &Mem64Pool,=0D - &PMem64Pool,=0D - IoResStatus,=0D - Mem32ResStatus,=0D - PMem32ResStatus,=0D - Mem64ResStatus,=0D - PMem64ResStatus=0D - );=0D -=0D + //=0D + // When resource conflict happens, adjust the BAR size first.=0D + // Only when adjusting BAR size doesn't help or BAR size cannot be ad= justed,=0D + // reject the device who requests largest resource that causes confli= ct.=0D + //=0D + ResizableBarAdjusted =3D FALSE;=0D + if (ResizableBarNeedAdjust) {=0D + ResizableBarAdjusted =3D AdjustPciDeviceBarSize (RootBridgeDev);=0D + ResizableBarNeedAdjust =3D FALSE;=0D + }=0D + if (!ResizableBarAdjusted) {=0D + Status =3D PciHostBridgeAdjustAllocation (=0D + &IoPool,=0D + &Mem32Pool,=0D + &PMem32Pool,=0D + &Mem64Pool,=0D + &PMem64Pool,=0D + IoResStatus,=0D + Mem32ResStatus,=0D + PMem32ResStatus,=0D + Mem64ResStatus,=0D + PMem64ResStatus=0D + );=0D + }=0D //=0D // Destroy all the resource tree=0D //=0D @@ -1651,3 +1720,91 @@ PciHostBridgeEnumerator ( =0D return EFI_SUCCESS;=0D }=0D +=0D +/**=0D + This function is used to program the Resizable BAR Register.=0D +=0D + @param PciIoDevice A pointer to the PCI_IO_DEVICE.=0D + @param ResizableBarOp PciResizableBarMax: Set BAR to max size=0D + PciResizableBarMin: set BAR to min size.=0D +=0D + @retval EFI_SUCCESS Successfully enumerated the host bridge.=0D + @retval other Some error occurred when enumerating the h= ost bridge.=0D +=0D +**/=0D +EFI_STATUS=0D +PciProgramResizableBar (=0D + IN PCI_IO_DEVICE *PciIoDevice,=0D + IN PCI_RESIZABLE_BAR_OPERATION ResizableBarOp=0D + )=0D +{=0D + EFI_PCI_IO_PROTOCOL *PciIo;=0D + UINT64 Capabilities;=0D + UINT32 Index;=0D + UINT32 Offset;=0D + INTN Bit;=0D + UINTN ResizableBarNumber;=0D + EFI_STATUS Status;=0D + PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Entries[PCI_MAX_= BAR];=0D +=0D + ASSERT (PciIoDevice->ResizableBarOffset !=3D 0);=0D +=0D + DEBUG ((DEBUG_INFO, " Programs Resizable BAR register, offset: 0x%08x,= number: %d\n",=0D + PciIoDevice->ResizableBarOffset, PciIoDevice->ResizableBarNumber))= ;=0D +=0D + ResizableBarNumber =3D MIN (PciIoDevice->ResizableBarNumber, PCI_MAX_BAR= );=0D + PciIo =3D &PciIoDevice->PciIo;=0D + Status =3D PciIo->Pci.Read (=0D + PciIo,=0D + EfiPciIoWidthUint8,=0D + PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTENDED_C= APABILITIES_HEADER),=0D + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY) *= ResizableBarNumber,=0D + (VOID *)(&Entries)=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + for (Index =3D 0; Index < ResizableBarNumber; Index++) {=0D +=0D + //=0D + // When the bit of Capabilities Set, indicates that the Function suppo= rts=0D + // operating with the BAR sized to (2^Bit) MB.=0D + // Example:=0D + // Bit 0 is set: supports operating with the BAR sized to 1 MB=0D + // Bit 1 is set: supports operating with the BAR sized to 2 MB=0D + // Bit n is set: supports operating with the BAR sized to (2^n) MB=0D + //=0D + Capabilities =3D LShiftU64(Entries[Index].ResizableBarControl.Bits.Bar= SizeCapability, 28)=0D + | Entries[Index].ResizableBarCapability.Bits.BarSizeCapa= bility;=0D +=0D + if (ResizableBarOp =3D=3D PciResizableBarMax) {=0D + Bit =3D HighBitSet64(Capabilities);=0D + } else if (ResizableBarOp =3D=3D PciResizableBarMin) {=0D + Bit =3D LowBitSet64(Capabilities);=0D + } else {=0D + ASSERT ((ResizableBarOp =3D=3D PciResizableBarMax) || (ResizableBarO= p =3D=3D PciResizableBarMin));=0D + }=0D +=0D + ASSERT (Bit >=3D 0);=0D +=0D + Offset =3D PciIoDevice->ResizableBarOffset + sizeof (PCI_EXPRESS_EXTEN= DED_CAPABILITIES_HEADER)=0D + + Index * sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_= BAR_ENTRY)=0D + + OFFSET_OF (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_E= NTRY, ResizableBarControl);=0D +=0D + Entries[Index].ResizableBarControl.Bits.BarSize =3D (UINT32) Bit;=0D + DEBUG ((=0D + DEBUG_INFO,=0D + " Resizable Bar: Offset =3D 0x%x, Bar Size Capability =3D 0x%016lx= , New Bar Size =3D 0x%lx\n",=0D + OFFSET_OF (PCI_TYPE00, Device.Bar[Entries[Index].ResizableBarControl= .Bits.BarIndex]),=0D + Capabilities, LShiftU64 (SIZE_1MB, Bit)=0D + ));=0D + PciIo->Pci.Write (=0D + PciIo,=0D + EfiPciIoWidthUint32,=0D + Offset,=0D + 1,=0D + &Entries[Index].ResizableBarControl.Uint32=0D + );=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciLib.h index 10b435d146..aeec6d6b6d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h @@ -1,7 +1,7 @@ /** @file=0D Internal library declaration for PCI Bus module.=0D =0D -Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
=0D +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -24,6 +24,10 @@ typedef struct { UINT8 *AllocRes;=0D } EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD;=0D =0D +typedef enum {=0D + PciResizableBarMin =3D 0x00,=0D + PciResizableBarMax =3D 0xFF=0D +} PCI_RESIZABLE_BAR_OPERATION;=0D =0D /**=0D Retrieve the PCI Card device BAR information via PciIo interface.=0D @@ -156,4 +160,20 @@ PciHostBridgeEnumerator ( IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc=0D );=0D =0D +/**=0D + This function is used to program the Resizable BAR Register.=0D +=0D + @param PciIoDevice A pointer to the PCI_IO_DEVICE.=0D + @param ResizableBarOp PciResizableBarMax: Set BAR to max size=0D + PciResizableBarMin: set BAR to min size.=0D +=0D + @retval EFI_SUCCESS Successfully enumerated the host bridge.=0D + @retval other Some error occurred when enumerating the h= ost bridge.=0D +=0D +**/=0D +EFI_STATUS=0D +PciProgramResizableBar (=0D + IN PCI_IO_DEVICE *PciIoDevice,=0D + IN PCI_RESIZABLE_BAR_OPERATION ResizableBarOp=0D + );=0D #endif=0D diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 9b52b34494..9173fdef83 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -4,7 +4,7 @@ # and libraries instances, which are used for those modules.=0D #=0D # Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.=0D -# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
=0D +# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
=0D # Copyright (c) 2016, Linaro Ltd. All rights reserved.
=0D # (C) Copyright 2016 - 2019 Hewlett Packard Enterprise Development LP
= =0D # Copyright (c) 2017, AMD Incorporated. All rights reserved.
=0D @@ -2043,6 +2043,12 @@ # @Prompt Enable StatusCode via memory.=0D gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE|BOOLEAN|0x00= 010023=0D =0D + ## Indicates if the PCIe Resizable BAR Capability Supported.

=0D + # TRUE - PCIe Resizable BAR Capability is supported.
=0D + # FALSE - PCIe Resizable BAR Capability is not supported.
=0D + # @Prompt Enable PCIe Resizable BAR Capability support.=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport|TRUE|BOOLEAN|0= x10000024=0D +=0D [PcdsPatchableInModule]=0D ## Specify memory size with page number for PEI code when=0D # Loading Module at Fixed Address feature is enabled.=0D --=20 2.24.0.windows.2