From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) by mx.groups.io with SMTP id smtpd.web10.65.1609801123970806012 for ; Mon, 04 Jan 2021 14:58:44 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=TYo9rwhQ; spf=pass (domain: nuviainc.com, ip: 209.85.216.53, mailfrom: rebecca@nuviainc.com) Received: by mail-pj1-f53.google.com with SMTP id l23so538560pjg.1 for ; Mon, 04 Jan 2021 14:58:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z+1qAhfd7Lm05ya/KF25iwh8+L/nIjTka3bYRgymc/U=; b=TYo9rwhQ7UapIhFCjhB8h41JpsDsoJd5h/Qr5TFf6zIrFQt0DHvGhtS3te+JmFQPty ACHAYTYhDnsSeskBSQ0Kk5DkqloUW8tl5aY5akHNfIt/keSNLePtYNNlZi0hev7PdBZ6 oMw0fw7VXGK2FGYVR1wUygcM0C8Hc0n7Mnpm6It7O2WivQGplT4P/+5Mk4UCtcwcEsHj nrhv7gslw6PRY7cxiRiUTZC88cvxRi24vsajlC4tZDBznkGhKaXV9/0H5WsTW2UOBDy/ kuytxMnrdXntk9Ylo0v8gV2DQugmUE0T8VhPjlUbhNxhiTQsMF4eEJFiywmoas/9aYwU pZAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z+1qAhfd7Lm05ya/KF25iwh8+L/nIjTka3bYRgymc/U=; b=H2bYJxZrAGuzed2Xo9yHRP2LlvP/bWaJA8cIv5vJCOLYTkFcvmfUe5E/IELsJ2tWeO 4YCgQqUX1ERcr3dj37tMQMaT4uECWiQvOw4AwD4UEDm6JyAyAmZPXcX98iAbb1gMDYV5 AFYFNEYAsw7P+t+qdwVKitDvVZ2mPHHQoE9MKz3J6rOGJZWBGKqIm++qG9Yz7b3MinZv uwHGRWu6507WkYvRc7VXy2gy4TNNYh19aHT1vKMYGCudWhG46nrPjqS+YK4c51aXX8k+ SBJpmoP/cTASyyGyBZDGZWrdkqF36nw6UogUBrNvzlQ2XaZWYkvajmHm7hUNxo62Vqtg OHZw== X-Gm-Message-State: AOAM533jK+bjCkbdMtpgSKcoZjyl6FnWQ+5jb3L6lXwsNb/aONYqkHHG nUPug7cfHYd0e0YXLJ+nurpWN3k6cfrrjdcuIgfdcj85fGYjpWU0AmARBH0mgB+6sHBiR9gXyzI rC406tcLzIFJFe4bGiri65nx5FO3QZiX0GckcKxTH0/cbfuInKbTjWfGgKW7x3KdYvlzvsJLG X-Google-Smtp-Source: ABdhPJyBf1/gE+r6mv7M0r+ltSeUB4qJvc9JHVeONYXjs3N8DgYOUFqULk/94eGJxyQh3A1Sbavuzg== X-Received: by 2002:a17:90b:4a10:: with SMTP id kk16mr1103792pjb.30.1609801123180; Mon, 04 Jan 2021 14:58:43 -0800 (PST) Return-Path: Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id x143sm64185289pgx.66.2021.01.04.14.58.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:58:42 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Leif Lindholm , Ard Biesheuvel , "nd @ arm . com . Sami Mujawar" , Liming Gao , Michael D Kinney , Zhiguang Liu Subject: [PATCH v5 03/23] ArmPkg: Add register encoding definition for MMFR2 Date: Mon, 4 Jan 2021 15:58:10 -0700 Message-Id: <20210104225830.12606-4-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104225830.12606-1-rebecca@nuviainc.com> References: <20210104225830.12606-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add register encoding definition for Memory Model Feature Register 2. We need to define it here because we build for ARMv8.0, which doesn't have it. Signed-off-by: Rebecca Cran --- ArmPkg/Include/Chipset/AArch64.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h index 0ade5cce91c3..7c2b592f92ee 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -112,6 +112,10 @@ #define ARM_VECTOR_LOW_A32_FIQ 0x700 #define ARM_VECTOR_LOW_A32_SERR 0x780 +// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we +// build for ARMv8.0, we need to define the register here. +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + #define VECTOR_BASE(tbl) \ .section .text.##tbl##,"ax"; \ .align 11; \ -- 2.26.2