From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) by mx.groups.io with SMTP id smtpd.web10.66.1609801131067894705 for ; Mon, 04 Jan 2021 14:58:51 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=fWRNGZgF; spf=pass (domain: nuviainc.com, ip: 209.85.216.46, mailfrom: rebecca@nuviainc.com) Received: by mail-pj1-f46.google.com with SMTP id m5so525490pjv.5 for ; Mon, 04 Jan 2021 14:58:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j8NFkhaQ4CCJJvKLIlxxFm0rzzg9Q2xcZkih1QSrbFA=; b=fWRNGZgFgzTA8M/pBGwfnzYVrmz69U6M9/XuCI9RPxavyNAKKpF/uZUY1eCh7/5X1P UoLoD4P0E1uriAwChPE2LiWmz2YOD2msqY4PWrDUETqoyoV3Q8fgyBJmyUED0k6jDkdH TuNbmPep9f1AOJWHq/U/nzNITq9OKKKNi6QI3JnYU2iwHiTNrsC/DAeIxzF/zJ3wMvz5 SqCIZSU86BA5mU8lXPaAsGu4SLV6xTcM8oS7U/chAyRc5T0INmRcHyzn6YEhTMBDWX1Z ebjUb81pGpIFJ7o7DgaTYO6AcVY3dtaDhtl3T12LH1QjfSwx8eK928tMSoCeGV0ShpEt VNyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j8NFkhaQ4CCJJvKLIlxxFm0rzzg9Q2xcZkih1QSrbFA=; b=LdCC5w84tboPhBqFPVHrxTaDB3SFRdgH2U7j6R1N9cn6A67zCTX6R1pdsF5/1vqJHa AqupxTESy82WMCAPi3+iTrv9Vjsikz6ajgjL32rRmhuQJHo1G40VapniEVBuJ/JwYYHS HqeYaar+98NYR84q/t5m8escpp8y2uinKxEsdl37ywauj1g+ZKKYWlWn42SHiJHFBjDs nK2BQPe9+ufVAipB9XkI1K2kB/XuGS9Qg3W9AH5OHSAZkXijzkHA7zhbTVMj0odHOQhY kfWuHOqK9M8zKWwJKejRTseF/wIPS6l6ZFJbM9OA+APbBLcYghijHMVI/NMbzamrqqD7 oCSQ== X-Gm-Message-State: AOAM530KzjviWfAC5QU39FqiGzR2rbWAoH5Lj7UmoneDdN27gURpFJhL mB9ZOUST2V581f1zPhX8WYGcUyx6Yg/DsULt6rFlncNP0Itxt0tNKi3r1wv2Cv4pbg/sv7Hv5gP 5HGbn0mZ9n1WR+MmBIMXcJINj7XyKJYD7IxWQ1YKodBcYRI7xOAz/qZ6e3xuSXaxNJFyWaWrD X-Google-Smtp-Source: ABdhPJyHWVAW69se7VJPReV8qtkiG0DwbipeXO8xC0vHnR6LolEdO+OWkdmbv4cylm6y6DKuXf1B9g== X-Received: by 2002:a17:90a:430f:: with SMTP id q15mr1090406pjg.218.1609801130122; Mon, 04 Jan 2021 14:58:50 -0800 (PST) Return-Path: Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id x143sm64185289pgx.66.2021.01.04.14.58.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jan 2021 14:58:49 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Leif Lindholm , Ard Biesheuvel , "nd @ arm . com . Sami Mujawar" , Liming Gao , Michael D Kinney , Zhiguang Liu Subject: [PATCH v5 07/23] ArmPkg: Update ArmLibPrivate.h with cache register definitions Date: Mon, 4 Jan 2021 15:58:14 -0700 Message-Id: <20210104225830.12606-8-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210104225830.12606-1-rebecca@nuviainc.com> References: <20210104225830.12606-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Update the cache definitions in ArmLibPrivate.h based on current ARMv8 documentation. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 97 ++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h index 8959bdd9d73c..5d0224080f3f 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -1,5 +1,7 @@ /** @file + ArmLibPrivate.h + Copyright (c) 2020, NUVIA Inc. All rights reserved.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -50,6 +52,101 @@ #define CACHE_ARCHITECTURE_UNIFIED (0UL) #define CACHE_ARCHITECTURE_SEPARATE (1UL) + +/// Defines the structure of the CSSELR (Cache Size Selection) register +typedef union { + struct { + UINT32 InD :1; ///< Instruction not Data bit + UINT32 Level :3; ///< Cache level (zero based) + UINT32 TnD :1; ///< Allocation not Data bit + UINT32 Reserved :27; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSELR_DATA; + +/// The cache type values for the InD field of the CSSELR register +typedef enum +{ + /// Select the data or unified cache + CsselrCacheTypeDataOrUnified = 0, + /// Select the instruction cache + CsselrCacheTypeInstruction, + CsselrCacheTypeMax +} CSSELR_CACHE_TYPE; + +/// Defines the structure of the CCSIDR (Current Cache Size ID) register +typedef union { + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) + UINT64 Associativity :10; ///< Associativity - 1 + UINT64 NumSets :15; ///< Number of sets in the cache -1 + UINT64 Unknown :4; ///< Reserved, UNKNOWN + UINT64 Reserved :32; ///< Reserved, RES0 + } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported. + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) + UINT64 Associativity :21; ///< Associativity - 1 + UINT64 Reserved1 :8; ///< Reserved, RES0 + UINT64 NumSets :24; ///< Number of sets in the cache -1 + UINT64 Reserved2 :8; ///< Reserved, RES0 + } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported. + struct { + UINT64 LineSize : 3; + UINT64 Associativity : 21; + UINT64 Reserved : 9; + UINT64 Unallocated : 32; + } BitsCcidxAA32; + UINT64 Data; ///< The entire 64-bit value +} CCSIDR_DATA; + +/// Defines the structure of the AARCH32 CCSIDR2 register. +typedef union { + struct { + UINT32 NumSets :24; ///< Number of sets in the cache - 1 + UINT32 Reserved :8; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSIDR2_DATA; + +/** Defines the structure of the CLIDR (Cache Level ID) register. + * + * The lower 32 bits are the same for both AARCH32 and AARCH64 + * so we can use the same structure for both. +**/ +typedef union { + struct { + UINT32 Ctype1 : 3; ///< Level 1 cache type + UINT32 Ctype2 : 3; ///< Level 2 cache type + UINT32 Ctype3 : 3; ///< Level 3 cache type + UINT32 Ctype4 : 3; ///< Level 4 cache type + UINT32 Ctype5 : 3; ///< Level 5 cache type + UINT32 Ctype6 : 3; ///< Level 6 cache type + UINT32 Ctype7 : 3; ///< Level 7 cache type + UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable + UINT32 LoC : 3; ///< Level of Coherency + UINT32 LoUU : 3; ///< Level of Unification Uniprocessor + UINT32 Icb : 3; ///< Inner Cache Boundary + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CLIDR_DATA; + +/// The cache types reported in the CLIDR register. +typedef enum { + /// No cache is present + ClidrCacheTypeNone = 0, + /// There is only an instruction cache + ClidrCacheTypeInstructionOnly, + /// There is only a data cache + ClidrCacheTypeDataOnly, + /// There are separate data and instruction caches + ClidrCacheTypeSeparate, + /// There is a unified cache + ClidrCacheTypeUnified, + ClidrCacheTypeMax +} CLIDR_CACHE_TYPE; + +#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * level)) & 0b111) + VOID CPSRMaskInsert ( IN UINT32 Mask, -- 2.26.2