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From: "Rebecca Cran" <rebecca@nuviainc.com>
To: devel@edk2.groups.io
Cc: Rebecca Cran <rebecca@nuviainc.com>,
Leif Lindholm <leif@nuviainc.com>,
Ard Biesheuvel <ard.biesheuvel@arm.com>,
"nd @ arm . com . Sami Mujawar" <Sami.Mujawar@arm.com>,
Liming Gao <gaoliming@byosoft.com.cn>,
Michael D Kinney <michael.d.kinney@intel.com>,
Zhiguang Liu <zhiguang.liu@intel.com>,
Sami Mujawar <sami.mujawar@arm.com>
Subject: [PATCH v5 08/23] ArmPkg: Add definition of the maximum cache level in ARMv8-A
Date: Mon, 4 Jan 2021 15:58:15 -0700
Message-Id: <20210104225830.12606-9-rebecca@nuviainc.com>
X-Mailer: git-send-email 2.26.2
In-Reply-To: <20210104225830.12606-1-rebecca@nuviainc.com>
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The ARM Architecture Reference Manual for ARMv8-A defines up to
seven levels of cache, L1 through L7.
Define MAX_ARM_CACHE_LEVEL to be 7.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
---
ArmPkg/Include/Library/ArmLib.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 26cb05def0a2..fd4f06d24274 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -109,6 +109,10 @@ typedef enum {
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
+// The ARM Architecture Reference Manual for ARMv8-A defines up
+// to 7 levels of cache, L1 through L7.
+#define MAX_ARM_CACHE_LEVEL 7
+
UINTN
EFIAPI
ArmDataCacheLineLength (
--
2.26.2