From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) by mx.groups.io with SMTP id smtpd.web12.12960.1610242003690204904 for ; Sat, 09 Jan 2021 17:26:44 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=VmIMcXbS; spf=pass (domain: nuviainc.com, ip: 209.85.221.45, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f45.google.com with SMTP id 91so12658884wrj.7 for ; Sat, 09 Jan 2021 17:26:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=ENhIXpJZ/yeSk2kEWgnxUfLkmUs9BI2tbuvmXKm6EQE=; b=VmIMcXbSMLcXCAKpWJ1D6jJquHJS6+Q3mxEOyNcI6/wD3R/74X0Tien480vqCyNId2 gf+PjkruDhMIUaskFG5NaYYMk/dyIEJ3+K+vqTnwzsPfuGhgNyRPrhNVr0DDn1e2+/5Z WuCVnQXrlzb320ZJ2YjRpqnOXT5A3nBohlgnPtkTTCJYXOPlEfzKLx20ytmUQphLZtnh CTKlXd7LidaSTcjWDKI+5uZA98fDUKLA31cONR+Qgfd83BZb+hljL5e+Wwy29nadTRRJ D7fpKcw6dV65tI0UvAQyVVeIx4kxcJBQxKI+t/XQlDqit5oqbq6FPq/bHz8YnVBvg09P 73fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=ENhIXpJZ/yeSk2kEWgnxUfLkmUs9BI2tbuvmXKm6EQE=; b=K03x4f08KGJm3GFhittPhMM4VtO5vGaT9rmaG2vbC/NhzD/29hN0XgBm8h1QFiqO/A 3ZGrxnqJqcq4AdzVviMTb0Lu8+X7s8EihqFtkuhwBZ0w22BHyn5bd6AU74hQ0KOPLMgo HM5qnl3Tw/bzArUKh7Gee/TFoXLKXJXnBpNoxUBswZVR0QHa6l8cP8pP1OC9VfR2oxfq xd0bvXklSgPeR2WFXnx4Sg/1cPiHNu9ThgiqenvHnRYLsAr14bhydAKcdPaoDA9QW6Qy hNugYPri41NaXeDMRt4viAUCHPLavvnO1DuSSM6BCtO3xatQnCb2Vb+hwCJjPT1HSDlZ Ko7w== X-Gm-Message-State: AOAM531DEgiLIiZi6tl/6aXrMsUfm5P6f9vPI34DhjyM+A9uvIZM216u nJoNmij9aefbi9T7iPJYmUFpkg== X-Google-Smtp-Source: ABdhPJwK5Wtp/MwKpRA0bTiAzUWkcobtKKeLZ5yB9CHImm559gzhIhow+slDZlMyPX7ZTBMoarUVIg== X-Received: by 2002:a5d:4bc5:: with SMTP id l5mr10121530wrt.15.1610242002379; Sat, 09 Jan 2021 17:26:42 -0800 (PST) Return-Path: Received: from vanye (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id o3sm17905902wrc.93.2021.01.09.17.26.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jan 2021 17:26:42 -0800 (PST) Date: Sun, 10 Jan 2021 01:26:40 +0000 From: "Leif Lindholm" To: Rebecca Cran Cc: devel@edk2.groups.io, Ard Biesheuvel , "nd @ arm . com . Sami Mujawar" , Liming Gao , Michael D Kinney , Zhiguang Liu Subject: Re: [PATCH v5 03/23] ArmPkg: Add register encoding definition for MMFR2 Message-ID: <20210110012640.GA1664@vanye> References: <20210104225830.12606-1-rebecca@nuviainc.com> <20210104225830.12606-4-rebecca@nuviainc.com> MIME-Version: 1.0 In-Reply-To: <20210104225830.12606-4-rebecca@nuviainc.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Jan 04, 2021 at 15:58:10 -0700, Rebecca Cran wrote: > Add register encoding definition for Memory Model Feature Register 2. > We need to define it here because we build for ARMv8.0, which doesn't > have it. > > Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm > --- > ArmPkg/Include/Chipset/AArch64.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h > index 0ade5cce91c3..7c2b592f92ee 100644 > --- a/ArmPkg/Include/Chipset/AArch64.h > +++ b/ArmPkg/Include/Chipset/AArch64.h > @@ -112,6 +112,10 @@ > #define ARM_VECTOR_LOW_A32_FIQ 0x700 > #define ARM_VECTOR_LOW_A32_SERR 0x780 > > +// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we > +// build for ARMv8.0, we need to define the register here. > +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 > + > #define VECTOR_BASE(tbl) \ > .section .text.##tbl##,"ax"; \ > .align 11; \ > -- > 2.26.2 >