From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) by mx.groups.io with SMTP id smtpd.web12.13389.1610244492844218819 for ; Sat, 09 Jan 2021 18:08:13 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=R6rTp2V1; spf=pass (domain: nuviainc.com, ip: 209.85.221.52, mailfrom: leif@nuviainc.com) Received: by mail-wr1-f52.google.com with SMTP id i9so12722381wrc.4 for ; Sat, 09 Jan 2021 18:08:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=4wzJEh8DSiPCZMZZPV9HzLMr2tnimY96KEbbUsPOqyI=; b=R6rTp2V10xN+Zt2TszvnCv6gjo9I3KYAoyJialX9xnb9FoV9arAkjTCsAEdhHQ3xvk gZEtBF6f+7lCmeK0Mve9Y32+wbN/miz4eDVV3VExPYJLDAK0YfBGiJjhE2LgG7VMNwr6 0E8EMbcmnbnVsXQs1kGAZy9iL3RbpN7lrQW8mPqf5HhHyysjbkvQl496/9U8ynl7QADO OZpZyZf91OZOHyRa0lI2a5EIRpMnyxBT00EsyryZZbKaMJN7VaTFsOGqdQLIL5oJMCb3 FRxzkK9T2ifCsTZmIfnTClxo8jauwoVBQ2L7agqvA0CN1HhKGynpfeFVUcBAidh0PZ7f p3yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=4wzJEh8DSiPCZMZZPV9HzLMr2tnimY96KEbbUsPOqyI=; b=Os722usXnPOdc3QTU0HmqhBRGa57dZyzt35HLLHFC1HgU8IMey6mbo+Tf3FyAAJoXk xnPOW1vUIuyWclCk6QFt0ad33yhWsKzBEZu7uQUuGboydgP2gC724S9OScLBnMaEGdZN sUxmAFg59ra/TXDBad/t/cfhKGkCie2Id58f5pXIAEDmC762zn2bB6WwEj05xRtSVXXX jyn68KRZcrJZsYKRFlTmWkAV35s614INUjLJjznQwquvvdWgmliTZ6G3u3MzHWoUNmb8 4W/eDjXqqaQNOsjX1cyesBe3Bhj+9ZSkp36fW0cJLRR2ZgU3sZtCr73pKi7YzqU1mw6G DGAg== X-Gm-Message-State: AOAM531J4TTUBUGY6ODVrdu+r4FCtGts4fMG8ebY97z1bsHtgKS1Y/v1 L4qt5NTqUsNtv44dgfDRdV4KHA== X-Google-Smtp-Source: ABdhPJwbav7sg3nFPgLoC5EDM3FE6V0Qct4vRnpQfygjBZk2kT92mvRFxER295qItWHftd0pedJ4Dg== X-Received: by 2002:adf:fdcb:: with SMTP id i11mr10323803wrs.349.1610244491334; Sat, 09 Jan 2021 18:08:11 -0800 (PST) Return-Path: Received: from vanye (cpc1-cmbg19-2-0-cust915.5-4.cable.virginm.net. [82.27.183.148]) by smtp.gmail.com with ESMTPSA id u205sm18140127wme.42.2021.01.09.18.08.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Jan 2021 18:08:10 -0800 (PST) Date: Sun, 10 Jan 2021 02:08:09 +0000 From: "Leif Lindholm" To: Rebecca Cran Cc: devel@edk2.groups.io, Ard Biesheuvel , "nd @ arm . com . Sami Mujawar" , Liming Gao , Michael D Kinney , Zhiguang Liu Subject: Re: [PATCH v5 19/23] ArmPkg: Add Library/OemMiscLib.h Message-ID: <20210110020809.GE1664@vanye> References: <20210104225830.12606-1-rebecca@nuviainc.com> <20210104225830.12606-20-rebecca@nuviainc.com> MIME-Version: 1.0 In-Reply-To: <20210104225830.12606-20-rebecca@nuviainc.com> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Jan 04, 2021 at 15:58:26 -0700, Rebecca Cran wrote: > OemMiscLib.h provides the interface which platforms should implement to > interact with the SmbiosMiscDxe and ProcessorSubClassDxe drivers to > update SMBIOS tables. > > Signed-off-by: Rebecca Cran > --- > ArmPkg/Include/Library/OemMiscLib.h | 159 ++++++++++++++++++++ > 1 file changed, 159 insertions(+) > > diff --git a/ArmPkg/Include/Library/OemMiscLib.h b/ArmPkg/Include/Library/OemMiscLib.h > new file mode 100644 > index 000000000000..83562a3ece9d > --- /dev/null > +++ b/ArmPkg/Include/Library/OemMiscLib.h > @@ -0,0 +1,159 @@ > +/** @file > +* > +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. > +* Copyright (c) 2015, Linaro Limited. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > + > +#ifndef OEM_MISC_LIB_H_ > +#define OEM_MISC_LIB_H_ > + > +#include > +#include > + > +typedef enum > +{ Inconsistent opening bracket placement in this file. > + CpuCacheL1 = 0, > + CpuCacheL2, > + CpuCacheL3, > + CpuCacheL4, > + CpuCacheL5, > + CpuCacheL6, > + CpuCacheL7, > + CpuCacheLevelMax > +} CPU_CACHE_LEVEL; Needs OEMMISC/OEM_MISC prefix, or possibly OEM - which applies below too. / Leif > + > +typedef struct > +{ > + UINT8 Voltage; ///< Processor voltage > + UINT16 CurrentSpeed; ///< Current clock speed in MHz > + UINT16 MaxSpeed; ///< Maximum clock speed in MHz > + UINT16 ExternalClock; ///< External clock speed in MHz > + UINT16 CoreCount; ///< Number of cores available > + UINT16 CoresEnabled; ///< Number of cores enabled > + UINT16 ThreadCount; ///< Number of threads per processor > +} MISC_PROCESSOR_DATA; > + > +typedef enum { > + ProductNameType01, > + SerialNumType01, > + UuidType01, > + SystemManufacturerType01, > + AssertTagType02, > + SerialNumberType02, > + BoardManufacturerType02, > + AssetTagType03, > + SerialNumberType03, > + VersionType03, > + ChassisTypeType03, > + ManufacturerType03, > + SmbiosHiiStringFieldMax > +} SMBIOS_HII_STRING_FIELD; > + > +/* > + * The following are functions that the each platform needs to > + * implement in its OemMiscLib library. > + */ > + > +/** Gets the CPU frequency of the specified processor. > + > + @param ProcessorIndex Index of the processor to get the frequency for. > + > + @return CPU frequency in Hz > +**/ > +EFIAPI > +UINTN > +OemGetCpuFreq ( > + IN UINT8 ProcessorIndex > + ); > + > +/** Gets information about the specified processor and stores it in > + the structures provided. > + > + @param ProcessorIndex Index of the processor to get the information for. > + @param ProcessorStatus Processor status. > + @param ProcessorCharacteristics Processor characteritics. > + @param MiscProcessorData Miscellaneous processor information. > + > + @return TRUE on success, FALSE on failure. > +**/ > +EFIAPI > +BOOLEAN > +OemGetProcessorInformation ( > + IN UINTN ProcessorIndex, > + IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus, > + IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics, > + IN OUT MISC_PROCESSOR_DATA *MiscProcessorData > + ); > + > +/** Gets information about the cache at the specified cache level. > + > + @param ProcessorIndex The processor to get information for. > + @param CacheLevel The cache level to get information for. > + @param InstructionOrUnifiedCache Whether the cache is instruction or > + unified, not data. > + @param SmbiosCacheTable The SMBIOS Type7 cache information structure. > + > + @return TRUE on success, FALSE on failure. > +**/ > +EFIAPI > +BOOLEAN > +OemGetCacheInformation ( > + IN UINT8 ProcessorIndex, > + IN UINT8 CacheLevel, > + IN BOOLEAN InstructionOrUnifiedCache, > + IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable > + ); > + > +/** Gets the maximum number of sockets supported by the platform. > + > + @return The maximum number of sockets. > +**/ > +EFIAPI > +UINT8 > +OemGetProcessorMaxSockets ( > + VOID > + ); > + > +/** Gets the type of chassis for the system. > + > + @param ChassisType The type of the chassis. > + > + @retval EFI_SUCCESS The chassis type was fetched successfully. > +**/ > +EFIAPI > +EFI_STATUS > +OemGetChassisType ( > + OUT UINT8 *ChassisType > + ); > + > +/** Returns whether the specified processor is present or not. > + > + @param ProcessIndex The processor index to check. > + > + @return TRUE is the processor is present, FALSE otherwise. > +**/ > +EFIAPI > +BOOLEAN > +OemIsSocketPresent ( > + IN UINTN ProcessorIndex > + ); > + > +/** Updates the HII string for the specified field. > + > + @param mHiiHandle The HII handle. > + @param TokenToUpdate The string to update. > + @param Offset The field to get information about. > +**/ > +EFIAPI > +VOID > +UpdateSmbiosInfo ( > + IN EFI_HII_HANDLE mHiiHandle, > + IN EFI_STRING_ID TokenToUpdate, > + IN SMBIOS_HII_STRING_FIELD Offset > + ); > + > +#endif // OEM_MISC_LIB_H_ > -- > 2.26.2 >