* [RFC 1/3] rpi4: Add XHCI/PCI selection menu
2021-01-12 22:27 [RFC 0/3] Rpi4: Enable ACPI PCIe conduit Jeremy Linton
@ 2021-01-12 22:27 ` Jeremy Linton
2021-02-08 17:39 ` [edk2-devel] " Andrei Warkentin
2021-01-12 22:27 ` [RFC 2/3] rpi4/acpi/dsdt: break XHCI into its own SSDT Jeremy Linton
2021-01-12 22:27 ` [RFC 3/3] rpi4/acpi: Add PCIe SSDT Jeremy Linton
2 siblings, 1 reply; 5+ messages in thread
From: Jeremy Linton @ 2021-01-12 22:27 UTC (permalink / raw)
To: devel
Cc: pete, awarkentin, samer.el-haj-mahmoud, leif, ard.biesheuvel,
Jeremy Linton
ARM has standardized a SMC PCI conduit that can be used
to access the PCI config space in a standardized way. This
functionality doesn't yet exist in many OS/Distro's. Lets
add another advanced config item that allows the user
to toggle between presenting the XHCI on the base rpi4
as a platform device, or presenting this newer PCIe
conduit.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 32 ++++++++++++++++++++++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf | 3 ++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni | 5 ++++
.../RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr | 13 +++++++++
Platform/RaspberryPi/Include/ConfigVars.h | 4 +++
Platform/RaspberryPi/RPi3/RPi3.dsc | 9 ++++++
Platform/RaspberryPi/RPi4/RPi4.dsc | 11 ++++++++
Platform/RaspberryPi/RaspberryPi.dec | 3 ++
8 files changed, 80 insertions(+)
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 6fcbdcdd17..7a3b8e9068 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -266,6 +266,38 @@ SetupVariables (
ASSERT_EFI_ERROR (Status);
}
+ if (mModelFamily >= 4) {
+ Size = sizeof (UINT32);
+ Status = gRT->GetVariable (L"XhciPci",
+ &gConfigDxeFormSetGuid,
+ NULL, &Size, &Var32);
+ if (EFI_ERROR (Status) || (Var32 != 2)) {
+ // enable Xhci by default
+ Status = PcdSet32S (PcdXhciPci, 1);
+ ASSERT_EFI_ERROR (Status);
+ Status = PcdSet32S (PcdXhci, 1);
+ ASSERT_EFI_ERROR (Status);
+ Status = PcdSet32S (PcdPci, 0);
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ // enable PCIe
+ Status = PcdSet32S (PcdXhciPci, 2);
+ ASSERT_EFI_ERROR (Status);
+ Status = PcdSet32S (PcdXhci, 0);
+ ASSERT_EFI_ERROR (Status);
+ Status = PcdSet32S (PcdPci, 1);
+ ASSERT_EFI_ERROR (Status);
+ }
+ } else {
+ // disable pcie and xhci
+ Status = PcdSet32S (PcdXhciPci, 0);
+ ASSERT_EFI_ERROR (Status);
+ Status = PcdSet32S (PcdXhci, 0);
+ ASSERT_EFI_ERROR (Status);
+ Status = PcdSet32S (PcdPci, 0);
+ ASSERT_EFI_ERROR (Status);
+ }
+
Size = sizeof (AssetTagVar);
Status = gRT->GetVariable (L"AssetTag",
&gConfigDxeFormSetGuid,
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
index 544e3b3e10..aa0fbc7e25 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.inf
@@ -92,6 +92,9 @@
gRaspberryPiTokenSpaceGuid.PcdRamLimitTo3GB
gRaspberryPiTokenSpaceGuid.PcdFanOnGpio
gRaspberryPiTokenSpaceGuid.PcdFanTemp
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci
+ gRaspberryPiTokenSpaceGuid.PcdXhci
+ gRaspberryPiTokenSpaceGuid.PcdPci
[Depex]
gPcdProtocolGuid AND gRaspberryPiFirmwareProtocolGuid
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
index 2afe8f32ae..34efb82f57 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.uni
@@ -57,6 +57,11 @@
#string STR_ADVANCED_FANTEMP_PROMPT #language en-US "ACPI fan temperature"
#string STR_ADVANCED_FANTEMP_HELP #language en-US "Cycle a fan at C"
+#string STR_ADVANCED_XHCIPCI_PROMPT #language en-US "ACPI XHCI/PCIe"
+#string STR_ADVANCED_XHCIPCI_HELP #language en-US "OS sees XHCI USB platform device or PCIe bridge"
+#string STR_ADVANCED_XHCIPCI_XHCI #language en-US "XHCI"
+#string STR_ADVANCED_XHCIPCI_PCIE #language en-US "PCIe"
+
#string STR_ADVANCED_ASSET_TAG_PROMPT #language en-US "Asset Tag"
#string STR_ADVANCED_ASSET_TAG_HELP #language en-US "Set the system Asset Tag"
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
index de5e43471a..4d5876eb24 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxeHii.vfr
@@ -56,6 +56,11 @@ formset
name = FanTemp,
guid = CONFIGDXE_FORM_SET_GUID;
+ efivarstore ADVANCED_XHCIPCI_VARSTORE_DATA,
+ attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+ name = XhciPci,
+ guid = CONFIGDXE_FORM_SET_GUID;
+
efivarstore SYSTEM_TABLE_MODE_VARSTORE_DATA,
attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
name = SystemTableMode,
@@ -207,6 +212,14 @@ formset
default = 60,
endnumeric;
endif;
+
+ oneof varid = XhciPci.Value,
+ prompt = STRING_TOKEN(STR_ADVANCED_XHCIPCI_PROMPT),
+ help = STRING_TOKEN(STR_ADVANCED_XHCIPCI_HELP),
+ flags = NUMERIC_SIZE_4 | INTERACTIVE | RESET_REQUIRED,
+ option text = STRING_TOKEN(STR_ADVANCED_XHCIPCI_XHCI), value = 1, flags = DEFAULT;
+ option text = STRING_TOKEN(STR_ADVANCED_XHCIPCI_PCIE), value = 2, flags = 0;
+ endoneof;
#endif
string varid = AssetTag.AssetTag,
prompt = STRING_TOKEN(STR_ADVANCED_ASSET_TAG_PROMPT),
diff --git a/Platform/RaspberryPi/Include/ConfigVars.h b/Platform/RaspberryPi/Include/ConfigVars.h
index c185bfe28b..eb08ad8987 100644
--- a/Platform/RaspberryPi/Include/ConfigVars.h
+++ b/Platform/RaspberryPi/Include/ConfigVars.h
@@ -77,6 +77,10 @@ typedef struct {
} ADVANCED_FANTEMP_VARSTORE_DATA;
typedef struct {
+ UINT32 Value;
+} ADVANCED_XHCIPCI_VARSTORE_DATA;
+
+typedef struct {
#define SYSTEM_TABLE_MODE_ACPI 0
#define SYSTEM_TABLE_MODE_BOTH 1
#define SYSTEM_TABLE_MODE_DT 2
diff --git a/Platform/RaspberryPi/RPi3/RPi3.dsc b/Platform/RaspberryPi/RPi3/RPi3.dsc
index 530b42796a..0aeb27d69d 100644
--- a/Platform/RaspberryPi/RPi3/RPi3.dsc
+++ b/Platform/RaspberryPi/RPi3/RPi3.dsc
@@ -514,6 +514,15 @@
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberryPiTokenSpaceGuid|0x0|0
+ # Select XHCI/PCIe mode (not valid on rpi3)
+ #
+ # 0 - DISABLED
+ #
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0x0|0
+ # SSDT selectors
+ gRaspberryPiTokenSpaceGuid.PcdXhci|L"Xhci"|gConfigDxeFormSetGuid|0x0|0
+ gRaspberryPiTokenSpaceGuid.PcdPci|L"Pci"|gConfigDxeFormSetGuid|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4/RPi4.dsc
index 0cd1014095..d5952288cc 100644
--- a/Platform/RaspberryPi/RPi4/RPi4.dsc
+++ b/Platform/RaspberryPi/RPi4/RPi4.dsc
@@ -528,6 +528,17 @@
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|L"ResetDelay"|gRaspberryPiTokenSpaceGuid|0x0|0
+ # Select XHCI/PCIe mode
+ #
+ # 0 - DISABLED (not valid for rpi4)
+ # 1 - Xhci Enabled (default)
+ # 2 - Pcie Enabled
+ #
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|L"XhciPci"|gConfigDxeFormSetGuid|0x0|1
+ # SSDT selectors
+ gRaspberryPiTokenSpaceGuid.PcdXhci|L"Xhci"|gConfigDxeFormSetGuid|0x0|1
+ gRaspberryPiTokenSpaceGuid.PcdPci|L"Pci"|gConfigDxeFormSetGuid|0x0|0
+
#
# Common UEFI ones.
#
diff --git a/Platform/RaspberryPi/RaspberryPi.dec b/Platform/RaspberryPi/RaspberryPi.dec
index 10723036aa..6c7d4e5116 100644
--- a/Platform/RaspberryPi/RaspberryPi.dec
+++ b/Platform/RaspberryPi/RaspberryPi.dec
@@ -69,3 +69,6 @@
gRaspberryPiTokenSpaceGuid.PcdFanOnGpio|0|UINT32|0x0000001C
gRaspberryPiTokenSpaceGuid.PcdFanTemp|0|UINT32|0x0000001D
gRaspberryPiTokenSpaceGuid.PcdPlatformResetDelay|0|UINT32|0x0000001E
+ gRaspberryPiTokenSpaceGuid.PcdXhci|0|UINT32|0x0000001F
+ gRaspberryPiTokenSpaceGuid.PcdPci|0|UINT32|0x00000020
+ gRaspberryPiTokenSpaceGuid.PcdXhciPci|0|UINT32|0x00000021
--
2.13.7
^ permalink raw reply related [flat|nested] 5+ messages in thread* [RFC 2/3] rpi4/acpi/dsdt: break XHCI into its own SSDT
2021-01-12 22:27 [RFC 0/3] Rpi4: Enable ACPI PCIe conduit Jeremy Linton
2021-01-12 22:27 ` [RFC 1/3] rpi4: Add XHCI/PCI selection menu Jeremy Linton
@ 2021-01-12 22:27 ` Jeremy Linton
2021-01-12 22:27 ` [RFC 3/3] rpi4/acpi: Add PCIe SSDT Jeremy Linton
2 siblings, 0 replies; 5+ messages in thread
From: Jeremy Linton @ 2021-01-12 22:27 UTC (permalink / raw)
To: devel
Cc: pete, awarkentin, samer.el-haj-mahmoud, leif, ard.biesheuvel,
Jeremy Linton
Lets prepare to switch between XHCI and PCI by moving
the XHCI definition into its own SSDT. That way we can
select it based on the menu settings.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 1 +
Platform/RaspberryPi/AcpiTables/Dsdt.asl | 4 +--
Platform/RaspberryPi/AcpiTables/Xhci.asl | 33 ++++++++++++++--------
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 5 ++++
4 files changed, 28 insertions(+), 15 deletions(-)
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index 2867c83b71..17dee581a0 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -36,6 +36,7 @@
Pptt.aslc
Pcct.aslc
SsdtThermal.asl
+ Xhci.asl
[Packages]
ArmPkg/ArmPkg.dec
diff --git a/Platform/RaspberryPi/AcpiTables/Dsdt.asl b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
index ae3bd129d6..5a665d7dd1 100644
--- a/Platform/RaspberryPi/AcpiTables/Dsdt.asl
+++ b/Platform/RaspberryPi/AcpiTables/Dsdt.asl
@@ -63,9 +63,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 5, "RPIFDN", "RPI", 2)
Scope (\_SB_)
{
include ("Pep.asl")
-#if (RPI_MODEL == 4)
- include ("Xhci.asl")
-#endif
+
Method (_OSC, 4, Serialized) { // _OSC: Operating System Capabilities
CreateDWordField (Arg3, 0x00, STS0)
CreateDWordField (Arg3, 0x04, CAP0)
diff --git a/Platform/RaspberryPi/AcpiTables/Xhci.asl b/Platform/RaspberryPi/AcpiTables/Xhci.asl
index bc3fea60f9..6d18adf590 100644
--- a/Platform/RaspberryPi/AcpiTables/Xhci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Xhci.asl
@@ -9,6 +9,8 @@
#include <IndustryStandard/Bcm2711.h>
+#include "AcpiTables.h"
+
/*
* The following can be used to remove parenthesis from
* defined macros that the compiler complains about.
@@ -24,12 +26,17 @@
*/
#define XHCI_REG_LENGTH 0x1000
-Device (SCB0) {
- Name (_HID, "ACPI0004")
- Name (_UID, 0x0)
- Name (_CCA, 0x0)
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4XHCI", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
- Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+ Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
/*
* Container devices with _DMA must have _CRS, meaning SCB0
* to provide all resources that XHC0 consumes (except
@@ -57,9 +64,9 @@ Device (SCB0) {
Add (MMBE, XHCI_REG_LENGTH - 1, MMBE)
Add (MMLE, XHCI_REG_LENGTH - 1, MMLE)
Return (RBUF)
- }
+ }
- Name (_DMA, ResourceTemplate() {
+ Name (_DMA, ResourceTemplate() {
/*
* XHC0 is limited to DMA to first 3GB. Note this
* only applies to PCIe, not GENET or other devices
@@ -79,10 +86,10 @@ Device (SCB0) {
,
,
)
- })
+ })
- Device (XHC0)
- {
+ Device (XHC0)
+ {
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x0) // _UID: Unique ID
Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute
@@ -131,5 +138,7 @@ Device (SCB0) {
Debug = "xHCI enable"
Store (0x6, CMND)
}
- }
-}
+ } // end XHC0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 7a3b8e9068..f13abd67c0 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -755,6 +755,11 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
SsdtNameOpReplace
},
{
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'X', 'H', 'C', 'I'),
+ PcdToken(PcdXhci),
+ NULL
+ },
+ {
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
0,
NULL
--
2.13.7
^ permalink raw reply related [flat|nested] 5+ messages in thread* [RFC 3/3] rpi4/acpi: Add PCIe SSDT
2021-01-12 22:27 [RFC 0/3] Rpi4: Enable ACPI PCIe conduit Jeremy Linton
2021-01-12 22:27 ` [RFC 1/3] rpi4: Add XHCI/PCI selection menu Jeremy Linton
2021-01-12 22:27 ` [RFC 2/3] rpi4/acpi/dsdt: break XHCI into its own SSDT Jeremy Linton
@ 2021-01-12 22:27 ` Jeremy Linton
2 siblings, 0 replies; 5+ messages in thread
From: Jeremy Linton @ 2021-01-12 22:27 UTC (permalink / raw)
To: devel
Cc: pete, awarkentin, samer.el-haj-mahmoud, leif, ard.biesheuvel,
Jeremy Linton
Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port, on a machine without
a MADT it attempts to connect to the SMC conduit. This definition
doesn't have any power mgmt, and only provides a description of
the root port.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +
Platform/RaspberryPi/AcpiTables/Pci.asl | 239 +++++++++++++++++++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 5 +
3 files changed, 247 insertions(+)
create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index 17dee581a0..d261861e59 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -37,6 +37,7 @@
Pcct.aslc
SsdtThermal.asl
Xhci.asl
+ Pci.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -57,6 +58,8 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
new file mode 100644
index 0000000000..71b90d6958
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,239 @@
+/** @file
+ *
+ * Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ * Copyright (c) 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Bcm2711.h>
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...) __VA_ARGS__
+#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW) // 600000000
+#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN) // 03ffffff
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN) // f8000000
+
+/*
+ * According to UEFI boot log for the VLI device on Pi 4.
+ */
+#define XHCI_REG_LENGTH 0x1000
+
+// copy paste job from juno
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
+ Link, /* Interrupt allocated via Link device. */ \
+ Zero /* global system interrupt number (no used) */ \
+ }
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link)
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Method (_CRS, 0, Serialized) {
+ // Container devices with _DMA must have _CRS,
+ // meaning SCB0 to provide all resources that
+ // PCI0 consumes (except interrupts).
+ Name (RBUF, ResourceTemplate () {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX
+ 0x0,
+ 0x1, // LEN
+ ,
+ ,
+ MMIO
+ )
+ })
+ CreateQwordField (RBUF, MMIO._MAX, MMBE)
+ CreateQwordField (RBUF, MMIO._LEN, MMLE)
+ Add (MMBE, XHCI_REG_LENGTH - 1, MMBE)
+ Add (MMLE, XHCI_REG_LENGTH - 1, MMLE)
+ Return (RBUF)
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ // PCIe is limited to DMA to first 3GB. Note this
+ // only applies to PCIe, not GENET or other devices
+ QWordMemory (ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ //
+ // PCI Root Complex
+ //
+ LNK_DEVICE(1, LNKA, 175)
+ LNK_DEVICE(2, LNKB, 176) //todo check int b,c,d values
+ LNK_DEVICE(3, LNKC, 177)
+ LNK_DEVICE(4, LNKD, 178)
+
+ Device(PCI0)
+ {
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 0) // mark the PCI noncoherent
+
+ // Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ QWordMemory (ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKA), // INTA
+ ROOT_PRT_ENTRY(1, LNKB), // INTB
+ ROOT_PRT_ENTRY(2, LNKC), // INTC
+ ROOT_PRT_ENTRY(3, LNKD), // INTD
+ })
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ QWordMemory ( // 32-bit BAR Windows in 64-bit addr
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, //cacheable? is that right?
+ 0x00000000, // Granularity
+ 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
+ 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
+ 2 // SANITIZED_PCIE_MMIO_LEN + 1
+ ,,,MMI1,,TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ // Work around ASL's inability to add in a resource definition
+ // or for that matter compute the min,max,len properly
+ CreateQwordField (RBUF, MMI1._MIN, MMIB)
+ CreateQwordField (RBUF, MMI1._MAX, MMIE)
+ CreateQwordField (RBUF, MMI1._TRA, MMIT)
+ CreateQwordField (RBUF, MMI1._LEN, MMIL)
+ Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
+ Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
+ Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
+ Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
+
+ Return (RBUF)
+ } // Method(_CRS)
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ // See [1] 6.2.10, [2] 4.5
+ Method(_OSC,4) {
+ // Note, This code is very similar to the code in the PCIe firmware
+ // specification which can be used as a reference
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ // Mask out Native HotPlug
+ And(CTRL,0x1E,CTRL)
+ // Always allow native PME, AER (no dependencies)
+
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+ } // PCI0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index f13abd67c0..87ad0fc816 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -760,6 +760,11 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
NULL
},
{
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
+ PcdToken(PcdPci),
+ NULL
+ },
+ {
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
0,
NULL
--
2.13.7
^ permalink raw reply related [flat|nested] 5+ messages in thread