From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) by mx.groups.io with SMTP id smtpd.web11.6231.1610534033959322406 for ; Wed, 13 Jan 2021 02:33:54 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: huawei.com, ip: 45.249.212.191, mailfrom: cenjiahui@huawei.com) Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4DG3g73kWzzj6wq; Wed, 13 Jan 2021 18:32:51 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.498.0; Wed, 13 Jan 2021 18:33:43 +0800 From: "Jiahui Cen" To: CC: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Rebecca Cran , Peter Grehan , Anthony Perard , Julien Grall , Leif Lindholm , Sami Mujawar , , , Jiahui Cen , Yubo Miao Subject: [PATCH v5 06/10] ArmVirtPkg/FdtPciHostBridgeLib: Refactor Init/UninitRootBridge() Date: Wed, 13 Jan 2021 18:33:27 +0800 Message-ID: <20210113103331.10375-7-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210113103331.10375-1-cenjiahui@huawei.com> References: <20210113103331.10375-1-cenjiahui@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Content-Type: text/plain Content-Transfer-Encoding: quoted-printable Rebase ArmVirtPkg/FdtPciHostBridgeLib to the new PciHostBridgeUtilityInitRootBridge()/PciHostBridgeUtilityUninitRootBridge= () functions. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3059 Cc: Laszlo Ersek Cc: Ard Biesheuvel Cc: Leif Lindholm Signed-off-by: Jiahui Cen Signed-off-by: Yubo Miao --- ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf | 1 + ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 124 +++= +++++++---------- 2 files changed, 61 insertions(+), 64 deletions(-) diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.i= nf b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf index 01d39626d14c..b813a0851d2a 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf @@ -34,6 +34,7 @@ [Packages] OvmfPkg/OvmfPkg.dec =20 [LibraryClasses] + BaseMemoryLib DebugLib DevicePathLib DxeServicesTableLib diff --git a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c= b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c index d554479bf0de..3ec7992b6331 100644 --- a/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c +++ b/ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c @@ -7,6 +7,7 @@ =20 **/ #include +#include #include #include #include @@ -20,37 +21,6 @@ #include #include =20 -#pragma pack(1) -typedef struct { - ACPI_HID_DEVICE_PATH AcpiDevicePath; - EFI_DEVICE_PATH_PROTOCOL EndDevicePath; -} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; -#pragma pack () - -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath =3D { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A03), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } -}; - // // We expect the "ranges" property of "pci-host-ecam-generic" to consist= of // records like this. @@ -319,11 +289,18 @@ PciHostBridgeGetRootBridges ( UINTN *Count ) { - UINT64 IoBase, IoSize; - UINT64 Mmio32Base, Mmio32Size; - UINT64 Mmio64Base, Mmio64Size; - UINT32 BusMin, BusMax; - EFI_STATUS Status; + UINT64 IoBase, IoSize; + UINT64 Mmio32Base, Mmio32Size; + UINT64 Mmio64Base, Mmio64Size; + UINT32 BusMin, BusMax; + EFI_STATUS Status; + UINT64 Attributes; + UINT64 AllocationAttributes; + PCI_ROOT_BRIDGE_APERTURE Io; + PCI_ROOT_BRIDGE_APERTURE Mem; + PCI_ROOT_BRIDGE_APERTURE MemAbove4G; + PCI_ROOT_BRIDGE_APERTURE PMem; + PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; =20 if (PcdGet64 (PcdPciExpressBaseAddress) =3D=3D 0) { DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION_= _)); @@ -341,33 +318,29 @@ PciHostBridgeGetRootBridges ( return NULL; } =20 - *Count =3D 1; + ZeroMem (&Io, sizeof (Io)); + ZeroMem (&Mem, sizeof (Mem)); + ZeroMem (&MemAbove4G, sizeof (MemAbove4G)); + ZeroMem (&PMem, sizeof (PMem)); + ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G)); =20 - mRootBridge.Segment =3D 0; - mRootBridge.Supports =3D EFI_PCI_ATTRIBUTE_ISA_IO_16 | - EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_= IO | - EFI_PCI_ATTRIBUTE_VGA_IO_16 | - EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_1= 6; - mRootBridge.Attributes =3D mRootBridge.Supports; + Attributes =3D EFI_PCI_ATTRIBUTE_ISA_IO_16 | + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | + EFI_PCI_ATTRIBUTE_VGA_IO_16 | + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; =20 - mRootBridge.DmaAbove4G =3D TRUE; - mRootBridge.NoExtendedConfigSpace =3D FALSE; - mRootBridge.ResourceAssigned =3D FALSE; + AllocationAttributes =3D EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM; =20 - mRootBridge.AllocationAttributes =3D EFI_PCI_HOST_BRIDGE_COMBINE_MEM_= PMEM; - - mRootBridge.Bus.Base =3D BusMin; - mRootBridge.Bus.Limit =3D BusMax; - mRootBridge.Io.Base =3D IoBase; - mRootBridge.Io.Limit =3D IoBase + IoSize - 1; - mRootBridge.Mem.Base =3D Mmio32Base; - mRootBridge.Mem.Limit =3D Mmio32Base + Mmio32Size - 1; + Io.Base =3D IoBase; + Io.Limit =3D IoBase + IoSize - 1; + Mem.Base =3D Mmio32Base; + Mem.Limit =3D Mmio32Base + Mmio32Size - 1; =20 if (sizeof (UINTN) =3D=3D sizeof (UINT64)) { - mRootBridge.MemAbove4G.Base =3D Mmio64Base; - mRootBridge.MemAbove4G.Limit =3D Mmio64Base + Mmio64Size - 1; + MemAbove4G.Base =3D Mmio64Base; + MemAbove4G.Limit =3D Mmio64Base + Mmio64Size - 1; if (Mmio64Size > 0) { - mRootBridge.AllocationAttributes |=3D EFI_PCI_HOST_BRIDGE_MEM64_DE= CODE; + AllocationAttributes |=3D EFI_PCI_HOST_BRIDGE_MEM64_DECODE; } } else { // @@ -376,19 +349,41 @@ PciHostBridgeGetRootBridges ( // BARs unless they are allocated below 4 GB. So ignore the range ab= ove // 4 GB in this case. // - mRootBridge.MemAbove4G.Base =3D MAX_UINT64; - mRootBridge.MemAbove4G.Limit =3D 0; + MemAbove4G.Base =3D MAX_UINT64; + MemAbove4G.Limit =3D 0; } =20 // // No separate ranges for prefetchable and non-prefetchable BARs // - mRootBridge.PMem.Base =3D MAX_UINT64; - mRootBridge.PMem.Limit =3D 0; - mRootBridge.PMemAbove4G.Base =3D MAX_UINT64; - mRootBridge.PMemAbove4G.Limit =3D 0; + PMem.Base =3D MAX_UINT64; + PMem.Limit =3D 0; + PMemAbove4G.Base =3D MAX_UINT64; + PMemAbove4G.Limit =3D 0; =20 - mRootBridge.DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBri= dgeDevicePath; + Status =3D PciHostBridgeUtilityInitRootBridge ( + Attributes, + Attributes, + AllocationAttributes, + TRUE, + FALSE, + BusMin, + BusMax, + &Io, + &Mem, + &MemAbove4G, + &PMem, + &PMemAbove4G, + &mRootBridge + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a: failed to initialize PCI host bridge: %r\n= ", + __FUNCTION__, Status)); + *Count =3D 0; + return NULL; + } + + *Count =3D 1; =20 return &mRootBridge; } @@ -408,6 +403,7 @@ PciHostBridgeFreeRootBridges ( ) { ASSERT (Count =3D=3D 1); + PciHostBridgeUtilityUninitRootBridge (Bridges); } =20 /** --=20 2.29.2