From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-io1-f45.google.com (mail-io1-f45.google.com [209.85.166.45]) by mx.groups.io with SMTP id smtpd.web09.4092.1610642200405137485 for ; Thu, 14 Jan 2021 08:36:40 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=VrUvsUm3; spf=pass (domain: nuviainc.com, ip: 209.85.166.45, mailfrom: rebecca@nuviainc.com) Received: by mail-io1-f45.google.com with SMTP id z5so12310770iob.11 for ; Thu, 14 Jan 2021 08:36:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D2gEjFelyPSjnUpcU9RoYvNbAEFfhxFoj8ehlO3TW7A=; b=VrUvsUm3YWQJhyAsybSzBTFvZMFLsZcoFn0BBGztY1t3vmWYxfbvq3t0Up6ehq8CUz UBx15pjdmhf0WXrSDvRQYg3BL2zVi9XbDFsyyn283INevo+vVBzmzBbkzkD+69UVOzFt Hjv2+9/SqJhZbuligAKYNCMZZwXIkU4gT2d4ejgkMnbJlkWWc6yvSt8LBPnjs/FAR9gM XkzuJDCPdSURrjFgXxRDwNQrIWEyy5z14R6eToGLL/0kkApbC8A/yJXqb2NOfDJFgWio +oTsx1JMXBXGc+Cvl+41PeZIbeVVXa3fIzmwOvjwCCAE+jKZkchckwxI34owPIHMhXNh 2XQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D2gEjFelyPSjnUpcU9RoYvNbAEFfhxFoj8ehlO3TW7A=; b=Z6zs+evXEderpRNIJvMq8MZd7HfE3Q30QPiLllM3QJlgmTKvn8cY+WsPbGjKmmnbYw WSy1AHYfy2I/bUteG2QBizLArR8Hifqb2J8px4EtMlmnEursWZZl51fXXt9YoGUz8dGc lrAcP2eGK7Sbnz7B6IgDVht3XQf9IH42gnzdurLGmaN1RaGujOuFI1Gcmly2hOOwJFR0 7ReqWAyKoF616JGgrnGIAvlKHdn83zOLhPv5IgQ/KvzykIerESZMUBXyMEdtbzRhOxFK TKXMYffHp1aqaBzpiVHIGmo2kOpesvTHCBfFdhPoFfOgTPGcRXipkHuCZckFhpjyP7dJ JM7Q== X-Gm-Message-State: AOAM531fBp6QGsCoVEuPB/XhmBXOgU8CdDMu6+5oTyP0Od/+IMCY4js7 ATC03/Qmm0luJf0Ol68Zj4gpnG27csp5Q1Dvkl/KstZnGMqOzHgYunFaphGHXMdjMKDL57y6Y8o Ii50kYDo/x/1XZdNhvuGT96m6jaysRtS4IYkthBDtFDqGEj94UiDyGTuonwhaiI8oeb/q8chd X-Google-Smtp-Source: ABdhPJzsXQxsMS91jABErXNpL2fKmbOcw6THFnome6FRtZQkdfE1Ipx1DZAb4dal6wgGwK5Jrdd7rA== X-Received: by 2002:a6b:fe19:: with SMTP id x25mr5771038ioh.78.1610642199544; Thu, 14 Jan 2021 08:36:39 -0800 (PST) Return-Path: Received: from cube.nuviainc.com (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id y5sm3711920ilj.35.2021.01.14.08.36.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Jan 2021 08:36:39 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , Leif Lindholm , Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Sami Mujawar Subject: [PATCH v6 04/22] ArmPkg: Add register encoding definition for MMFR2 Date: Thu, 14 Jan 2021 09:36:10 -0700 Message-Id: <20210114163628.31952-5-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210114163628.31952-1-rebecca@nuviainc.com> References: <20210114163628.31952-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add register encoding definition for Memory Model Feature Register 2. We need to define it here because we build for ARMv8.0, which doesn't have it. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/Chipset/AArch64.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h index 0ade5cce91c3..7c2b592f92ee 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -112,6 +112,10 @@ #define ARM_VECTOR_LOW_A32_FIQ 0x700 #define ARM_VECTOR_LOW_A32_SERR 0x780 +// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we +// build for ARMv8.0, we need to define the register here. +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + #define VECTOR_BASE(tbl) \ .section .text.##tbl##,"ax"; \ .align 11; \ -- 2.26.2