From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by mx.groups.io with SMTP id smtpd.web08.1453.1610700541600381274 for ; Fri, 15 Jan 2021 00:49:02 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: phytium.com.cn, ip: 206.189.21.223, mailfrom: jialing@phytium.com.cn) Received: from localhost.localdomain (unknown [117.136.88.47]) by c1app12 (Coremail) with SMTP id DAINCgDHzpbFVgFgExlyBA--.39669S4; Fri, 15 Jan 2021 16:48:52 +0800 (CST) From: Ling Jia To: devel@edk2.groups.io Cc: Leif Lindholm , Ling , Peng Xie , Yiqi Shu Subject: [PATCH v1 02/10] Silicon/Phytium: Added Acpi support to Phytium2000-4 Date: Fri, 15 Jan 2021 08:47:54 +0000 Message-Id: <20210115084802.62196-3-jialing@phytium.com.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115084802.62196-1-jialing@phytium.com.cn> References: <20210115084802.62196-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: DAINCgDHzpbFVgFgExlyBA--.39669S4 X-Coremail-Antispam: 1UD129KBjvAXoWDXry5uFW8Wr18tF18Gw1xXwb_yoW7WFW8Ao WI9an2q3y8WFsFv3yrZ3yDKF4UurnxuayYkwn7u3y5ZF9xXw15tF97Xa15Xryagr1DKrnx GrWxta4rZF4xK34kn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYK7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r15M28IrcIa0x kI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJw A2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26F4UJVW0 owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE14v_GFyl42 xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWU GwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4U MIIF0xvE42xK8VAvwI8IcIk0rVW8JVW3JwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU8LvtDUUUU X-Originating-IP: [117.136.88.47] X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable From: Ling Added Acpi driver and table to Phytium2000-4, the ACPI Tables providing library AcpiTables.inf uses a lot of information that is available in the form of PCDs for differnt platforms. Cc: Leif Lindholm Signed-off-by: Ling Jia Signed-off-by: Peng Xie Reviewed-by: Yiqi Shu --- Platform/Phytium/Durian/DurianPkg.dsc = | 7 + Platform/Phytium/Durian/DurianPkg.fdf = | 7 + Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf = | 58 +++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf = | 61 +++++ Silicon/Phytium/Include/PhytiumPlatform.h = | 93 +++++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatform.c = | 254 ++++++++++++++++++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiSsdtRootPci.asl = | 234 ++++++++++++++++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dbg2.aslc = | 85 +++++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Cpu.asl = | 85 +++++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Dsdt.asl = | 15 ++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Uart.asl = | 65 +++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Fadt.aslc = | 81 +++++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Gtdt.aslc = | 87 +++++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Iort.aslc = | 89 +++++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Madt.aslc = | 66 +++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Mcfg.aslc = | 69 ++++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Pptt.aslc = | 219 +++++++++++++++++ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Spcr.aslc = | 83 +++++++ 18 files changed, 1658 insertions(+) diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Duria= n/DurianPkg.dsc index ef01cc217ace..45375383b22c 100644 --- a/Platform/Phytium/Durian/DurianPkg.dsc +++ b/Platform/Phytium/Durian/DurianPkg.dsc @@ -284,6 +284,13 @@ [Components.common] #=0D MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf=0D =0D + #=0D + # ACPI Support=0D + #=0D + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf=0D + Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf=0D + Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.in= f=0D +=0D #=0D # Bds=0D #=0D diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Duria= n/DurianPkg.fdf index f2f4cbc9ac7f..b4804c27aec4 100644 --- a/Platform/Phytium/Durian/DurianPkg.fdf +++ b/Platform/Phytium/Durian/DurianPkg.fdf @@ -109,6 +109,13 @@ [FV.FvMain] INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf=0D INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.i= nf=0D =0D + #=0D + # ACPI Support=0D + #=0D + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf=0D + INF RuleOverride=3DACPITABLE Silicon/Phytium/Phytium2000-4/Drivers/AcpiT= ables/AcpiTables.inf=0D + INF Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDx= e.inf=0D +=0D INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf=0D =0D #=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlat= formDxe.inf b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPla= tformDxe.inf new file mode 100644 index 000000000000..c1b1756f269f --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDxe= .inf @@ -0,0 +1,58 @@ +#/** @file=0D +# Sample ACPI Platform Driver.=0D +#=0D +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#**/=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010019=0D + BASE_NAME =3D AcpiPlatform=0D + FILE_GUID =3D d51068e8-40dc-11eb-9322-1f6d234e9e6e= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D AcpiPlatformEntryPoint=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[Sources]=0D + AcpiPlatform.c=0D +=0D +[Packages]=0D + ArmPkg/ArmPkg.dec=0D + ArmPlatformPkg/ArmPlatformPkg.dec=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Silicon/Phytium/Phytium.dec=0D +=0D +[LibraryClasses]=0D + UefiLib=0D + DxeServicesLib=0D + PcdLib=0D + BaseMemoryLib=0D + DebugLib=0D + UefiBootServicesTableLib=0D + UefiDriverEntryPoint=0D + HobLib=0D +=0D +[Guids]=0D + gPhytiumPlatformPciHostInforGuid=0D + gPhytiumPlatformCpuInforGuid=0D +=0D +[Protocols]=0D + gEfiAcpiTableProtocolGuid ## CONSUMES=0D +=0D +[Pcd]=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile ## CONSUMES=0D +=0D +[FixedPcd]=0D + gArmTokenSpaceGuid.PcdGicRedistributorsBase=0D +=0D +[Depex]=0D + gEfiAcpiTableProtocolGuid=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.in= f b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf new file mode 100644 index 000000000000..677ac31d3acc --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf @@ -0,0 +1,61 @@ +#/** @file=0D +#=0D +# ACPI table data and ASL sources required to boot the platform.=0D +#=0D +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#**/=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010019=0D + BASE_NAME =3D AcpiTables=0D + FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD= =0D + MODULE_TYPE =3D USER_DEFINED=0D + VERSION_STRING =3D 1.0=0D +=0D +[Sources]=0D + Dsdt/Dsdt.asl=0D + Spcr.aslc=0D + Fadt.aslc=0D + Gtdt.aslc=0D + Madt.aslc=0D + Mcfg.aslc=0D + Iort.aslc=0D + Pptt.aslc=0D + AcpiSsdtRootPci.asl=0D +=0D +[Packages]=0D + ArmPkg/ArmPkg.dec=0D + ArmPlatformPkg/ArmPlatformPkg.dec=0D + EmbeddedPkg/EmbeddedPkg.dec=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Silicon/Phytium/Phytium.dec=0D +=0D +[FixedPcd]=0D + gArmPlatformTokenSpaceGuid.PcdCoreCount=0D + gArmTokenSpaceGuid.PcdGicDistributorBase=0D + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase=0D + gArmTokenSpaceGuid.PcdGicRedistributorsBase=0D +=0D + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum=0D + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum=0D + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum=0D + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum=0D +=0D + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase=0D + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase=0D +=0D + #=0D + # PL011 UART Settings for Serial Port Console Redirection=0D + #=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase=0D + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate=0D + gArmPlatformTokenSpaceGuid.PL011UartClkInHz=0D + gArmPlatformTokenSpaceGuid.PL011UartInterrupt=0D +=0D + gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase=0D +=0D + gArmPlatformTokenSpaceGuid.PcdWatchdogCount=0D diff --git a/Silicon/Phytium/Include/PhytiumPlatform.h b/Silicon/Phytium/In= clude/PhytiumPlatform.h new file mode 100644 index 000000000000..495c5611eb15 --- /dev/null +++ b/Silicon/Phytium/Include/PhytiumPlatform.h @@ -0,0 +1,93 @@ +/** @file=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef __PHYTIUM_H__=0D +#define __PHYTIUM_H__=0D +#include =0D +=0D +#define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) = \=0D + { = \=0D + EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACP= I_RESERVED_WORD, \=0D + GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD = \=0D + }=0D +=0D +#define EFI_ACPI_5_1_GICR_STRUCTURE_INIT( = \=0D + GicRBase, GicRlength) = \=0D + { = \=0D + EFI_ACPI_5_1_GICR, sizeof (EFI_ACPI_5_1_GICR_STRUCTURE), EFI_ACPI_RESE= RVED_WORD, \=0D + GicRBase, GicRlength = \=0D + }=0D +=0D +#define EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT( = \=0D + ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) = \=0D + { = \=0D + 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , = \=0D + ACPIProcessorUID, Flags, ClockDomain = \=0D + }=0D +=0D +#define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( = \=0D + ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHig= h, Flags) \=0D + { = \=0D + 1, sizeof (EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , E= FI_ACPI_RESERVED_WORD, \=0D + AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESER= VED_DWORD, Flags, \=0D + EFI_ACPI_RESERVED_QWORD = \=0D + }=0D +=0D +#define EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, = PmuIrq, \=0D + GicBase, GicVBase, GicHBase, GsivId, GicRBase, ProcessorPowerEfficienc= yClass) \=0D + { = \=0D + EFI_ACPI_6_1_GIC, sizeof (EFI_ACPI_6_1_GIC_STRUCTURE), EFI_ACPI_RESERV= ED_WORD, \=0D + GicId, AcpiCpuUid, Flags, 0, PmuIrq, 0, GicBase, GicVBase, GicHBase, = \=0D + GsivId, GicRBase, Mpidr, ProcessorPowerEfficiencyClass, {0, 0, 0} = \=0D + }=0D +=0D +#define EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDis= tVector, GicVersion) \=0D + { = \=0D + EFI_ACPI_6_1_GICD, sizeof (EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE), EF= I_ACPI_RESERVED_WORD, \=0D + GicDistHwId, GicDistBase, GicDistVector, GicVersion, = \=0D + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYT= E} \=0D + }=0D +=0D +//=0D +// ACPI table information used to initialize tables.=0D +//=0D +#define EFI_ACPI_PHYTIUM_OEM_ID 'F','T','-','L','T','D' = // OEMID 6 bytes long=0D +#define EFI_ACPI_PHYTIUM_OEM_TABLE_ID SIGNATURE_64('P','H','Y','T','I'= ,'U','M',' ') // OEM table id 8 bytes long=0D +#define EFI_ACPI_PHYTIUM_OEM_REVISION 0x20201111=0D +#define EFI_ACPI_PHYTIUM_CREATOR_ID SIGNATURE_32('P','H','Y','T')=0D +#define EFI_ACPI_PHYTIUM_CREATOR_REVISION 0x20201111=0D +=0D +// A macro to initialise the common header part of EFI ACPI tables as defi= ned by=0D +// EFI_ACPI_DESCRIPTION_HEADER structure.=0D +#define PHYTIUM_ACPI_HEADER(Signature, Type, Revision) { \=0D + Signature, /* UINT32 Signature */ \=0D + sizeof (Type), /* UINT32 Length */ \=0D + Revision, /* UINT8 Revision */ \=0D + 0, /* UINT8 Checksum */ \=0D + { EFI_ACPI_PHYTIUM_OEM_ID }, /* UINT8 OemId[6] */ = \=0D + EFI_ACPI_PHYTIUM_OEM_TABLE_ID, /* UINT64 OemTableId */ \=0D + EFI_ACPI_PHYTIUM_OEM_REVISION, /* UINT32 OemRevision */ \=0D + EFI_ACPI_PHYTIUM_CREATOR_ID, /* UINT32 CreatorId */ \=0D + EFI_ACPI_PHYTIUM_CREATOR_REVISION /* UINT32 CreatorRevision */ \=0D + }=0D +=0D +//=0D +// Multiple APIC Description Table=0D +//=0D +#pragma pack (1)=0D +=0D +typedef struct {=0D + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;=0D + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[4];= =0D + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;=0D + EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[1];=0D +} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;=0D +=0D +#pragma pack ()=0D +=0D +#endif=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlat= form.c b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatform= .c new file mode 100644 index 000000000000..b212585d694e --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatform.c @@ -0,0 +1,254 @@ +/** @file=0D + Sample ACPI Platform Driver.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Locate the first instance of a protocol. If the protocol requested is a= n=0D + FV protocol, then it will return the first FV that contains the ACPI tab= le=0D + storage file.=0D +=0D + @param[out] Instance Return pointer to the first instance of th= e protocol.=0D +=0D + @return EFI_SUCCESS The function completed successfully.=0D +=0D + @return EFI_NOT_FOUND The protocol could not be located.=0D +=0D + @return EFI_OUT_OF_RESOURCES There are not enough resources to find the= protocol.=0D +=0D +**/=0D +EFI_STATUS=0D +LocateFvInstanceWithTables (=0D + OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_HANDLE *HandleBuffer;=0D + UINTN NumberOfHandles;=0D + EFI_FV_FILETYPE FileType;=0D + UINT32 FvStatus;=0D + EFI_FV_FILE_ATTRIBUTES Attributes;=0D + UINTN Size;=0D + UINTN Index;=0D + EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance;=0D +=0D + FvStatus =3D 0;=0D +=0D + //=0D + // Locate protocol.=0D + //=0D + Status =3D gBS->LocateHandleBuffer (=0D + ByProtocol,=0D + &gEfiFirmwareVolume2ProtocolGuid,=0D + NULL,=0D + &NumberOfHandles,=0D + &HandleBuffer=0D + );=0D + if (EFI_ERROR (Status)) {=0D + //=0D + // Defined errors at this time are not found and out of resources.=0D + //=0D + return Status;=0D + }=0D +=0D + //=0D + // Looking for FV with ACPI storage file=0D + //=0D +=0D + for (Index =3D 0; Index < NumberOfHandles; Index++) {=0D + //=0D + // Get the protocol on this handle=0D + // This should not fail because of LocateHandleBuffer=0D + //=0D + Status =3D gBS->HandleProtocol (=0D + HandleBuffer[Index],=0D + &gEfiFirmwareVolume2ProtocolGuid,=0D + (VOID**) &FvInstance=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // See if it has the ACPI storage file=0D + //=0D + Status =3D FvInstance->ReadFile (=0D + FvInstance,=0D + (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),= =0D + NULL,=0D + &Size,=0D + &FileType,=0D + &Attributes,=0D + &FvStatus=0D + );=0D +=0D + //=0D + // If we found it, then we are done=0D + //=0D + if (Status =3D=3D EFI_SUCCESS) {=0D + *Instance =3D FvInstance;=0D + break;=0D + }=0D + }=0D +=0D + //=0D + // Free any allocated buffers=0D + //=0D + gBS->FreePool (HandleBuffer);=0D +=0D + return Status;=0D +}=0D +=0D +=0D +/**=0D + This function calculates and updates an UINT8 checksum.=0D +=0D + @param[in] Buffer Pointer to buffer to checksum.=0D +=0D + @param[in] Size Number of bytes to checksum.=0D +=0D +**/=0D +VOID=0D +AcpiPlatformChecksum (=0D + IN UINT8 *Buffer,=0D + IN UINTN Size=0D + )=0D +{=0D + UINTN ChecksumOffset;=0D +=0D + ChecksumOffset =3D OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);=0D +=0D + //=0D + // Set checksum to 0 first=0D + //=0D + Buffer[ChecksumOffset] =3D 0;=0D +=0D + //=0D + // Update checksum value=0D + //=0D + Buffer[ChecksumOffset] =3D CalculateCheckSum8(Buffer, Size);=0D +}=0D +=0D +=0D +/**=0D + This function is the entrypoint of the acpi platform.=0D +=0D + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e.=0D +=0D + @param[in] SystemTable A pointer to the EFI System Table.=0D +=0D + @retval EFI_SUCCESS The entry point is executed successfully.=0D +=0D + @retval other Some error occurs when executing this entry po= int.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +AcpiPlatformEntryPoint (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_ACPI_TABLE_PROTOCOL *AcpiTable;=0D + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;=0D + INTN Instance;=0D + EFI_ACPI_COMMON_HEADER *CurrentTable;=0D + UINTN TableHandle;=0D + UINT32 FvStatus;=0D + UINTN TableSize;=0D + UINTN Size;=0D +=0D + Instance =3D 0;=0D + CurrentTable =3D NULL;=0D + TableHandle =3D 0;=0D +=0D + //=0D + // Find the AcpiTable protocol=0D + //=0D + Status =3D gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID*= *)&AcpiTable);=0D + if (EFI_ERROR (Status)) {=0D + return EFI_ABORTED;=0D + }=0D +=0D + //=0D + // Locate the firmware volume protocol=0D + //=0D + Status =3D LocateFvInstanceWithTables (&FwVol);=0D + if (EFI_ERROR (Status)) {=0D + return EFI_ABORTED;=0D + }=0D + //=0D + // Read tables from the storage file.=0D + //=0D + while (Status =3D=3D EFI_SUCCESS) {=0D +=0D + Status =3D FwVol->ReadSection (=0D + FwVol,=0D + (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),=0D + EFI_SECTION_RAW,=0D + Instance,=0D + (VOID**) &CurrentTable,=0D + &Size,=0D + &FvStatus=0D + );=0D + if (!EFI_ERROR(Status)) {=0D + //=0D + // Add the table=0D + //=0D + TableHandle =3D 0;=0D +=0D + TableSize =3D ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length= ;=0D + ASSERT (Size >=3D TableSize);=0D +=0D + //=0D + // Checksum ACPI table=0D + //=0D + AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize);=0D +=0D + //=0D + // Install ACPI table=0D + //=0D + Status =3D AcpiTable->InstallAcpiTable (=0D + AcpiTable,=0D + CurrentTable,=0D + TableSize,=0D + &TableHandle=0D + );=0D +=0D + //=0D + // Free memory allocated by ReadSection=0D + //=0D + gBS->FreePool (CurrentTable);=0D +=0D + if (EFI_ERROR(Status)) {=0D + return EFI_ABORTED;=0D + }=0D +=0D + //=0D + // Increment the instance=0D + //=0D + Instance++;=0D + CurrentTable =3D NULL;=0D + }=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiSsdtRootP= ci.asl b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiSsdtRootPci.a= sl new file mode 100644 index 000000000000..0661f2c4f779 --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiSsdtRootPci.asl @@ -0,0 +1,234 @@ +/** @file=0D + Phytium ACPI ASL Sources.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +/*=0D + See ACPI 6.1 Section 6.2.13=0D +=0D + There are two ways that _PRT can be used. ...=0D +=0D + In the first model, a PCI Link device is used to provide additional=0D + configuration information such as whether the interrupt is Level or=0D + Edge triggered, it is active High or Low, Shared or Exclusive, etc.=0D +=0D + In the second model, the PCI interrupts are hardwired to specific=0D + interrupt inputs on the interrupt controller and are not=0D + configurable. In this case, the Source field in _PRT does not=0D + reference a device, but instead contains the value zero, and the=0D + Source Index field contains the global system interrupt to which the=0D + PCI interrupt is hardwired.=0D +=0D + We use the first model with link indirection to set the correct=0D + interrupt type as PCI defaults (Level Triggered, Active Low) are not=0D + compatible with GICv2.=0D +*/=0D +=0D +#define LNK_DEVICE(Unique_Id, Link_Name, irq) = \=0D + Device(Link_Name) { = \=0D + Name(_HID, EISAID("PNP0C0F")) = \=0D + Name(_UID, Unique_Id) = \=0D + Name(_PRS, ResourceTemplate() { = \=0D + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } = \=0D + }) = \=0D + Method (_CRS, 0) { Return (_PRS) } = \=0D + Method (_SRS, 1) { } = \=0D + Method (_DIS) { } = \=0D + }=0D +=0D +#define PRT_ENTRY(Address, Pin, Link) = \=0D + Package (4) { = \=0D + Address, /* uses the same format as _ADR */ = \=0D + Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INT= C, 3-INTD). */ \=0D + Link, /* Interrupt allocated via Link device. */ = \=0D + Zero /* global system interrupt number (no used) */ = \=0D + }=0D +=0D +/*=0D + See Reference [1] 6.1.1=0D + "High word=E2=80=93Device #, Low word=E2=80=93Function #. (for example, = device 3, function 2 is=0D + 0x00030002). To refer to all the functions on a device #, use a functio= n number of FFFF)."=0D +*/=0D +#define ROOT_PRT_ENTRY(Dev, Pin, Link) PRT_ENTRY(Dev * 0x10000 + 0xFFFF,= Pin, Link)=0D +=0D +=0D +DefinitionBlock("SsdtPci.aml", "SSDT", 2, "FT-LTD", "PHYTIUM ", EFI_ACPI_P= HYTIUM_OEM_REVISION) {=0D + Scope(_SB) {=0D + //=0D + // PCI Root Complex=0D + //=0D + LNK_DEVICE(1, LNKA, 60)=0D + LNK_DEVICE(2, LNKB, 61)=0D + LNK_DEVICE(3, LNKC, 62)=0D + LNK_DEVICE(4, LNKD, 63)=0D +=0D + // reserve ECAM memory range=0D + Device(RES0)=0D + {=0D + Name(_HID, EISAID("PNP0C02"))=0D + Name(_UID, 0)=0D + Name(_CRS, ResourceTemplate() {=0D + QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, Cach= eable, ReadWrite,=0D + 0x0, // Granularity=0D + 0x40000000, // Range Minimum=0D + 0x4FFFFFFF, // Range Maximum=0D + 0, // Translation Offset=0D + 0x10000000, // Length=0D + ,,)=0D + })=0D + }=0D +=0D + Device(PCI0)=0D + {=0D + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge=0D + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge=0D + Name(_SEG, Zero) // PCI Segment Group number=0D + Name(_BBN, 0) // PCI Base Bus Number=0D + Name(_CCA, 1) // Initially mark the PCI coherent (fo= r JunoR1)=0D +=0D + // Root Complex=0D + Device (RP0) {=0D + Name(_ADR, 0x00000000) // Dev 0, Func 0=0D + }=0D + // PCI Routing Table=0D + Name(_PRT, Package() {=0D + ROOT_PRT_ENTRY(0, 0, LNKA), // INTA=0D + ROOT_PRT_ENTRY(0, 1, LNKB), // INTB=0D + ROOT_PRT_ENTRY(0, 2, LNKC), // INTC=0D + ROOT_PRT_ENTRY(0, 3, LNKD), // INTD=0D +=0D + ROOT_PRT_ENTRY(1, 0, LNKA), // INTA=0D + ROOT_PRT_ENTRY(1, 1, LNKB), // INTB=0D + ROOT_PRT_ENTRY(1, 2, LNKC), // INTC=0D + ROOT_PRT_ENTRY(1, 3, LNKD), // INTD=0D +=0D + ROOT_PRT_ENTRY(2, 0, LNKA), // INTA=0D + ROOT_PRT_ENTRY(2, 1, LNKB), // INTB=0D + ROOT_PRT_ENTRY(2, 2, LNKC), // INTC=0D + ROOT_PRT_ENTRY(2, 3, LNKD), // INTD=0D +=0D + ROOT_PRT_ENTRY(3, 0, LNKA), // INTA=0D + ROOT_PRT_ENTRY(3, 1, LNKB), // INTB=0D + ROOT_PRT_ENTRY(3, 2, LNKC), // INTC=0D + ROOT_PRT_ENTRY(3, 3, LNKD), // INTD=0D +=0D + ROOT_PRT_ENTRY(4, 0, LNKA), // INTA=0D + ROOT_PRT_ENTRY(4, 1, LNKB), // INTB=0D + ROOT_PRT_ENTRY(4, 2, LNKC), // INTC=0D + ROOT_PRT_ENTRY(4, 3, LNKD), // INTD=0D +=0D + ROOT_PRT_ENTRY(5, 0, LNKA), // INTA=0D + ROOT_PRT_ENTRY(5, 1, LNKB), // INTB=0D + ROOT_PRT_ENTRY(5, 2, LNKC), // INTC=0D + ROOT_PRT_ENTRY(5, 3, LNKD), // INTD=0D + })=0D +=0D + // Root complex resources=0D + Method (_CRS, 0, Serialized) {=0D + Name (RBUF, ResourceTemplate () {=0D + WordBusNumber (=0D + ResourceProducer,=0D + MinFixed, MaxFixed, PosDecode,=0D + 0, // AddressGranularity=0D + 0, // AddressMinimum - Minimum Bus Numbe= r=0D + 255, // AddressMaximum - Maximum Bus Numbe= r=0D + 0, // AddressTranslation - Set to 0=0D + 256 // RangeLength - Number of Busses=0D + )=0D +=0D + DWordMemory ( // 32-bit BAR Windows=0D + ResourceProducer, PosDecode,=0D + MinFixed, MaxFixed,=0D + Cacheable, ReadWrite,=0D + 0x00000000, // Granularity=0D + 0x58000000, // Min Base Address=0D + 0x7FFFFFFF, // Max Base Address=0D + 0x00000000, // Translate=0D + 0x28000000 // Length=0D + )=0D +=0D + QWordMemory ( // 64-bit BAR Windows=0D + ResourceProducer, PosDecode,=0D + MinFixed, MaxFixed,=0D + Cacheable, ReadWrite,=0D + 0x00000000, // Granularity=0D + 0x1000000000, // Min Base Address=0D + 0x1FFFFFFFFF, // Max Base Address=0D + 0x0000000000, // Translate=0D + 0x1000000000 // Length=0D + )=0D +=0D + DWordIo ( // IO window=0D + ResourceProducer,=0D + MinFixed,=0D + MaxFixed,=0D + PosDecode,=0D + EntireRange,=0D + 0x00000000, // Granularity=0D + 0x00000000, // Min Base Address=0D + 0x00efffff, // Max Base Address=0D + 0x50000000, // Translate=0D + 0x00f00000, // Length=0D + ,,,TypeTranslation=0D + )=0D + }) // Name(RBUF)=0D +=0D + Return (RBUF)=0D + } // Method(_CRS)=0D +=0D + //=0D + // OS Control Handoff=0D + //=0D + Name(SUPP, Zero) // PCI _OSC Support Field value=0D + Name(CTRL, Zero) // PCI _OSC Control Field value=0D +=0D + /*=0D + See [1] 6.2.10, [2] 4.5=0D + */=0D + Method(_OSC,4) {=0D + // Check for proper UUID=0D + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {= =0D + // Create DWord-adressable fields from the Capabilities Buffer=0D + CreateDWordField(Arg3,0,CDW1)=0D + CreateDWordField(Arg3,4,CDW2)=0D + CreateDWordField(Arg3,8,CDW3)=0D +=0D + // Save Capabilities DWord2 & 3=0D + Store(CDW2,SUPP)=0D + Store(CDW3,CTRL)=0D +=0D + // Only allow native hot plug control if OS supports:=0D + // * ASPM=0D + // * Clock PM=0D + // * MSI/MSI-X=0D + If(LNotEqual(And(SUPP, 0x16), 0x16)) {=0D + And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)=0D + }=0D +=0D + // Do not allow native PME, AER (no dependencies)=0D + // Never allow SHPC (no SHPC controller in this system)=0D + And(CTRL,0x10,CTRL)=0D +=0D + If(LNotEqual(Arg1,One)) { // Unknown revision=0D + Or(CDW1,0x08,CDW1)=0D + }=0D +=0D + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked=0D + Or(CDW1,0x10,CDW1)=0D + }=0D + // Update DWORD3 in the buffer=0D + Store(CTRL,CDW3)=0D + Return(Arg3)=0D + } Else {=0D + Or(CDW1,4,CDW1) // Unrecognized UUID=0D + Return(Arg3)=0D + }=0D + }=0D + }=0D + }=0D +}=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dbg2.aslc b/S= ilicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dbg2.aslc new file mode 100644 index 000000000000..ede0fe3c62c6 --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dbg2.aslc @@ -0,0 +1,85 @@ +/** @file=0D + Phytium ACPI ASL Sources.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#define NUMBER_DEBUG_DEVICE_INFO 1=0D +#define NUMBER_OF_GENERIC_ADDRESS 1=0D +#define NAMESPACE_STRING_SIZE 8=0D +=0D +#pragma pack(1)=0D +=0D +typedef struct {=0D + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader;=0D + EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS= ];=0D + UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS];=0D + CHAR8 NamespaceString[NAMESPACE_STRING_SIZE];=0D +} EFI_ACPI_DBG2_DDI_STRUCT;=0D +=0D +typedef struct {=0D + EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc;=0D + EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO];=0D +} EFI_ACPI_DEBUG_PORT_2_TABLE;=0D +=0D +#pragma pack()=0D +=0D +EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 =3D {=0D + {=0D + PHYTIUM_ACPI_HEADER(=0D + EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE,=0D + EFI_ACPI_DEBUG_PORT_2_TABLE,=0D + EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION=0D + ),=0D + OFFSET_OF(EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi),=0D + NUMBER_DEBUG_DEVICE_INFO=0D + },=0D + {=0D + {=0D + {=0D + EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,=0D + sizeof(EFI_ACPI_DBG2_DDI_STRUCT),=0D + NUMBER_OF_GENERIC_ADDRESS,=0D + NAMESPACE_STRING_SIZE,=0D + OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString),=0D + 0,=0D + 0,=0D + EFI_ACPI_DBG2_PORT_TYPE_SERIAL,=0D + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART,=0D + {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},=0D + OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, Address),=0D + OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, AddressSize),=0D + },=0D + {=0D + {=0D + EFI_ACPI_6_1_SYSTEM_MEMORY,=0D + 32,=0D + 0,=0D + EFI_ACPI_6_1_DWORD,=0D + FixedPcdGet64(PcdSerialRegisterBase)=0D + }=0D + },=0D + {=0D + 0x1000=0D + },=0D + "COM0"=0D + }=0D + }=0D +};=0D +=0D +//=0D +// Reference the table being generated to prevent the optimizer from remov= ing the=0D +// data structure from the executable=0D +//=0D +VOID* CONST ReferenceAcpiTable =3D &Dbg2;=0D +=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Cpu.asl = b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Cpu.asl new file mode 100644 index 000000000000..4a761149c508 --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Cpu.asl @@ -0,0 +1,85 @@ +/** @file=0D + Phytium ACPI ASL Sources.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +Scope(_SB)=0D +{=0D + Device (CLU0) {=0D + Name(_HID, "ACPI0010")=0D + Name(_UID, 1)=0D + Method (_STA, 0, NotSerialized) {=0D + Return(0x0F)=0D + }=0D + Device(CPU0) {=0D + Name(_HID, "ACPI0007")=0D + Name(_UID, 0)=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () {"clock-name","c0"},=0D + Package () {"clock-domain",0},=0D + }=0D + })=0D + Method (_STA, 0, NotSerialized) {=0D + Return(0x0F)=0D + }=0D + }=0D +=0D + Device(CPU1) {=0D + Name(_HID, "ACPI0007")=0D + Name(_UID, 1)=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () {"clock-name","c0"},=0D + Package () {"clock-domain",0},=0D + }=0D + })=0D + Method (_STA, 0, NotSerialized) {=0D + Return(0x0F)=0D + }=0D + }=0D + }=0D +=0D + Device (CLU1) {=0D + Name(_HID, "ACPI0010")=0D + Name(_UID, 2)=0D + Method (_STA, 0, NotSerialized) {=0D + Return(0x0F)=0D + }=0D + Device(CPU2) {=0D + Name(_HID, "ACPI0007")=0D + Name(_UID, 2)=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () {"clock-name","c1"},=0D + Package () {"clock-domain",1},=0D + }=0D + })=0D + Method (_STA, 0, NotSerialized) {=0D + Return(0x0F)=0D + }=0D + }=0D +=0D + Device(CPU3) {=0D + Name(_HID, "ACPI0007")=0D + Name(_UID, 3)=0D + Name (_DSD, Package () {=0D + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D + Package () {=0D + Package () {"clock-name","c1"},=0D + Package () {"clock-domain",1},=0D + }=0D + })=0D + Method (_STA, 0, NotSerialized) {=0D + Return(0x0F)=0D + }=0D + }=0D + }=0D +}=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Dsdt.asl= b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Dsdt.asl new file mode 100644 index 000000000000..01c48defa00f --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Dsdt.asl @@ -0,0 +1,15 @@ +/** @file=0D + Phytium ACPI ASL Sources.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +=0D +DefinitionBlock("DsdtTable.aml", "DSDT", 2, "FT-LTD", "PHYTIUM ", EFI_ACPI= _PHYTIUM_OEM_REVISION) {=0D + include ("Cpu.asl")=0D + include ("Uart.asl")=0D +}=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Uart.asl= b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Uart.asl new file mode 100644 index 000000000000..3e99c3c39f42 --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Uart.asl @@ -0,0 +1,65 @@ +/** @file=0D + Phytium ACPI ASL Sources.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +Scope(_SB)=0D +{=0D + //UART 1=0D + Device(UAR1) {=0D + Name(_HID, "ARMH0011")=0D + Name(_UID, 1)=0D + Name(_CRS, ResourceTemplate() {=0D + Memory32Fixed(ReadWrite, 0x28001000, 0x1000)=0D + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {39}=0D + })=0D +=0D + Method (_STA, 0, NotSerialized) { Return(0x0F) }=0D + }=0D +=0D + //UART 0=0D + Device(UAR0) {=0D + Name(_HID, "ARMH0011")=0D + Name(_UID, 0)=0D + Name(_CRS, ResourceTemplate() {=0D + Memory32Fixed(ReadWrite, 0x28000000, 0x1000)=0D + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 38 }=0D + })=0D +=0D + Method (_STA, 0, NotSerialized) {=0D + Return(0x0F)=0D + }=0D + }=0D +=0D + //UART 2=0D + Device(UAR2) {=0D + Name(_HID, "ARMH0011")=0D + Name(_UID, 2)=0D + Name(_CRS, ResourceTemplate() {=0D + Memory32Fixed(ReadWrite, 0x28002000, 0x1000)=0D + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {40}=0D + })=0D +=0D + Method (_STA, 0, NotSerialized) {=0D + Return(0x0F)=0D + }=0D + }=0D +=0D + //UART 3=0D + Device(UAR3) {=0D + Name(_HID, "ARMH0011")=0D + Name(_UID, 3)=0D + Name(_CRS, ResourceTemplate() {=0D + Memory32Fixed(ReadWrite, 0x28003000, 0x1000)=0D + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {41}=0D + })=0D +=0D + Method (_STA, 0, NotSerialized) {=0D + Return(0x0F)=0D + }=0D + }=0D +}=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Fadt.aslc b/S= ilicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Fadt.aslc new file mode 100644 index 000000000000..275f057ebfba --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Fadt.aslc @@ -0,0 +1,81 @@ +/** @file=0D + Phytium ACPI ASL Sources.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {=0D + PHYTIUM_ACPI_HEADER (=0D + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,=0D + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE,=0D + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION=0D + ),=0D + 0, = // UINT32 FirmwareCtrl=0D + 0, = // UINT32 Dsdt=0D + EFI_ACPI_RESERVED_BYTE, = // UINT8 Reserved0=0D + EFI_ACPI_6_1_PM_PROFILE_ENTERPRISE_SERVER, = // UINT8 PreferredPmProfile=0D + 0, = // UINT16 SciInt=0D + 0, = // UINT32 SmiCmd=0D + 0, = // UINT8 AcpiEnable=0D + 0, = // UINT8 AcpiDisable=0D + 0, = // UINT8 S4BiosReq=0D + 0, = // UINT8 PstateCnt=0D + 0, = // UINT32 Pm1aEvtBlk=0D + 0, = // UINT32 Pm1bEvtBlk=0D + 0, = // UINT32 Pm1aCntBlk=0D + 0, = // UINT32 Pm1bCntBlk=0D + 0, = // UINT32 Pm2CntBlk=0D + 0, = // UINT32 PmTmrBlk=0D + 0, = // UINT32 Gpe0Blk=0D + 0, = // UINT32 Gpe1Blk=0D + 0, = // UINT8 Pm1EvtLen=0D + 0, = // UINT8 Pm1CntLen=0D + 0, = // UINT8 Pm2CntLen=0D + 0, = // UINT8 PmTmrLen=0D + 0, = // UINT8 Gpe0BlkLen=0D + 0, = // UINT8 Gpe1BlkLen=0D + 0, = // UINT8 Gpe1Base=0D + 0, = // UINT8 CstCnt=0D + 0, = // UINT16 PLvl2Lat=0D + 0, = // UINT16 PLvl3Lat=0D + 0, = // UINT16 FlushSize=0D + 0, = // UINT16 FlushStride=0D + 0, = // UINT8 DutyOffset=0D + 0, = // UINT8 DutyWidth=0D + 0, = // UINT8 DayAlrm=0D + 0, = // UINT8 MonAlrm=0D + 0, = // UINT8 Century=0D + 0, = // UINT16 IaPcBootArch=0D + 0, = // UINT8 Reserved1=0D + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, = // UINT32 Flags=0D + NULL_GAS, = // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE ResetReg=0D + 0, = // UINT8 ResetValue=0D + EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, = // UINT16 ArmBootArchFlags=0D + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, = // UINT8 MinorRevision=0D + 0, = // UINT64 XFirmwareCtrl=0D + 0, = // UINT64 XDsdt=0D + NULL_GAS, = // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk=0D + NULL_GAS, = // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk=0D + NULL_GAS, = // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk=0D + NULL_GAS, = // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk=0D + NULL_GAS, = // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm2CntBlk=0D + NULL_GAS, = // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPmTmrBlk=0D + NULL_GAS, = // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe0Blk=0D + NULL_GAS, = // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe1Blk=0D + NULL_GAS, = // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepControlReg=0D + NULL_GAS, = // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepStatusReg=0D + 0 = // UINT64 Hypervisor Vendor Identify=0D +};=0D +=0D +//=0D +// Reference the table being generated to prevent the optimizer from remov= ing the=0D +// data structure from the executable=0D +//=0D +VOID* CONST ReferenceAcpiTable =3D &Fadt;=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Gtdt.aslc b/S= ilicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Gtdt.aslc new file mode 100644 index 000000000000..534a93e120ba --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Gtdt.aslc @@ -0,0 +1,87 @@ +/** @file=0D + Phytium ACPI ASL Sources.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY= _MAPPED_BLOCK_PRESENT=0D +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0=0D +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERR= UPT_MODE=0D +#define GTDT_GLOBAL_FLAGS_LEVEL 0=0D +=0D +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INT= ERRUPT_MODE=0D +#define GTDT_TIMER_LEVEL_TRIGGERED 0=0D +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INT= ERRUPT_POLARITY=0D +#define GTDT_TIMER_ACTIVE_HIGH 0=0D +#define GTDT_TIMER_ALWAYS_ON_CAPABILITY EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAY= S_ON_CAPABILITY=0D +=0D +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LE= VEL_TRIGGERED | EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY)=0D +=0D +#pragma pack (1)=0D +=0D +typedef struct {=0D + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;=0D + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[2];=0D +} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES;=0D +=0D +#pragma pack ()=0D +=0D +EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt =3D {=0D + {=0D + PHYTIUM_ACPI_HEADER(=0D + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,=0D + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES,=0D + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION=0D + ),=0D + 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddre= ss=0D + 0, // UINT32 Reserved=0D + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1Time= rGSIV=0D + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1Time= rFlags=0D + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1T= imerGSIV=0D + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1T= imerFlags=0D + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerG= SIV=0D + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerF= lags=0D + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2T= imerGSIV=0D + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2T= imerFlags=0D + 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePh= ysicalAddress=0D + 2,=0D + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE)=0D + },=0D +=0D + {=0D + {=0D + 1, //Type=0D + 28, //Size of this structure=0D + 0, //reserved=0D + 0x2800a000, //RefreshFrame Physical Address=0D + 0x2800b000, //WatchdogControlFrame Physical Address=0D + 48, //Watchdog Timer GSIV=0D + 0, //Watchdog Timer Flags high level=0D + },=0D +=0D + {=0D + 1,=0D + 28,=0D + 0,=0D + 0x28016000,=0D + 0x28017000,=0D + 49,=0D + 0,=0D + }=0D + }=0D +};=0D +=0D +//=0D +// Reference the table being generated to prevent the optimizer from remov= ing the=0D +// data structure from the executable=0D +//=0D +VOID* CONST ReferenceAcpiTable =3D &Gtdt;=0D +=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Iort.aslc b/S= ilicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Iort.aslc new file mode 100644 index 000000000000..a684806e69f0 --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Iort.aslc @@ -0,0 +1,89 @@ +/** @file=0D + Phytium ACPI ASL Sources.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +=0D +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)= =0D +=0D +#pragma pack(1)=0D +typedef struct {=0D + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node;=0D + UINT32 Identifiers[1];=0D +} PHYTIUM_ITS_NODE;=0D +=0D +typedef struct {=0D + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node;=0D + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping;=0D +} PHYTIUM_RC_NODE;=0D +=0D +typedef struct {=0D + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort;=0D + PHYTIUM_ITS_NODE ItsNode;=0D + PHYTIUM_RC_NODE RcNode[1];=0D +} PHYTIUM_IO_REMAPPING_STRUCTURE;=0D +=0D +#define __PHYTIUM_ID_MAPPING(In, Num, Out, Ref, Flags) \=0D + { \=0D + In, \=0D + Num, \=0D + Out, \=0D + FIELD_OFFSET(PHYTIUM_IO_REMAPPING_STRUCTURE, Ref), \=0D + Flags \=0D + }=0D +=0D +STATIC PHYTIUM_IO_REMAPPING_STRUCTURE Iort =3D {=0D + {=0D + PHYTIUM_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,=0D + PHYTIUM_IO_REMAPPING_STRUCTURE,=0D + EFI_ACPI_IO_REMAPPING_TABLE_REVISION),=0D + 2, // NumNodes=0D + sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset=0D + 0 // Reserved=0D + }, {=0D + // ItsNode=0D + {=0D + {=0D + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type=0D + sizeof(PHYTIUM_ITS_NODE), // Length=0D + 0x0, // Revision=0D + 0x0, // Reserved=0D + 0x0, // NumIdMappin= gs=0D + 0x0, // IdReference= =0D + },=0D + 1,=0D + }, {=0D + 0x0=0D + },=0D + }, {=0D + {=0D + // PciRcNode=0D + {=0D + {=0D + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type=0D + sizeof(PHYTIUM_RC_NODE), // Length=0D + 0x0, // Revision= =0D + 0x0, // Reserved= =0D + 0x1, // NumIdMapp= ings=0D + FIELD_OFFSET(PHYTIUM_RC_NODE, RcIdMapping), // IdReferen= ce=0D + },=0D + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCohe= rent=0D + 0x0, // Allocatio= nHints=0D + 0x0, // Reserved= =0D + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM, // MemoryAcc= essFlags=0D + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttrib= ute=0D + 0x0, // PciSegmen= tNumber=0D + },=0D + __PHYTIUM_ID_MAPPING(0x0, 0xffff, 0x0, ItsNode, 0),=0D + }=0D + }=0D +};=0D +#pragma pack()=0D +#=0D +VOID* CONST ReferenceAcpiTable =3D &Iort;=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Madt.aslc b/S= ilicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Madt.aslc new file mode 100644 index 000000000000..53ff85e7cd52 --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Madt.aslc @@ -0,0 +1,66 @@ +/** @file=0D + Phytium ACPI ASL Sources.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +=0D +// Differs from Juno, we have another affinity level beyond cluster and co= re=0D +// 0x20000 is only for socket 0=0D +#define PLATFORM_GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (Core= Id))=0D +=0D +// Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuI= rq, GicBase, GicVBase, GicHBase,=0D +// GsivId, GicRBase, Mpidr)=0D +// Note: The GIC Structure of the primary CPU must be the first entry (see= note in 5.2.12.14 GICC Structure of=0D +// ACPI v5.1).=0D +// The cores from a same cluster are kept together. It is not an ACP= I requirement but in case the OSPM uses=0D +// the ACPI ARM Parking protocol, it might want to wake up the cores= in the order of this table.=0D +=0D +#define EFI_GICC_STRUCTURE(AcpiCpuUid, Mpidr, GicRBaseOffset) = \=0D + EFI_ACPI_6_1_GICC_STRUCTURE_INIT(0, AcpiCpuUid, Mpidr, EFI_ACPI_6_1_GIC= _ENABLED, 23, \=0D + FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInt= erruptInterfaceBase) + 0x20000, \=0D + FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGe= t64 (PcdGicRedistributorsBase) + GicRBaseOffset, 0)=0D +//=0D +// Multiple APIC Description Table=0D +//=0D +EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D {=0D + {=0D + PHYTIUM_ACPI_HEADER (=0D + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,=0D + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE,=0D + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION=0D + ),=0D + //=0D + // MADT specific fields=0D + //=0D + 0, // LocalApicAddress=0D + 0, // Flags=0D + },=0D + {=0D + EFI_GICC_STRUCTURE(0x00, PLATFORM_GET_MPID(0x00, 0), 0x000000),=0D + EFI_GICC_STRUCTURE(0x01, PLATFORM_GET_MPID(0x00, 1), 0x020000),=0D + EFI_GICC_STRUCTURE(0x02, PLATFORM_GET_MPID(0x01, 0), 0x040000),=0D + EFI_GICC_STRUCTURE(0x03, PLATFORM_GET_MPID(0x01, 1), 0x060000),=0D + },=0D +=0D + EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBas= e), 0, 0x3),=0D + {=0D + EFI_ACPI_6_1_GIC_ITS_INIT(0, FixedPcdGet64(PcdGicDistributorBase) + 0x= 20000),=0D + }=0D +};=0D +=0D +=0D +//=0D +// Reference the table being generated to prevent the optimizer from remov= ing the=0D +// data structure from the executable=0D +//=0D +VOID* CONST ReferenceAcpiTable =3D &Madt;=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Mcfg.aslc b/S= ilicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Mcfg.aslc new file mode 100644 index 000000000000..9eb89062ffb1 --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Mcfg.aslc @@ -0,0 +1,69 @@ +/** @file=0D + Phytium ACPI ASL Sources.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +=0D +#define ACPI_6_1_MCFG_VERSION 0x1=0D +=0D +#pragma pack(1)=0D +typedef struct=0D +{=0D + UINT64 ullBaseAddress;=0D + UINT16 usSegGroupNum;=0D + UINT8 ucStartBusNum;=0D + UINT8 ucEndBusNum;=0D + UINT32 Reserved2;=0D +}EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE;=0D +=0D +typedef struct=0D +{=0D + EFI_ACPI_DESCRIPTION_HEADER Header;=0D + UINT64 Reserved1;=0D +}EFI_ACPI_6_1_MCFG_TABLE_CONFIG;=0D +=0D +typedef struct=0D +{=0D + EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;=0D + EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[1];=0D +}EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;=0D +#pragma pack()=0D +=0D +EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=3D=0D +{=0D + {=0D + {=0D + EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDR= ESS_DESCRIPTION_TABLE_SIGNATURE,=0D + sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_T= ABLE),=0D + ACPI_6_1_MCFG_VERSION,=0D + 0x00, // Checksum will b= e updated at runtime=0D + {EFI_ACPI_PHYTIUM_OEM_ID},=0D + EFI_ACPI_PHYTIUM_OEM_TABLE_ID,=0D + EFI_ACPI_PHYTIUM_OEM_REVISION,=0D + EFI_ACPI_PHYTIUM_CREATOR_ID,=0D + EFI_ACPI_PHYTIUM_CREATOR_REVISION=0D + },=0D + 0x0000000000000000, //Reserved=0D + },=0D + {=0D + {=0D + 0x40000000, //Base Address=0D + 0, //Segment Group Num= ber=0D + 0, //Start Bus Number= =0D + 0xff, //End Bus Number=0D + 0x00000000, //Reserved=0D + },=0D + }=0D +};=0D +=0D +//=0D +// Reference the table being generated to prevent the optimizer from remov= ing the=0D +// data structure from the executable=0D +//=0D +VOID* CONST ReferenceAcpiTable =3D &Mcfg;=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Pptt.aslc b/S= ilicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Pptt.aslc new file mode 100644 index 000000000000..cc5d82b5585b --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Pptt.aslc @@ -0,0 +1,219 @@ +/** @file=0D + Phytium ACPI ASL Sources.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +=0D +#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)= =0D +=0D +#pragma pack(1)=0D +typedef struct {=0D + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core;=0D + UINT32 Offset[2];=0D + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache;=0D + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache;=0D +} PHYTIUM_PPTT_CORE;=0D +=0D +typedef struct {=0D + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster;=0D + UINT32 Offset[1];=0D + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache;=0D + PHYTIUM_PPTT_CORE Cores[2];=0D +} PHYTIUM_PPTT_CLUSTER;=0D +=0D +typedef struct {=0D + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package;=0D + UINT32 Offset[1];=0D + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache;=0D + PHYTIUM_PPTT_CLUSTER Clusters[2];=0D + EFI_ACPI_6_2_PPTT_STRUCTURE_ID ID;=0D +} PHYTIUM_PPTT_PACKAGE;=0D +=0D +typedef struct {=0D + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt;=0D + PHYTIUM_PPTT_PACKAGE Packages[1];=0D +} PHYTIUM_PPTT_TABLE;=0D +#pragma pack()=0D +=0D +#define PPTT_CORE(pid, cid, id) { = \=0D + { = \=0D + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \=0D + FIELD_OFFSET (PHYTIUM_PPTT_CORE, DCache), = \=0D + {}, = \=0D + { = \=0D + 0, /* PhysicalPackage */ = \=0D + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */= \=0D + }, = \=0D + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, = \=0D + Packages[pid].Clusters[cid]), /* Parent */ = \=0D + 8 * (pid) + 4 * (cid) + (id), /* AcpiProcessorId */ = \=0D + 2, /* NumberOfPrivateResource= s */\=0D + }, { = \=0D + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, = \=0D + Packages[pid].Clusters[cid].Cores[id].DCache), = \=0D + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, = \=0D + Packages[pid].Clusters[cid].Cores[id].ICache), = \=0D + }, { = \=0D + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \=0D + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \=0D + {}, = \=0D + { = \=0D + 1, /* SizePropertyValid */ = \=0D + 1, /* NumberOfSetsValid */ = \=0D + 1, /* AssociativityValid */ = \=0D + 1, /* AllocationTypeValid */ = \=0D + 1, /* CacheTypeValid */ = \=0D + 1, /* WritePolicyValid */ = \=0D + 1, /* LineSizeValid */ = \=0D + }, = \=0D + 0, /* NextLevelOfCache */ = \=0D + SIZE_32KB, /* Size */ = \=0D + 256, /* NumberOfSets */ = \=0D + 2, /* Associativity */ = \=0D + { = \=0D + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \=0D + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, = \=0D + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \=0D + }, = \=0D + 64 /* LineSize */ = \=0D + }, { = \=0D + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \=0D + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \=0D + {}, = \=0D + { = \=0D + 1, /* SizePropertyValid */ = \=0D + 1, /* NumberOfSetsValid */ = \=0D + 1, /* AssociativityValid */ = \=0D + 1, /* AllocationTypeValid */ = \=0D + 1, /* CacheTypeValid */ = \=0D + 0, /* WritePolicyValid */ = \=0D + 1, /* LineSizeValid */ = \=0D + }, = \=0D + 0, /* NextLevelOfCache */ = \=0D + SIZE_32KB, /* Size */ = \=0D + 256, /* NumberOfSets */ = \=0D + 2, /* Associativity */ = \=0D + { = \=0D + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType = */ \=0D + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, = \=0D + 0, /* WritePolicy */ = \=0D + }, = \=0D + 64 /* LineSize */ = \=0D + } = \=0D +}=0D +=0D +#define PPTT_CLUSTER(pid, cid) { = \=0D + { = \=0D + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \=0D + FIELD_OFFSET (PHYTIUM_PPTT_CLUSTER, L2Cache), = \=0D + {}, = \=0D + { = \=0D + 0, /* PhysicalPackage */ = \=0D + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ = \=0D + }, = \=0D + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid]), /* Parent */ = \=0D + 0, /* AcpiProcessorId */ = \=0D + 1, /* NumberOfPrivateResources = */ \=0D + }, { = \=0D + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache)= , \=0D + }, { = \=0D + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \=0D + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \=0D + {}, = \=0D + { = \=0D + 1, /* SizePropertyValid */ = \=0D + 1, /* NumberOfSetsValid */ = \=0D + 1, /* AssociativityValid */ = \=0D + 1, /* AllocationTypeValid */ = \=0D + 1, /* CacheTypeValid */ = \=0D + 1, /* WritePolicyValid */ = \=0D + 1, /* LineSizeValid */ = \=0D + }, = \=0D + 0, /* NextLevelOfCache */ = \=0D + SIZE_2MB, /* Size */ = \=0D + 2048, /* NumberOfSets */ = \=0D + 16, /* Associativity */ = \=0D + { = \=0D + EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, = \=0D + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \=0D + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \=0D + }, = \=0D + 64 /* LineSize */ = \=0D + }, { = \=0D + PPTT_CORE(pid, cid, 0), = \=0D + PPTT_CORE(pid, cid, 1), = \=0D + } = \=0D +}=0D +=0D +#define PPTT_PANEL(pid) { = \=0D + { = \=0D + EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, = \=0D + FIELD_OFFSET (PHYTIUM_PPTT_PACKAGE, L3Cache), = \=0D + {}, = \=0D + { = \=0D + 1, /* PhysicalPackage */ = \=0D + EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid = */ \=0D + }, = \=0D + 0, /* Parent */ = \=0D + 0, /* AcpiProcessorId */ = \=0D + 1, /* NumberOfPrivateResour= ces */ \=0D + }, { = \=0D + FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid].L3Cache), = \=0D + }, { = \=0D + EFI_ACPI_6_2_PPTT_TYPE_CACHE, = \=0D + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), = \=0D + {}, = \=0D + { = \=0D + 1, /* SizePropertyValid */ = \=0D + 1, /* NumberOfSetsValid */ = \=0D + 1, /* AssociativityValid */= \=0D + 0, /* AllocationTypeValid *= / \=0D + 1, /* CacheTypeValid */ = \=0D + 1, /* WritePolicyValid */ = \=0D + 1, /* LineSizeValid */ = \=0D + }, = \=0D + 0, /* NextLevelOfCache */ = \=0D + SIZE_4MB, /* Size */ = \=0D + 4096, /* NumberOfSets */ = \=0D + 16, /* Associativity */ = \=0D + { = \=0D + 0, = \=0D + EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, = \=0D + EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, = \=0D + }, = \=0D + 64 /* LineSize */ = \=0D + }, { = \=0D + PPTT_CLUSTER (pid, 0), = \=0D + PPTT_CLUSTER (pid, 1), = \=0D + }, { = \=0D + EFI_ACPI_6_2_PPTT_TYPE_ID, = \=0D + sizeof(EFI_ACPI_6_2_PPTT_STRUCTURE_ID), = \=0D + {0}, = \=0D + 0x54594850, = \=0D + 0x3, = \=0D + 0x1, = \=0D + 0, = \=0D + 0, = \=0D + 0, = \=0D + } = \=0D +}=0D +=0D +=0D +STATIC PHYTIUM_PPTT_TABLE mPhytiumPpttTable =3D {=0D + {=0D + PHYTIUM_ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_S= TRUCTURE_SIGNATURE,=0D + PHYTIUM_PPTT_TABLE,=0D + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISIO= N),=0D + },=0D + {=0D + PPTT_PANEL(0)=0D + }=0D +};=0D +=0D +VOID * CONST ReferenceAcpiTable =3D &mPhytiumPpttTable;=0D diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Spcr.aslc b/S= ilicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Spcr.aslc new file mode 100644 index 000000000000..114ec9933738 --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Spcr.aslc @@ -0,0 +1,83 @@ +/** @file=0D + Phytium ACPI ASL Sources.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + * References:=0D + * Serial Port Console Redirection Table Specification Version 1.03 - Augu= st 10, 2015=0D + **/=0D +=0D +=0D +///=0D +/// SPCR Flow Control=0D +///=0D +#define SPCR_FLOW_CONTROL_NONE 0=0D +=0D +=0D +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr =3D {=0D + PHYTIUM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_= SIGNATURE,=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISI= ON),=0D + // UINT8 InterfaceType;=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_= UART,=0D + // UINT8 Reserved1[3];=0D + {=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE,=0D + EFI_ACPI_RESERVED_BYTE=0D + },=0D + // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;=0D + ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)),=0D + // UINT8 InterruptType;=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,=0D + // UINT8 Irq;=0D + 0, // Not used on ARM=0D + // UINT32 GlobalSystemInterrupt;=0D + FixedPcdGet32 (PL011UartInterrupt),=0D + // UINT8 BaudRate;=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,=0D + // UINT8 Parity;=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,=0D + // UINT8 StopBits;=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,=0D + // UINT8 FlowControl;=0D + SPCR_FLOW_CONTROL_NONE,=0D + // UINT8 TerminalType;=0D + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,=0D + // UINT8 Reserved2;=0D + EFI_ACPI_RESERVED_BYTE,=0D + // UINT16 PciDeviceId;=0D + 0xFFFF,=0D + // UINT16 PciVendorId;=0D + 0xFFFF,=0D + // UINT8 PciBusNumber;=0D + 0x00,=0D + // UINT8 PciDeviceNumber;=0D + 0x00,=0D + // UINT8 PciFunctionNumber;=0D + 0x00,=0D + // UINT32 PciFlags;=0D + 0x00000000,=0D + // UINT8 PciSegment;=0D + 0x00,=0D + // UINT32 Reserved3;=0D + EFI_ACPI_RESERVED_DWORD=0D +};=0D +=0D +//=0D +// Reference the table being generated to prevent the optimizer from remov= ing the=0D +// data structure from the executable=0D +//=0D +VOID* CONST ReferenceAcpiTable =3D &Spcr;=0D --=20 2.25.1