From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by mx.groups.io with SMTP id smtpd.web09.1486.1610700549642996378 for ; Fri, 15 Jan 2021 00:49:10 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: phytium.com.cn, ip: 206.189.21.223, mailfrom: jialing@phytium.com.cn) Received: from localhost.localdomain (unknown [117.136.88.47]) by c1app12 (Coremail) with SMTP id DAINCgDHzpbFVgFgExlyBA--.39669S7; Fri, 15 Jan 2021 16:49:06 +0800 (CST) From: Ling Jia To: devel@edk2.groups.io Cc: Leif Lindholm , Ling , Peng Xie , Yiqi Shu Subject: [PATCH v1 05/10] Silicon/Phytium: Added PciHostBridgeLib to Phytium2000-4 Date: Fri, 15 Jan 2021 08:47:57 +0000 Message-Id: <20210115084802.62196-6-jialing@phytium.com.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115084802.62196-1-jialing@phytium.com.cn> References: <20210115084802.62196-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: DAINCgDHzpbFVgFgExlyBA--.39669S7 X-Coremail-Antispam: 1UD129KBjvJXoW3tw43Kr1fCrykur4rurWxZwb_yoWDXF15pF 4jyws8X34DX3Wjvw4Fy3s7WF43Aa9Fkw45tr13Xa42vryfXF4kJrsFka43Wa4UX3Wjqa1x W3WYqFyru3Z0gaUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBG14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr1j 6rxdM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6x IIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_ Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVAFwVW8Zw CF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j 6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64 vIr41lIxAIcVC0I7IYx2IY67AKxVWUCVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_ Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0x vEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUfhLnUUUUU= X-Originating-IP: [117.136.88.47] X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Content-Transfer-Encoding: quoted-printable From: Ling The Pci host bridge library is mainly to get Pci bridge information. Cc: Leif Lindholm Signed-off-by: Ling Jia Signed-off-by: Peng Xie Reviewed-by: Yiqi Shu --- Platform/Phytium/Durian/DurianPkg.dsc = | 9 + Platform/Phytium/Durian/DurianPkg.fdf = | 9 + Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.in= f | 55 ++++++ Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.c = | 182 ++++++++++++++++++++ 4 files changed, 255 insertions(+) diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Duria= n/DurianPkg.dsc index a765ce0126b5..09c90d590347 100644 --- a/Platform/Phytium/Durian/DurianPkg.dsc +++ b/Platform/Phytium/Durian/DurianPkg.dsc @@ -39,6 +39,7 @@ [LibraryClasses.common] [LibraryClasses.common.DXE_DRIVER]=0D # Pci dependencies=0D PciSegmentLib|Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSeg= mentLib.inf=0D + PciHostBridgeLib|Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/= PciHostBridgeLib.inf=0D =0D ##########################################################################= ######=0D #=0D @@ -274,6 +275,14 @@ [Components.common] MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf=0D MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D =0D + #=0D + # PCI Support=0D + #=0D + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf=0D + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf=0D + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDevic= eDxe.inf=0D +=0D #=0D # The following 2 module perform the same work except one operate variab= le.=0D # Only one of both should be put into fdf.=0D diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Duria= n/DurianPkg.fdf index 98d3e07999ee..d50b2116b99a 100644 --- a/Platform/Phytium/Durian/DurianPkg.fdf +++ b/Platform/Phytium/Durian/DurianPkg.fdf @@ -109,6 +109,9 @@ [FV.FvMain] INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf=0D INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.i= nf=0D =0D + # Required by PCI=0D + INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf=0D +=0D #=0D # ACPI Support=0D #=0D @@ -135,6 +138,12 @@ [FV.FvMain] INF FatPkg/EnhancedFatDxe/Fat.inf=0D INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.i= nf=0D =0D + #=0D + # PCI Support=0D + #=0D + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf=0D + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D +=0D #=0D # SATA Controller=0D #=0D diff --git a/Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHost= BridgeLib.inf b/Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciH= ostBridgeLib.inf new file mode 100644 index 000000000000..70b8496e06d4 --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeL= ib.inf @@ -0,0 +1,55 @@ +#/** @file=0D +# PCI Host Bridge Library instance for Phytium SOC.=0D +#=0D +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#**/=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010019=0D + BASE_NAME =3D PciHostBridgeLib=0D + FILE_GUID =3D f965de0e-40fe-11eb-8290-3f9d1f895a80= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D PciHostBridgeLib|DXE_DRIVER=0D +=0D +#=0D +# The following information is for reference only and not required by the = build=0D +# tools.=0D +#=0D +# VALID_ARCHITECTURES =3D ARM AARCH64=0D +#=0D +=0D +[Sources]=0D + PciHostBridgeLib.c=0D +=0D +[Packages]=0D + ArmPkg/ArmPkg.dec=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + Silicon/Phytium/Phytium.dec=0D +=0D +[LibraryClasses]=0D + ArmLib=0D + DebugLib=0D + DevicePathLib=0D + MemoryAllocationLib=0D + HobLib=0D +=0D +[Guids]=0D + gPhytiumPlatformPciHostInforGuid=0D +=0D +[FixedPcd]=0D + gArmTokenSpaceGuid.PcdPciBusMin=0D + gArmTokenSpaceGuid.PcdPciBusMax=0D + gArmTokenSpaceGuid.PcdPciIoBase=0D + gArmTokenSpaceGuid.PcdPciIoSize=0D + gArmTokenSpaceGuid.PcdPciIoTranslation=0D + gArmTokenSpaceGuid.PcdPciMmio32Base=0D + gArmTokenSpaceGuid.PcdPciMmio32Size=0D + gArmTokenSpaceGuid.PcdPciMmio32Translation=0D + gArmTokenSpaceGuid.PcdPciMmio64Base=0D + gArmTokenSpaceGuid.PcdPciMmio64Size=0D + gArmTokenSpaceGuid.PcdPciMmio64Translation=0D diff --git a/Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHost= BridgeLib.c b/Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHos= tBridgeLib.c new file mode 100644 index 000000000000..ee9a79d73107 --- /dev/null +++ b/Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeL= ib.c @@ -0,0 +1,182 @@ +/** @file=0D + PCI Host Bridge Library instance for Phytium SOC.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#pragma pack(1)=0D +=0D +typedef struct {=0D + ACPI_HID_DEVICE_PATH AcpiDevicePath;=0D + EFI_DEVICE_PATH_PROTOCOL EndDevicePath;=0D +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;=0D +=0D +#pragma pack ()=0D +=0D +#define END_DEVICE_PATH_DEF { END_DEVICE_PATH_TYPE, \=0D + END_ENTIRE_DEVICE_PATH_SUBTYPE, \=0D + { END_DEVICE_PATH_LENGTH, 0 } \=0D + }=0D +=0D +#define ACPI_DEVICE_PATH_DEF(UID) {{ ACPI_DEVICE_PATH, ACPI_DP, \=0D + {(UINT8)(sizeof (ACPI_HID_DEVICE_PATH)= ), (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)} \=0D + }, \=0D + EISA_PNP_ID (0x0A03), UID \=0D + }=0D +=0D +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[]= =3D {=0D + {=0D + ACPI_DEVICE_PATH_DEF(0),=0D + END_DEVICE_PATH_DEF=0D + },=0D +};=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED=0D +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D {=0D + L"Mem", L"I/O", L"Bus"=0D +};=0D +=0D +STATIC PCI_ROOT_BRIDGE mRootBridge =3D {=0D + 0, // Segment=0D + 0, // Supports=0D + 0, // Attributes=0D + TRUE, // DmaAbove4G=0D + FALSE, // NoExtendedConfigSpace= =0D + FALSE, // ResourceAssigned=0D + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes= =0D + EFI_PCI_HOST_BRIDGE_MEM64_DECODE,=0D + {=0D + // Bus=0D + FixedPcdGet32 (PcdPciBusMin),=0D + FixedPcdGet32 (PcdPciBusMax)=0D + }, {=0D + // Io=0D + FixedPcdGet64 (PcdPciIoBase),=0D + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1=0D + }, {=0D + // Mem=0D + FixedPcdGet32 (PcdPciMmio32Base),=0D + FixedPcdGet32 (PcdPciMmio32Base) + (FixedPcdGet32 (PcdPciMmio32Size) -= 1)=0D + //0x7FFFFFFF=0D + }, {=0D + // MemAbove4G=0D + FixedPcdGet64 (PcdPciMmio64Base),=0D + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - = 1=0D + }, {=0D + // PMem=0D + MAX_UINT64,=0D + 0=0D + }, {=0D + // PMemAbove4G=0D + MAX_UINT64,=0D + 0=0D + },=0D + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath=0D +};=0D +=0D +/**=0D + Return all the root bridge instances in an array.=0D +=0D + @param[out] Count Return the count of root bridge instances.=0D +=0D + @return All the root bridge instances in an array.=0D + The array should be passed into PciHostBridgeFreeRootBridges()=0D + when it's not used.=0D +=0D +**/=0D +PCI_ROOT_BRIDGE *=0D +EFIAPI=0D +PciHostBridgeGetRootBridges (=0D + OUT UINTN *Count=0D + )=0D +{=0D + *Count =3D 1;=0D + return &mRootBridge;=0D +}=0D +=0D +=0D +/**=0D + Free the root bridge instances array returned from PciHostBridgeGetRootB= ridges().=0D +=0D + @param[in] Bridges The root bridge instances array.=0D + @param[in] Count The count of the array.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +PciHostBridgeFreeRootBridges (=0D + IN PCI_ROOT_BRIDGE *Bridges,=0D + IN UINTN Count=0D + )=0D +{=0D +=0D +}=0D +=0D +=0D +/**=0D + Inform the platform that the resource conflict happens.=0D +=0D + @param[in] HostBridgeHandle Handle of the Host Bridge.=0D + @param[in] Configuration Pointer to PCI I/O and PCI memory resource=0D + descriptors. The Configuration contains the reso= urces=0D + for all the root bridges. The resource for each = root=0D + bridge is terminated with END descriptor and an= =0D + additional END is appended indicating the end of= the=0D + entire resources. The resource descriptor field= =0D + values follow the description in=0D + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL= =0D + SubmitResources().=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +PciHostBridgeResourceConflict (=0D + IN EFI_HANDLE HostBridgeHandle,=0D + IN VOID *Configuration=0D + )=0D +{=0D + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;=0D + UINTN RootBridgeIndex;=0D +=0D + RootBridgeIndex =3D 0;=0D + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;=0D + while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) {=0D + for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript= or++) {=0D + ASSERT (Descriptor->ResType <=0D + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));=0D + DEBUG ((DEBUG_INFO, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n",=0D + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType= ],=0D + Descriptor->AddrLen, Descriptor->AddrRangeMax=0D + ));=0D + if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) {=0D + DEBUG ((DEBUG_INFO, " Granularity/SpecificFlag =3D %ld / %02x%= s\n",=0D + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag= ,=0D + ((Descriptor->SpecificFlag &=0D + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETC= HABLE=0D + ) !=3D 0) ? L" (Prefetchable)" : L""=0D + ));=0D + }=0D + }=0D + //=0D + // Skip the end descriptor for root bridge=0D + //=0D + ASSERT (Descriptor->Desc =3D=3D ACPI_END_TAG_DESCRIPTOR);=0D + Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(=0D + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1=0D + );=0D + }=0D +}=0D --=20 2.25.1