From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from zg8tmja2lje4os4yms4ymjma.icoremail.net (zg8tmja2lje4os4yms4ymjma.icoremail.net [206.189.21.223]) by mx.groups.io with SMTP id smtpd.web12.1404.1610700563932542978 for ; Fri, 15 Jan 2021 00:49:24 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: phytium.com.cn, ip: 206.189.21.223, mailfrom: jialing@phytium.com.cn) Received: from localhost.localdomain (unknown [117.136.88.47]) by c1app12 (Coremail) with SMTP id DAINCgDHzpbFVgFgExlyBA--.39669S10; Fri, 15 Jan 2021 16:49:15 +0800 (CST) From: Ling Jia To: devel@edk2.groups.io Cc: Leif Lindholm , Ling , Peng Xie , Yiqi Shu Subject: [PATCH v1 08/10] Silicon/Phytium: Added flash driver support to Phytium Silicon Date: Fri, 15 Jan 2021 08:48:00 +0000 Message-Id: <20210115084802.62196-9-jialing@phytium.com.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210115084802.62196-1-jialing@phytium.com.cn> References: <20210115084802.62196-1-jialing@phytium.com.cn> MIME-Version: 1.0 X-CM-TRANSID: DAINCgDHzpbFVgFgExlyBA--.39669S10 X-Coremail-Antispam: 1UD129KBjvAXoW3tw43Kr1kCF1fWr4UWF1rZwb_yoW8Cw1UAo WxZa1F9rWftrWSvFWDXr9rGa1xXFnavanxtw40yr9xXa97Xw43GrWIya1UXr45t348G3Zx G3yfXasxJFW7Jan5n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUY_7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r 4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26F4U JVW0owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7V C0I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j 6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE14v_GF yl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWU JVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7V AKI48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42 IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUeeHqDUUUU X-Originating-IP: [117.136.88.47] X-CM-SenderInfo: xmldzxdqj61x51wl3zoofrzhdfq/ Content-Transfer-Encoding: quoted-printable From: Ling The PhytiumSpiNorFlashDxe provided norflash initialization, read-write, erase and other interfaces. Cc: Leif Lindholm Signed-off-by: Ling Jia Signed-off-by: Peng Xie Reviewed-by: Yiqi Shu --- Platform/Phytium/Durian/DurianPkg.dsc = | 5 + Platform/Phytium/Durian/DurianPkg.fdf = | 5 + Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.= inf | 54 +++ Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.= h | 106 +++++ Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h = | 74 ++++ Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.= c | 435 ++++++++++++++++++++ 6 files changed, 679 insertions(+) diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Duria= n/DurianPkg.dsc index a23c1d52cece..d34432e95049 100644 --- a/Platform/Phytium/Durian/DurianPkg.dsc +++ b/Platform/Phytium/Durian/DurianPkg.dsc @@ -261,6 +261,11 @@ [Components.common] #=0D Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf=0D =0D + #=0D + # NOR Flash driver=0D + #=0D + Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDx= e.inf=0D +=0D #=0D # Usb Support=0D #=0D diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Duria= n/DurianPkg.fdf index ad0406b3133b..703537033944 100644 --- a/Platform/Phytium/Durian/DurianPkg.fdf +++ b/Platform/Phytium/Durian/DurianPkg.fdf @@ -110,6 +110,11 @@ [FV.FvMain] #=0D INF Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.in= f=0D =0D + #=0D + # NOR Flash driver=0D + #=0D + INF Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFla= shDxe.inf=0D +=0D # Variable services=0D INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf=0D INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.i= nf=0D diff --git a/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpi= NorFlashDxe.inf b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/Phyti= umSpiNorFlashDxe.inf new file mode 100644 index 000000000000..2979dad60c1e --- /dev/null +++ b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlas= hDxe.inf @@ -0,0 +1,54 @@ +#/** @file=0D +# Phytium NorFlash Drivers.=0D +#=0D +# Copyright (C) 2020, Phytium Technology Co,Ltd. All rights reserved.
= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#**/=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010019=0D + BASE_NAME =3D PhytiumSpiNorFlashDxe=0D + FILE_GUID =3D f37ef706-187c-48fd-9102-ddbf86f551be= =0D + MODULE_TYPE =3D DXE_RUNTIME_DRIVER=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D NorFlashPlatformEntryPoint=0D +=0D +[Sources.common]=0D + PhytiumSpiNorFlashDxe.c=0D + PhytiumSpiNorFlashDxe.h=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + ArmPkg/ArmPkg.dec=0D + ArmPlatformPkg/ArmPlatformPkg.dec=0D + Silicon/Phytium/Phytium.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + PcdLib=0D + IoLib=0D + UefiBootServicesTableLib=0D + DxeServicesTableLib=0D + UefiRuntimeLib=0D + UefiLib=0D + UefiDriverEntryPoint=0D +=0D +[FixedPcd]=0D + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase=0D + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize=0D + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase=0D + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize=0D +=0D +[Guids]=0D + gEfiEventVirtualAddressChangeGuid=0D +=0D +[Protocols]=0D + gPhytiumSpiMasterProtocolGuid=0D + gPhytiumFlashProtocolGuid=0D +=0D + [Depex]=0D + TRUE=0D + #gPhytiumSpiMasterProtocolGuid=0D diff --git a/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpi= NorFlashDxe.h b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/Phytium= SpiNorFlashDxe.h new file mode 100644 index 000000000000..caee5591f3bd --- /dev/null +++ b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlas= hDxe.h @@ -0,0 +1,106 @@ +/** @file=0D + Phytium NorFlash Drivers Header.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef __PHYTIUM_SPI_NORFALSH_DXE_H__=0D +#define __PHYTIUM_SPI_NORFALSH_DXE_H__=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Phytium Norflash registers=0D +**/=0D +#define REG_FLASH_CAP 0x000=0D +#define REG_RD_CFG 0x004=0D +#define REG_WR_CFG 0x008=0D +#define REG_FLUSH_REG 0x00C=0D +#define REG_CMD_PORT 0x010=0D +#define REG_ADDR_PORT 0x014=0D +#define REG_HD_PORT 0x018=0D +#define REG_LD_PORT 0x01C=0D +#define REG_CS_CFG 0x020=0D +#define REG_WIP_CFG 0x024=0D +#define REG_WP_REG 0x028=0D +=0D +#define NORFLASH_SIGNATURE SIGNATURE_32 ('P', 'T', 'Y', 'T')=0D +=0D +//=0D +// Platform Nor Flash Functions=0D +//=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformEraseSingleBlock (=0D + IN UINTN BlockAddress=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformErase (=0D + IN UINT64 Offset,=0D + IN UINT64 Length=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformRead (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + OUT UINT32 Len=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformWrite (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + IN UINT32 Len=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformGetDevices (=0D + OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformInitialization (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformEntryPoint (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + );=0D +=0D +typedef struct {=0D + EFI_NORFLASH_DRV_PROTOCOL FlashProtocol;=0D + UINTN Signature;=0D + EFI_HANDLE Handle;=0D +} PHYT_NorFlash_Device;=0D +=0D +#endif /* __PHYTIUM_SPI_NORFALSH_DXE_H__ */=0D diff --git a/Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h b/Silico= n/Phytium/Include/Protocol/PhytiumSpiNorFlash.h new file mode 100644 index 000000000000..84c83dbd88eb --- /dev/null +++ b/Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h @@ -0,0 +1,74 @@ +/** @file=0D + The Header of Protocol For NorFlash.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef __PHYTIUM_SPI_NORFALSH_H__=0D +#define __PHYTIUM_SPI_NORFALSH_H__=0D +=0D +typedef struct _EFI_NORFLASH_DRV_PROTOCOL EFI_NORFLASH_DRV_PROTOCOL;=0D +extern EFI_GUID gPhytiumFlashProtocolGuid;=0D +=0D +typedef struct {=0D + UINTN DeviceBaseAddress; // Start address of the Device Base Ad= dress (DBA)=0D + UINTN RegionBaseAddress; // Start address of one single region= =0D + UINTN Size;=0D + UINTN BlockSize;=0D + EFI_GUID Guid;=0D +} NOR_FLASH_DEVICE_DESCRIPTION;=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *NORFLASH_PLATFORM_ERASE_INTERFACE) (=0D + IN UINT64 Offset,=0D + IN UINT64 Length=0D + );=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE) (=0D + IN UINTN BlockAddress=0D + );=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *NORFLASH_PLATFORM_READ_INTERFACE) (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + OUT UINT32 Len=0D + );=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *NORFLASH_PLATFORM_WRITE_INTERFACE) (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + IN UINT32 Len=0D + );=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *NORFLASH_PLATFORM_GETDEVICE_INTERFACE) (=0D + OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices=0D + );=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *NORFLASH_PLATFORM_INIT_INTERFACE) (=0D + VOID=0D + );=0D +=0D +struct _EFI_NORFLASH_DRV_PROTOCOL{=0D + NORFLASH_PLATFORM_INIT_INTERFACE Initialization;=0D + NORFLASH_PLATFORM_GETDEVICE_INTERFACE GetDevices;=0D + NORFLASH_PLATFORM_ERASE_INTERFACE Erase;=0D + NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE EraseSingleBlock;=0D + NORFLASH_PLATFORM_READ_INTERFACE Read;=0D + NORFLASH_PLATFORM_WRITE_INTERFACE Write;=0D +};=0D +=0D +#endif /* __PHYTIUM_SPI_NORFALSH_H__*/=0D diff --git a/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpi= NorFlashDxe.c b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/Phytium= SpiNorFlashDxe.c new file mode 100644 index 000000000000..2614035e0714 --- /dev/null +++ b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlas= hDxe.c @@ -0,0 +1,435 @@ +/** @file=0D + Phytium NorFlash Drivers.=0D +=0D + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "PhytiumSpiNorFlashDxe.h"=0D +=0D +typedef struct {=0D + UINT32 Flash_Index;=0D + UINT32 Flash_Write;=0D + UINT32 Flash_Erase;=0D + UINT32 Flash_Pp;=0D +}FLASH_CMD_INFO;=0D +=0D +STATIC EFI_EVENT mSpiNorFlashVirtualAddrChangeEvent;=0D +STATIC UINTN mNorFlashControlBase;=0D +STATIC UINT32 mCmd_Write;=0D +STATIC UINT32 mCmd_Eares;=0D +STATIC UINT32 mCmd_Pp;=0D +=0D +#define SPI_FLASH_BASE FixedPcdGet64 (PcdSpiFlashBase)=0D +#define SPI_FLASH_SIZE FixedPcdGet64 (PcdSpiFlashSize)=0D +=0D +EFI_SPI_DRV_PROTOCOL *pSpiMasterProtocol;=0D +extern EFI_GUID gPhytiumSpiMasterProtocolGuid;=0D +PHYT_NorFlash_Device *flash_Instance;=0D +extern EFI_GUID gPhytiumFlashProtocolGuid;=0D +=0D +NOR_FLASH_DEVICE_DESCRIPTION mNorFlashDevices =3D {=0D + SPI_FLASH_BASE, /* Device Base Address */=0D + SPI_FLASH_BASE, /* Region Base Address */=0D + SIZE_1MB * 16, /* Size */=0D + SIZE_64KB, /* Block Size */=0D + {0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5= E, 0x59 } }=0D +};=0D +=0D +=0D +/**=0D + This function writed up to 256 bytes to flash through spi driver.=0D +=0D + @param[in] Address The address of the flash.=0D + @param[in] Buffer The pointer of buffer to be writed.=0D + @param[in] BufferSizeInBytes The bytes to be writed.=0D +=0D + @retval EFI_SUCCESS NorFlashWrite256() is executed successfull= y.=0D +=0D +**/=0D +STATIC=0D +EFI_STATUS=0D +NorFlashWrite256 (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + IN UINT32 BufferSizeInBytes=0D + )=0D +{=0D + UINT32 Index;=0D + UINT8 Cmd_id;=0D + UINT32 *TemBuffer;=0D +=0D + TemBuffer=3D Buffer;=0D +=0D + if(BufferSizeInBytes > 256) {=0D + DEBUG((DEBUG_ERROR, "The max length is 256 bytes.\n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + if(BufferSizeInBytes % 4 !=3D 0) {=0D + DEBUG((DEBUG_ERROR, "The length must four bytes aligned.\n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + if(Address % 4 !=3D 0) {=0D + DEBUG((DEBUG_ERROR, "The address must four bytes aligned.\n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Cmd_id =3D (UINT8)(mCmd_Pp & 0xff);=0D + pSpiMasterProtocol->SpiSetConfig (Cmd_id, 0x400000, REG_CMD_PORT);=0D + pSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);=0D +=0D + asm volatile ("isb sy":::"cc");=0D +=0D + Cmd_id =3D (UINT8)(mCmd_Write & 0xff);=0D + pSpiMasterProtocol->SpiSetConfig (Cmd_id, 0x000208, REG_WR_CFG);=0D +=0D + for(Index =3D 0; Index < BufferSizeInBytes / 4; Index++) {=0D + MmioWrite32(Address + Index * 4, TemBuffer[Index]);=0D + }=0D +=0D + asm volatile ("isb sy":::"cc");=0D +=0D + pSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_FLUSH_REG);=0D +=0D + asm volatile ("isb sy":::"cc");=0D +=0D + pSpiMasterProtocol->SpiSetConfig (0, 0x0, REG_WR_CFG);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + This function erased a sector of flash through spi driver.=0D +=0D + @param[in] BlockAddress The sector address to be erased.=0D +=0D + @retval None.=0D +=0D +**/=0D +STATIC=0D +inline void=0D +NorFlashPlatformEraseSector (=0D + IN UINTN BlockAddress=0D + )=0D +{=0D + UINT8 Cmd_id =3D 0;=0D +=0D + Cmd_id =3D (UINT8)(mCmd_Pp & 0xff);=0D + pSpiMasterProtocol->SpiSetConfig (Cmd_id, 0x400000, REG_CMD_PORT);=0D + pSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);=0D +=0D + asm volatile ("isb sy":::"cc");=0D +=0D + Cmd_id =3D (UINT8)(mCmd_Eares & 0xff);=0D + pSpiMasterProtocol->SpiSetConfig (Cmd_id, 0x408000, REG_CMD_PORT);=0D + pSpiMasterProtocol->SpiSetConfig (0, BlockAddress, REG_ADDR_PORT);=0D + pSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);=0D +=0D + asm volatile ("isb sy":::"cc");=0D +}=0D +=0D +=0D +/**=0D + Fixup internal data so that EFI can be call in virtual mode.=0D + Call the passed in Child Notify event and convert any pointers in=0D + lib to virtual mode.=0D +=0D + @param[in] Event The Event that is being processed.=0D +=0D + @param[in] Context Event Context.=0D +=0D + @retval None.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +PlatformNorFlashVirtualNotifyEvent (=0D + IN EFI_EVENT Event,=0D + IN VOID *Context=0D + )=0D +{=0D + EfiConvertPointer (0x0, (VOID **)&mNorFlashControlBase);=0D + EfiConvertPointer (0x0, (VOID**)&pSpiMasterProtocol->SpiGetConfig);=0D + EfiConvertPointer (0x0, (VOID**)&pSpiMasterProtocol->SpiSetConfig);=0D + EfiConvertPointer (0x0, (VOID**)&pSpiMasterProtocol);=0D +}=0D +=0D +=0D +/**=0D + This function inited the flash platform.=0D +=0D + @param None.=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformInitialization() is execut= ed successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformInitialization (=0D + VOID=0D + )=0D +{=0D +=0D + mCmd_Write =3D 0x2;=0D + mCmd_Eares =3D 0xD8;=0D + mCmd_Pp =3D 0x6;=0D +=0D + mNorFlashControlBase =3D FixedPcdGet64 (PcdSpiControllerBase);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + This function geted the flash device information.=0D +=0D + @param[out] NorFlashDevices the pointer to store flash device informa= tion.=0D + @param[out] Count the number of the flash device.=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformGetDevices() is executed s= uccessfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformGetDevices (=0D + OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices=0D + )=0D +{=0D +=0D + *NorFlashDevices =3D mNorFlashDevices;=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + This function readed flash content form the specified area of flash.=0D +=0D + @param[in] Address The address of the flash.=0D + @param[in] Buffer The pointer of the Buffer to be stored.=0D + @param[out] Len The bytes readed form flash.=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformRead() is executed succes= sfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformRead (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + OUT UINT32 Len=0D + )=0D +{=0D +=0D + DEBUG((DEBUG_BLKIO, "NorFlashPlatformRead: Address: 0x%lx Buffer:0x%p Le= n:0x%x\n", Address, Buffer, Len));=0D +=0D + CopyMem ((VOID *)Buffer, (VOID *)Address, Len);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + This function erased one block flash content.=0D +=0D + @param[in] BlockAddress the BlockAddress to be erased.=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformEraseSingleBlock() is exe= cuted successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformEraseSingleBlock (=0D + IN UINTN BlockAddress=0D + )=0D +{=0D +=0D + NorFlashPlatformEraseSector (BlockAddress);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + This function erased the flash content of the specified area.=0D +=0D + @param[in] Offset the offset of the flash.=0D + @param[in] Length length to be erased.=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformErase() is executed succe= ssfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformErase (=0D + IN UINT64 Offset,=0D + IN UINT64 Length=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT64 Index;=0D + UINT64 Count;=0D +=0D + Status =3D EFI_SUCCESS;=0D + if ((Length % SIZE_64KB) =3D=3D 0) {=0D + Count =3D Length / SIZE_64KB;=0D + for (Index =3D 0; Index < Count; Index++) {=0D + NorFlashPlatformEraseSingleBlock (Offset);=0D + Offset +=3D SIZE_64KB;=0D + }=0D + } else {=0D + Status =3D EFI_INVALID_PARAMETER;=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +=0D +/**=0D + This function writed data to flash.=0D +=0D + @param[in] Address the address of the flash.=0D +=0D + @param[in] Buffer the pointer of the Buffer to be writed.=0D +=0D + @param[in] BufferSizeInBytes the bytes of the Buffer.=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformWrite() is executed succe= ssfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformWrite (=0D + IN UINTN Address,=0D + IN VOID *Buffer,=0D + IN UINT32 BufferSizeInBytes=0D + )=0D +{=0D + UINT32 Index;=0D + UINT32 Remainder;=0D + UINT32 Quotient;=0D + EFI_STATUS Status;=0D + UINTN TmpAddress;=0D +=0D + DEBUG((DEBUG_BLKIO, "NorFlashPlatformWrite: Address: 0x%x Len:0x%x.\n", = Address, BufferSizeInBytes));=0D +=0D + Index =3D 0;=0D + Remainder =3D 0;=0D + Quotient =3D 0;=0D + TmpAddress =3D Address;=0D + Remainder =3D BufferSizeInBytes % 256;=0D + Quotient =3D BufferSizeInBytes / 256;=0D +=0D + if(BufferSizeInBytes <=3D 256) {=0D + Status =3D NorFlashWrite256 (TmpAddress, Buffer, BufferSizeInBytes);=0D + } else {=0D + for(Index =3D 0; Index < Quotient; Index++) {=0D + Status =3D NorFlashWrite256 (TmpAddress, Buffer, 256);=0D + TmpAddress +=3D 256;=0D + Buffer +=3D 256;=0D + }=0D +=0D + if(Remainder !=3D 0) {=0D + Status =3D NorFlashWrite256 (TmpAddress, Buffer, Remainder);=0D + }=0D + }=0D +=0D + if(EFI_ERROR(Status)) {=0D + ASSERT_EFI_ERROR(Status);=0D + }=0D +=0D + return EFI_SUCCESS;=0D +=0D +}=0D +=0D +=0D +/**=0D + This function inited the flash driver protocol.=0D +=0D + @param[in] NorFlashProtocol A pointer to the norflash protocol struct= .=0D +=0D + @retval EFI_SUCCESS NorFlashPlatformInitProtocol() is executed suc= cessfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformInitProtocol (=0D + IN EFI_NORFLASH_DRV_PROTOCOL *NorFlashProtocol=0D + )=0D +{=0D + NorFlashProtocol->Initialization =3D NorFlashPlatformInitialization;= =0D + NorFlashProtocol->GetDevices =3D NorFlashPlatformGetDevices;=0D + NorFlashProtocol->Erase =3D NorFlashPlatformErase;=0D + NorFlashProtocol->EraseSingleBlock =3D NorFlashPlatformEraseSingleBlock= ;=0D + NorFlashProtocol->Read =3D NorFlashPlatformRead;=0D + NorFlashProtocol->Write =3D NorFlashPlatformWrite;=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + This function is the entrypoint of the norflash driver.=0D +=0D + @param[in] ImageHandle The firmware allocated handle for the EFI imag= e.=0D +=0D + @param[in] SystemTable A pointer to the EFI System Table.=0D +=0D + @retval EFI_SUCCESS The entry point is executed successfully.=0D +=0D + @retval other Some error occurs when executing this entry po= int.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +NorFlashPlatformEntryPoint (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + Status =3D gBS->LocateProtocol (=0D + &gPhytiumSpiMasterProtocolGuid,=0D + NULL,=0D + (VOID **)&pSpiMasterProtocol=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return EFI_DEVICE_ERROR;=0D + }=0D +=0D + flash_Instance =3D AllocateRuntimeZeroPool (sizeof (PHYT_NorFlash_Device= ));=0D + if (flash_Instance =3D=3D NULL) {=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D +=0D + NorFlashPlatformInitProtocol (&flash_Instance->FlashProtocol);=0D +=0D + flash_Instance->Signature =3D NORFLASH_SIGNATURE;=0D +=0D + Status =3D gBS->InstallMultipleProtocolInterfaces (=0D + &(flash_Instance->Handle),=0D + &gPhytiumFlashProtocolGuid,=0D + &(flash_Instance->FlashProtocol),=0D + NULL=0D + );=0D + ASSERT_EFI_ERROR(Status);=0D +=0D + //Register for the virtual address change event=0D + Status =3D gBS->CreateEventEx (=0D + EVT_NOTIFY_SIGNAL,=0D + TPL_NOTIFY,=0D + PlatformNorFlashVirtualNotifyEvent,=0D + NULL,=0D + &gEfiEventVirtualAddressChangeGuid,=0D + &mSpiNorFlashVirtualAddrChangeEvent=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return Status;=0D +}=0D +=0D --=20 2.25.1