* [PATCH v1 01/10] Silicon/Phytium/: added PhytiumPlatformLib to Phytium2000-4
2021-01-15 8:47 added support for DurianPkg Ling Jia
@ 2021-01-15 8:47 ` Ling Jia
2021-01-22 13:13 ` Leif Lindholm
2021-01-15 8:47 ` [PATCH v1 02/10] Silicon/Phytium: Added Acpi support " Ling Jia
` (10 subsequent siblings)
11 siblings, 1 reply; 15+ messages in thread
From: Ling Jia @ 2021-01-15 8:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling, Peng Xie, Yiqi Shu
From: Ling <jialing@phytium.com.cn>
The PhytiumPlatformLib supported the system
library for Phytium2000-4 chip.
Maintainers.txt: Adds maintainers and reviewers for the DurianPkg.
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Signed-off-by: Peng Xie <xiepeng@phytium.com.cn>
Reviewed-by: Yiqi Shu <shuyiqi@phytium.com.cn>
---
Silicon/Phytium/Phytium.dec | 60 +++
Silicon/Phytium/Phytium.dsc.inc | 388 ++++++++++++++++++++
Platform/Phytium/Durian/DurianPkg.dsc | 302 +++++++++++++++
Platform/Phytium/Durian/DurianPkg.fdf | 199 ++++++++++
Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf | 66 ++++
Silicon/Phytium/Include/PhytiumSystemServiceInterface.h | 112 ++++++
Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c | 135 +++++++
Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c | 148 ++++++++
Maintainers.txt | 7 +
Silicon/Phytium/Phytium.fdf.inc | 119 ++++++
Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S | 76 ++++
11 files changed, 1612 insertions(+)
diff --git a/Silicon/Phytium/Phytium.dec b/Silicon/Phytium/Phytium.dec
new file mode 100644
index 000000000000..a064fd60a9c5
--- /dev/null
+++ b/Silicon/Phytium/Phytium.dec
@@ -0,0 +1,60 @@
+## @file
+# This package provides common open source Phytium silicon modules.
+#
+# Copyright (C) 2020, Phytium Technology Co,Ltd. All rights reserved.
+#
+# SPDX-License-Identifier:BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = PhytiumPkg
+ PACKAGE_GUID = b34af0b4-3e7c-11eb-a9d0-0738806d2dec
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes]
+ Include # Root include for the package
+
+[Guids.common]
+ gPhytiumPlatformTokenSpaceGuid = { 0x8c3abed4, 0x1fc8, 0x46d3, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xde, 0x76 } }
+ gPhytiumPlatformMemoryInforGuid = { 0xe5d0f31b, 0x18b2, 0x4ec1, { 0xba, 0x20, 0x9c, 0x6d, 0xb7, 0x87, 0x91, 0x79 } }
+ gPhytiumPlatformCpuInforGuid = { 0x60c3c4b0, 0xe189, 0x4cbb, { 0x88, 0x6a, 0x96, 0x87, 0x21, 0xe0, 0xe0, 0xb0 } }
+ gPhytiumPlatformPciHostInforGuid = { 0x24b99cf4, 0x2e51, 0x440e, { 0x8c, 0x7a, 0xea, 0xa2, 0xe0, 0x29, 0x32, 0xf } }
+ gShellSfHiiGuid = {0x7e57433d, 0x1016, 0x407a, { 0x9d, 0xb8, 0xf9, 0x56, 0x12, 0x19, 0x66, 0x16 } }
+
+[PcdsFixedAtBuild.common]
+ #
+ # PCI configuration address space
+ #
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase|0x0|UINT64|0x00000000
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize|0x0|UINT64|0x00000001
+
+ #
+ # PCI configuration address space
+ #
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x0|UINT64|0x00000002
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x0|UINT64|0x00000003
+
+ #
+ # SPI Flash Controller Register Base Address and Size
+ #
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase|0x0|UINT64|0x00000004
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x0|UINT64|0x00000005
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x0|UINT64|0x00000006
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x0|UINT64|0x00000007
+ gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT32|0x00000008
+ gPhytiumPlatformTokenSpaceGuid.PcdLogoFile |{ 0x99, 0x8b, 0xAA, 0x7B, 0xBB, 0x61, 0xD5, 0x11, 0x9A, 0x5D, 0xBB, 0x90, 0x27, 0x3F, 0xC2, 0x4D }|VOID*|0x40000013
+
+[Protocols]
+ gPhytiumSpiMasterProtocolGuid = { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}}
+ gPhytiumFlashProtocolGuid = { 0x00b4af42, 0xfbd0, 0x11ea, { 0x80, 0x3a, 0x27, 0xea, 0x5e, 0x65, 0xe3, 0xf6}}
diff --git a/Silicon/Phytium/Phytium.dsc.inc b/Silicon/Phytium/Phytium.dsc.inc
new file mode 100644
index 000000000000..15b66f6bd55d
--- /dev/null
+++ b/Silicon/Phytium/Phytium.dsc.inc
@@ -0,0 +1,388 @@
+## @file
+# This package provides common open source Phytium silicon modules.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+#
+# SPDX-License-Identifier:BSD-2-Clause-Patent
+#
+##
+
+
+[LibraryClasses.common]
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+
+!if $(TARGET) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+ HttpLib|NetworkPkg/Library/DxeHttpLib/DxeHttpLib.inf
+
+ #
+ # Assume everything is fixed at build
+ #
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ #BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+ # ARM Architectural Libraries
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+ ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+
+ #
+ # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+ # in the debugger will show load and unload commands for symbols. You can cut and paste this
+ # into the command window to load symbols. We should be able to use a script to do this, but
+ # the version of RVD I have does not support scripts accessing system memory.
+ #
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+ AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+
+ #
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+ PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+ VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+ # Scsi Requirements
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+
+ # USB Requirements
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+ # Networking Requirements
+ NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|NetworkPkg/Library/DxeDpcLib/DxeDpcLib.inf
+ UdpIoLib|NetworkPkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|NetworkPkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+ IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+ RngLib|MdePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf
+
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf
+ SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
+
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+ BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
+
+[LibraryClasses.common.SEC]
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+ LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+[LibraryClasses.common.SEC, LibraryClasses.common.PEIM]
+ MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+
+ # UiApp dependencies
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+!endif
+
+!if $(TARGET) != RELEASE
+ DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf
+!endif
+ VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf
+[LibraryClasses.AARCH64.DXE_RUNTIME_DRIVER]
+ #
+ # PSCI support in EL3 may not be available if we are not running under a PSCI
+ # compliant secure firmware, but since the default VExpress EfiResetSystemLib
+ # cannot be supported at runtime (due to the fact that the syscfg MMIO registers
+ # cannot be runtime remapped), it is our best bet to get ResetSystem functionality
+ # on these platforms.
+ #
+ EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
+
+[LibraryClasses.ARM, LibraryClasses.AARCH64]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+ # Add support for GCC stack protector
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+
+[BuildOptions]
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+[BuildOptions.AARCH64.EDKII.DXE_RUNTIME_DRIVER]
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ # If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+ # It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+ # Force the UEFI GIC driver to use GICv2 legacy mode. To use
+ # GICv3 without GICv2 legacy in UEFI, the ARM Trusted Firmware needs
+ # to configure the Non-Secure interrupts in the GIC Redistributors
+ # which is not supported at the moment.
+ gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+ # Indicates if EFI 1.1 ISO 639-2 language supports are obsolete
+ # TRUE - Deprecate global variable LangCodes.
+ # FALSE - Does not deprecate global variable LangCodes.
+ # Deprecate Global Variable LangCodes.
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangDeprecate|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+ gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE
+
+ # DEBUG_ASSERT_ENABLED 0x01
+ # DEBUG_PRINT_ENABLED 0x02
+ # DEBUG_CODE_ENABLED 0x04
+ # CLEAR_MEMORY_ENABLED 0x08
+ # ASSERT_BREAKPOINT_ENABLED 0x10
+ # ASSERT_DEADLOOP_ENABLED 0x20
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+ # DEBUG_INIT 0x00000001 // Initialization
+ # DEBUG_WARN 0x00000002 // Warnings
+ # DEBUG_LOAD 0x00000004 // Load events
+ # DEBUG_FS 0x00000008 // EFI File system
+ # DEBUG_POOL 0x00000010 // Alloc & Free's
+ # DEBUG_PAGE 0x00000020 // Alloc & Free's
+ # DEBUG_INFO 0x00000040 // Verbose
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
+ # DEBUG_VARIABLE 0x00000100 // Variable
+ # DEBUG_BM 0x00000400 // Boot Manager
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver
+ # DEBUG_NET 0x00004000 // SNI Driver
+ # DEBUG_UNDI 0x00010000 // UNDI Driver
+ # DEBUG_LOADFILE 0x00020000 // UNDI Driver
+ # DEBUG_EVENT 0x00080000 // Event messages
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes
+ # DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ #gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+ #gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+ #gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+ # 20ms
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|200000
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ # RunAxf support via Dynamic Shell Command protocol
+ # We want to use the Shell Libraries but don't want it to initialise
+ # automatically. We initialise the libraries when the command is called by the
+ # Shell.
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot
+ gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04
+ gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04
+ gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04
+!endif
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
+!else
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000
+!endif
+
+ # Default platform supported RFC 4646 languages: English & French & Chinese Simplified.
+ # Default Value of PlatformLangCodes Variable.
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US;zh-Hans"
+
+ # Default current RFC 4646 language: Chinese Simplified.
+ # Default Value of PlatformLang Variable.
+ gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang|"en-US"
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
+ #
+ # ACPI Table Version
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt|67
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
+
+[PcdsDynamicDefault.common.DEFAULT]
+ ## This PCD defines the video horizontal resolution.
+ # This PCD could be set to 0 then video resolution could be at highest resolution.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|640
+ ## This PCD defines the video vertical resolution.
+ # This PCD could be set to 0 then video resolution could be at highest resolution.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|480
+
+ ## This PCD defines the Console output row and the default value is 80 according to UEFI spec.
+ # This PCD could be set to 0 then console output could be at max column and max row.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|128
+ ## This PCD defines the Console output column and the default value is 25 according to UEFI spec.
+ # This PCD could be set to 0 then console output could be at max column and max row.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|40
+
+ ## Specify the video horizontal resolution of text setup.
+ # @Prompt Video Horizontal Resolution of Text Setup
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
+
+ ## Specify the video vertical resolution of text setup.
+ # @Prompt Video Vertical Resolution of Text Setup
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
+
+ ## Specify the console output column of text setup.
+ # @Prompt Console Output Column of Text Setup
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|128
+ ## Specify the console output row of text setup.
+ # @Prompt Console Output Row of Text Setup
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|40
+
+ ## The number of seconds that the firmware will wait before initiating the original default boot selection.
+ # A value of 0 indicates that the default boot selection is to be initiated immediately on boot.
+ # The value of 0xFFFF then firmware will wait for user input before booting.
+ # @Prompt Boot Timeout (s)
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|5
diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
new file mode 100644
index 000000000000..ef01cc217ace
--- /dev/null
+++ b/Platform/Phytium/Durian/DurianPkg.dsc
@@ -0,0 +1,302 @@
+## @file
+# This package provides common open source Phytium Platform modules.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+#
+# SPDX-License-Identifier:BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = DurianPkg
+ PLATFORM_GUID = 8f7ac876-3e7c-11eb-86cb-33f68535d613
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Platform/Phytium/Durian/DurianPkg.fdf
+
+!include Silicon/Phytium/Phytium.dsc.inc
+
+[LibraryClasses.common]
+ # Phytium Platform library
+ ArmPlatformLib|Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf
+
+ TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+
+ # PL011 UART Driver and Dependency Libraries
+ SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+ PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartClockLib.inf
+ PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Durian Platform"
+
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0x303
+
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|4
+ gArmPlatformTokenSpaceGuid.PcdClusterCount|2
+
+ #
+ # NV Storage PCDs.
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xe00000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xe10000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xe20000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
+
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+
+ #
+ # PL011 - Serial Terminal
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x28001000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz|48000000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+
+
+ #
+ # ARM General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x29900000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x29980000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x29c00000
+
+ # System IO space
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase|0x0
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize|0x40000000
+
+ # System Memory (2GB ~ 4GB - 64MB), the top 64MB is reserved for PBF
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x7B000000
+
+ # Stack Size
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
+
+ #
+ # Designware PCI Root Complex
+ #
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|28
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x40000000
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x10000000
+ gArmTokenSpaceGuid.PcdPciBusMin|0
+ gArmTokenSpaceGuid.PcdPciBusMax|255
+ gArmTokenSpaceGuid.PcdPciIoBase|0x00000
+ gArmTokenSpaceGuid.PcdPciIoSize|0xf00000
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0x50000000
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x58000000
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x28000000
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x1000000000
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x1000000000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
+
+ #
+ # SPI Flash Control Register Base Address and Size
+ #
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase|0x0
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x1000000
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x28014000
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x1000
+
+ #
+ # RTC I2C Controller Register Base Address and Speed
+ #
+ gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress|0x2800D000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"V1.0"
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # PCD database
+ #
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ }
+
+ ArmPlatformPkg/PrePi/PeiMPCore.inf {
+ <LibraryClasses>
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+ }
+
+ #
+ #Dxe core entry
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+
+ #DXE driver
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+ }
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+
+ #
+ # Common Arm Timer and Gic Components
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # security system
+ #
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
+ <LibraryClasses>
+ NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
+ }
+
+ #
+ #network, mod for https boot.
+ #
+ NetworkPkg/SnpDxe/SnpDxe.inf
+ NetworkPkg/DpcDxe/DpcDxe.inf
+ NetworkPkg/MnpDxe/MnpDxe.inf
+ NetworkPkg/ArpDxe/ArpDxe.inf
+ NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf
+ NetworkPkg/Ip4Dxe/Ip4Dxe.inf
+ NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf
+ NetworkPkg/Udp4Dxe/Udp4Dxe.inf
+ NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf
+
+ NetworkPkg/Ip6Dxe/Ip6Dxe.inf
+ NetworkPkg/Udp6Dxe/Udp6Dxe.inf
+ NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
+ NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
+ NetworkPkg/TcpDxe/TcpDxe.inf
+
+ NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+ NetworkPkg/DnsDxe/DnsDxe.inf
+ NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
+ NetworkPkg/HttpDxe/HttpDxe.inf
+ #NetworkPkg/HttpBootDxe/HttpBootDxe.inf
+
+ # FV Filesystem
+ MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+
+ #
+ # Common Console Components
+ #
+ # ConIn,ConOut,StdErr
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+
+ #
+ # Hii database init
+ #
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+
+ #
+ # Generic Watchdog Timer
+ #
+ ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+
+ #
+ # Usb Support
+ #
+ MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # IDE/AHCI Support
+ #
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+
+ #
+ # The following 2 module perform the same work except one operate variable.
+ # Only one of both should be put into fdf.
+ #
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+
+ #
+ # NVME Support
+ #
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf
+ MdeModulePkg/Application/UiApp/UiApp.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
+ NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
+ }
+ MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
+
diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Durian/DurianPkg.fdf
new file mode 100644
index 000000000000..f2f4cbc9ac7f
--- /dev/null
+++ b/Platform/Phytium/Durian/DurianPkg.fdf
@@ -0,0 +1,199 @@
+## @file
+# This package provides common open source Phytium Platform modules.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+#
+# SPDX-License-Identifier:BSD-2-Clause-Patent
+#
+##
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.PHYTIUM]
+BaseAddress = 0x88000000|gArmTokenSpaceGuid.PcdFdBaseAddress
+Size = 0x01000000|gArmTokenSpaceGuid.PcdFdSize
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x10000
+NumBlocks = 0x100
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x200000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 16 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ APRIORI DXE {
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ }
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ #INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+
+ # Variable services
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # SATA Controller
+ #
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+ INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+
+ #
+ # NVMe boot devices
+ #
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
+ # NetWork
+ #
+ INF NetworkPkg/SnpDxe/SnpDxe.inf
+ INF NetworkPkg/DpcDxe/DpcDxe.inf
+ INF NetworkPkg/MnpDxe/MnpDxe.inf
+ INF NetworkPkg/ArpDxe/ArpDxe.inf
+ INF NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF NetworkPkg/Ip4Dxe/Ip4Dxe.inf
+ INF NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF NetworkPkg/Udp4Dxe/Udp4Dxe.inf
+ INF NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf
+
+ #
+ # UEFI applications
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+!include Silicon/Phytium/Phytium.fdf.inc
diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf
new file mode 100644
index 000000000000..7ad0f31549ef
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf
@@ -0,0 +1,66 @@
+#/** @file
+# Library for Phytium Platform.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = PhytiumPlatformLib
+ FILE_GUID = fac08f56-40fe-11eb-a2a3-27b46864b1f3
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/Phytium/Phytium.dec
+
+[LibraryClasses]
+ IoLib
+ ArmLib
+ ArmSmcLib
+ MemoryAllocationLib
+ SerialPortLib
+ HobLib
+ BaseMemoryLib
+
+[Sources.common]
+ PhytiumPlatformLib.c
+ PhytiumPlatformLibMem.c
+
+[Sources.AARCH64]
+ AArch64/PhytiumPlatformHelper.S
+
+[Guids]
+ gPhytiumPlatformMemoryInforGuid
+ gPhytiumPlatformCpuInforGuid
+ gPhytiumPlatformPciHostInforGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase
+ gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase
+ gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+ gArmTokenSpaceGuid.PcdPciIoBase
+ gArmTokenSpaceGuid.PcdPciIoSize
+ gArmTokenSpaceGuid.PcdPciIoTranslation
+ gArmTokenSpaceGuid.PcdPciMmio32Base
+ gArmTokenSpaceGuid.PcdPciMmio32Size
+ gArmTokenSpaceGuid.PcdPciMmio32Translation
+ gArmTokenSpaceGuid.PcdPciMmio64Base
+ gArmTokenSpaceGuid.PcdPciMmio64Size
+
+[Pcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
diff --git a/Silicon/Phytium/Include/PhytiumSystemServiceInterface.h b/Silicon/Phytium/Include/PhytiumSystemServiceInterface.h
new file mode 100644
index 000000000000..ddea33dbc275
--- /dev/null
+++ b/Silicon/Phytium/Include/PhytiumSystemServiceInterface.h
@@ -0,0 +1,112 @@
+/** @file
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __OEMSVC_H_
+#define __OEMSVC_H_
+
+/* SMC function IDs for OEM Service queries */
+#define PHYTIUM_OEM_SVC_PSSI_VERSION 0x8200ff03
+#define PHYTIUM_OEM_SVC_PBF_VERSION 0x82000001
+#define PHYTIUM_OEM_SVC_CPU_VERSION 0xc2000002
+#define PHYTIUM_OEM_SVC_CPU_MAPS 0xc2000003
+#define PHYTIUM_OEM_SVC_CPU_CONF 0xc2000004
+#define PHYTIUM_OEM_SVC_MEM_REGIONS 0xc2000005
+#define PHYTIUM_OEM_SVC_MCU_DIMMS 0xc2000006
+#define PHYTIUM_OEM_SVC_PCI_CONTROLLER 0xc2000007
+#define PHYTIUM_OEM_SVC_HOST_BRIDGE 0xc2000008
+#define PHYTIUM_OEM_SVC_GET_FLASH_CMD 0xC200000C
+
+#define PHYTIUM_IOBASE_MASK 0xfffffff
+#define PHYTIUM_MEMIO32_MASK 0xffffffff
+#define PHYTIUM_MEMIO64_MASK 0xffffffffff
+
+#pragma pack(1)
+
+typedef struct {
+ UINT64 CpuMapCount;
+ UINT64 CpuMap[1];
+} PHYTIUM_CPU_MAP_INFOR;
+
+
+typedef struct {
+ UINT64 CpuFreq; // Hz
+ UINT64 CpuL3CacheSize; // Byte
+ UINT64 CpuL3CacheLineSize; // Byte
+} PHYTIUM_CPU_COURE_INFOR;
+
+typedef struct {
+ UINT64 CupVersion; //cpu version
+ PHYTIUM_CPU_COURE_INFOR CpuCoreInfo; //cpu core info
+ PHYTIUM_CPU_MAP_INFOR CpuMapInfo; //cpu map info
+}PHYTIUM_CPU_INFO;
+
+typedef struct {
+ UINT64 MemSize; // MB
+ UINT64 MemDramId;
+ UINT64 MemModuleId;
+ UINT64 MemSerial;
+ UINT64 MemSlotNumber;
+ UINT64 MemFeatures;
+} MCU_DIMM;
+
+#define MCU_DIMM_MAXCOUNT 2
+
+typedef struct {
+ UINT64 MemFreq; // MHz
+ UINT64 MemDimmCount;
+ MCU_DIMM McuDimm[1];
+} MCU_DIMMS;
+
+typedef struct {
+ UINT64 MemStart;
+ UINT64 MemSize;
+ UINT64 MemNodeId;
+} MEMORY_BLOCK;
+
+typedef struct {
+ UINT64 MemBlockCount;
+ MEMORY_BLOCK MemBlock[1];
+} MEMORY_INFOR;
+
+typedef struct {
+ UINT8 PciLane;
+ UINT8 PciSpeed;
+ UINT8 Reserved[6];
+} PCI_BLOCK;
+
+typedef struct {
+ UINT64 PciCount;
+ PCI_BLOCK PciBlock[1];
+} PHYTIUM_PCI_CONTROLLER;
+
+typedef struct {
+ UINT8 BusStart;
+ UINT8 BusEnd;
+ UINT8 Reserved[6];
+ UINT64 PciConfigBase;
+ UINT64 IoBase;
+ UINT64 IoSize;
+ UINT64 Mem32Base;
+ UINT64 Mem32Size;
+ UINT64 Mem64Base;
+ UINT64 Mem64Size;
+ UINT16 IntA;
+ UINT16 IntB;
+ UINT16 IntC;
+ UINT16 IntD;
+} PCI_HOST_BLOCK;
+
+typedef struct {
+ UINT64 PciHostCount;
+ PCI_HOST_BLOCK PciHostBlock[1];
+} PHYTIUM_PCI_HOST_BRIDGE;
+
+#pragma pack ()
+
+
+#endif /* __OEMSVC_H_ */
diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c
new file mode 100644
index 000000000000..2affc9c131b9
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c
@@ -0,0 +1,135 @@
+/** @file
+ Library for Phytium platform.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+ARM_CORE_INFO mPhytiumMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ }
+};
+
+/*
+ This function geted the current Boot Mode.
+
+ This function returns the boot reason on the platform.
+
+ @return Return the current Boot Mode of the platform.
+
+*/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+
+/**
+ Initialize controllers that must setup in the normal world.
+
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ in the PEI phase.
+
+ @retval EFI_SUCCESS ArmPlatformInitialize() is executed successfully.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ return RETURN_SUCCESS;
+}
+
+
+/**
+ This function Inited the system (or sometimes called permanent) memory.
+
+ This memory is generally represented by the DRAM.
+
+ @param[in] None.
+
+ @retval None.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+ VOID
+ )
+{
+ // Nothing to do here
+}
+
+
+/**
+ This function geted the information of core.
+
+ @param[out] CoreCount The count of CoreInfoTable.
+ @param[out] ArmCoreTable The pointer of CoreInfoTable.
+
+ @retval EFI_SUCCESS PrePeiCoreGetMpCoreInfo() is executed successfully.
+
+**/
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = PcdGet32 (PcdCoreCount);
+ *ArmCoreTable = mPhytiumMpCoreInfoTable;
+ return EFI_SUCCESS;
+}
+
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =
+{
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &mArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+
+/**
+ This function geted the information of Ppitable.
+
+ @param[out] PpiListSize The size of Ppitable.
+ @param[out] PpiList The pointer of Ppitable.
+
+ @retval None.
+
+**/
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c
new file mode 100644
index 000000000000..ff70cb28a20a
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c
@@ -0,0 +1,148 @@
+/** @file
+ Library of memory map for Phytium platform.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/ArmSmcLib.h>
+#include <PhytiumSystemServiceInterface.h>
+
+// Number of Virtual Memory Map Descriptors
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 32
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
+ MEMORY_BLOCK *MemBlock = NULL;
+ MEMORY_INFOR *MemInfor = NULL;
+ ARM_SMC_ARGS ArmSmcArgs;
+ UINT32 MemBlockCnt = 0, Index, Index1;
+
+ CacheAttributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ ASSERT (VirtualMemoryMap != NULL);
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ ResourceAttributes =
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+ EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+ MemInfor = AllocatePages(1);
+ ASSERT(MemInfor != NULL);
+
+ ArmSmcArgs.Arg0 = PHYTIUM_OEM_SVC_MEM_REGIONS;
+ ArmSmcArgs.Arg1 = (UINTN)MemInfor;
+ ArmSmcArgs.Arg2 = EFI_PAGE_SIZE;
+ ArmCallSmc (&ArmSmcArgs);
+ if (ArmSmcArgs.Arg0 == 0) {
+ MemBlockCnt = MemInfor->MemBlockCount;
+ MemBlock = MemInfor->MemBlock;
+ } else {
+ ASSERT(FALSE);
+ }
+
+ //Soc Io Space
+ VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemIoBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemIoBase);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemIoSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ //
+ // PCI Configuration Space
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciConfigBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciConfigBase);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciConfigSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ //
+ // PCI Memory Space
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciIoBase) + PcdGet64(PcdPciIoTranslation);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciIoBase) + PcdGet64(PcdPciIoTranslation);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciIoSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ //
+ // PCI Memory Space
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPciMmio32Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPciMmio32Base);
+ VirtualMemoryTable[Index].Length = PcdGet32 (PcdPciMmio32Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ //
+ // 64-bit PCI Memory Space
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciMmio64Base);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciMmio64Base);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciMmio64Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ //DDR
+ for (Index1 = 0; Index1 < MemBlockCnt; Index1++) {
+ VirtualMemoryTable[++Index].PhysicalBase = MemBlock->MemStart;
+ VirtualMemoryTable[Index].VirtualBase = MemBlock->MemStart;
+ VirtualMemoryTable[Index].Length = MemBlock->MemSize;
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ MemBlock->MemStart,
+ MemBlock->MemSize);
+
+ MemBlock ++;
+ }
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ for (Index1 = 0; Index1 < Index; Index1++) {
+ DEBUG((DEBUG_ERROR, "PhysicalBase %12lx VirtualBase %12lx Length %12lx Attributes %12lx\n", VirtualMemoryTable[Index1].PhysicalBase,\
+ VirtualMemoryTable[Index1].VirtualBase, VirtualMemoryTable[Index1].Length, VirtualMemoryTable[Index1].Attributes));
+ }
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/Maintainers.txt b/Maintainers.txt
index 56e16fc48cb4..a23dab394a61 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -310,3 +310,10 @@ F: Silicon/SiFive/
M: Abner Chang <abner.chang@hpe.com>
M: Gilbert Chen <gilbert.chen@hpe.com>
R: Daniel Schaefer <daniel.schaefer@hpe.com>
+
+Phytium platforms and silicon
+F: Platform/Phytium/
+F: Silicon/silicon/
+M: Peng Xie <xiepeng@phytium.com.cn>
+M: Ling Jia <jialing@phytium.com.cn>
+R: Yiqi Shu <shuyiqi@phytium.com.cn>
diff --git a/Silicon/Phytium/Phytium.fdf.inc b/Silicon/Phytium/Phytium.fdf.inc
new file mode 100644
index 000000000000..641266c6012f
--- /dev/null
+++ b/Silicon/Phytium/Phytium.fdf.inc
@@ -0,0 +1,119 @@
+## @file
+# This package provides common open source Phytium silicon modules.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
+#
+# SPDX-License-Identifier:BSD-2-Clause-Patent
+#
+##
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) FIXED {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.BIOSINFO]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW BIN Align = 16 $(INF_OUTPUT)/$(MODULE_NAME).acpi
+ }
+
+[Rule.Common.UEFI_APPLICATION.UI]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="Enter Setup"
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI |.acpi
+ RAW ASL |.aml
+ }
diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S
new file mode 100644
index 000000000000..cce23b786197
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S
@@ -0,0 +1,76 @@
+#
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <AutoGen.h>
+
+.text
+.align 2
+
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+
+PrimaryCoreMpid: .word 0x0
+
+
+ASM_PFX(ArmPlatformPeiBootAction):
+ // Save MPIDR_EL1[23:0] in a variable.
+ mov x20, x30
+ bl ASM_PFX(ArmReadMpidr)
+ lsl w0, w0, #8
+ lsr w0, w0, #8
+ ldr x1, =PrimaryCoreMpid
+ str w0, [x1]
+ ret x20
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
+ ldr x0, =PrimaryCoreMpid
+ ldr w0, [x0]
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_PFX(ArmPlatformIsPrimaryCore):
+ mov x20, x30
+ bl ASM_PFX(ArmReadMpidr)
+ lsl w0, w0, #8
+ lsr w0, w0, #8
+ ldr x1, =PrimaryCoreMpid
+ ldr w1, [x1]
+ cmp w0, w1
+ cset x0, eq
+ ret x20
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_PFX(ArmPlatformGetCorePosition):
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v1 01/10] Silicon/Phytium/: added PhytiumPlatformLib to Phytium2000-4
2021-01-15 8:47 ` [PATCH v1 01/10] Silicon/Phytium/: added PhytiumPlatformLib to Phytium2000-4 Ling Jia
@ 2021-01-22 13:13 ` Leif Lindholm
2021-01-25 8:56 ` 贾玲
0 siblings, 1 reply; 15+ messages in thread
From: Leif Lindholm @ 2021-01-22 13:13 UTC (permalink / raw)
To: Ling Jia; +Cc: devel, Peng Xie, Yiqi Shu
On Fri, Jan 15, 2021 at 08:47:53 +0000, Ling Jia wrote:
> From: Ling <jialing@phytium.com.cn>
>
> The PhytiumPlatformLib supported the system
> library for Phytium2000-4 chip.
> Maintainers.txt: Adds maintainers and reviewers for the DurianPkg.
>
> Cc: Leif Lindholm <leif@nuviainc.com>
> Signed-off-by: Ling Jia <jialing@phytium.com.cn>
> Signed-off-by: Peng Xie <xiepeng@phytium.com.cn>
> Reviewed-by: Yiqi Shu <shuyiqi@phytium.com.cn>
Please include only your own Signed-off-by:.
This indicates the poster confirming the submission's conformance with
the developer certificate of origin. The poster cannot make the same
claim on the behalf of someone else.
Also, please do not include any internal "Reviewed-by:" statements in
the posted patch. Reviewed-by: is added to subsequent submissions
after reviewers have given them in replies to the mailing list. Or by
the maintainer pushing the patches, for the final version.
> ---
> Silicon/Phytium/Phytium.dec | 60 +++
> Silicon/Phytium/Phytium.dsc.inc | 388 ++++++++++++++++++++
> Platform/Phytium/Durian/DurianPkg.dsc | 302 +++++++++++++++
> Platform/Phytium/Durian/DurianPkg.fdf | 199 ++++++++++
> Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf | 66 ++++
> Silicon/Phytium/Include/PhytiumSystemServiceInterface.h | 112 ++++++
> Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c | 135 +++++++
> Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c | 148 ++++++++
> Maintainers.txt | 7 +
> Silicon/Phytium/Phytium.fdf.inc | 119 ++++++
> Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S | 76 ++++
> 11 files changed, 1612 insertions(+)
>
> diff --git a/Silicon/Phytium/Phytium.dec b/Silicon/Phytium/Phytium.dec
> new file mode 100644
> index 000000000000..a064fd60a9c5
> --- /dev/null
> +++ b/Silicon/Phytium/Phytium.dec
> @@ -0,0 +1,60 @@
> +## @file
> +# This package provides common open source Phytium silicon modules.
> +#
> +# Copyright (C) 2020, Phytium Technology Co,Ltd. All rights reserved.
> +#
> +# SPDX-License-Identifier:BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + DEC_SPECIFICATION = 0x00010005
This is correct, but a very old version.
Unless you are building with a *very* old version of BaseTools, it
would make sense to specify a recent version.
These can be found for all tianocore configuration file formats at
https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Documentation
Note that these versions can also be expressed in decimal form.
0x00010005 corresponds to 1.5.
The current .dec format, 1.27, would be written in hexadecimal as
0x0001001b.
Please consider updating this across all config files.
> + PACKAGE_NAME = PhytiumPkg
This is the file I would like to see as
Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec.
If it is renamed, this PACKAGE_NAME should be changed to PhytiumCommonPkg.
> + PACKAGE_GUID = b34af0b4-3e7c-11eb-a9d0-0738806d2dec
> + PACKAGE_VERSION = 0.1
> +
> +################################################################################
> +#
> +# Include Section - list of Include Paths that are provided by this package.
> +# Comments are used for Keywords and Module Types.
> +#
> +# Supported Module Types:
> +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> +#
> +################################################################################
> +[Includes]
> + Include # Root include for the package
> +
> +[Guids.common]
> + gPhytiumPlatformTokenSpaceGuid = { 0x8c3abed4, 0x1fc8, 0x46d3, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xde, 0x76 } }
> + gPhytiumPlatformMemoryInforGuid = { 0xe5d0f31b, 0x18b2, 0x4ec1, { 0xba, 0x20, 0x9c, 0x6d, 0xb7, 0x87, 0x91, 0x79 } }
This does not appear to be used?
It is declared in some .inf files, but never referenced.
> + gPhytiumPlatformCpuInforGuid = { 0x60c3c4b0, 0xe189, 0x4cbb, { 0x88, 0x6a, 0x96, 0x87, 0x21, 0xe0, 0xe0, 0xb0 } }
Same as above.
> + gPhytiumPlatformPciHostInforGuid = { 0x24b99cf4, 0x2e51, 0x440e, { 0x8c, 0x7a, 0xea, 0xa2, 0xe0, 0x29, 0x32, 0xf } }
Same as above.
> + gShellSfHiiGuid = {0x7e57433d, 0x1016, 0x407a, { 0x9d, 0xb8, 0xf9, 0x56, 0x12, 0x19, 0x66, 0x16 } }
This does not appear to be used at all, even in .inf?
> +
> +[PcdsFixedAtBuild.common]
> + #
> + # PCI configuration address space
Not PCI?
> + #
> + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase|0x0|UINT64|0x00000000
> + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize|0x0|UINT64|0x00000001
> +
> + #
> + # PCI configuration address space
> + #
> + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x0|UINT64|0x00000002
> + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x0|UINT64|0x00000003
> +
> + #
> + # SPI Flash Controller Register Base Address and Size
> + #
> + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase|0x0|UINT64|0x00000004
> + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x0|UINT64|0x00000005
> + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x0|UINT64|0x00000006
> + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x0|UINT64|0x00000007
> + gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT32|0x00000008
> + gPhytiumPlatformTokenSpaceGuid.PcdLogoFile |{ 0x99, 0x8b, 0xAA, 0x7B, 0xBB, 0x61, 0xD5, 0x11, 0x9A, 0x5D, 0xBB, 0x90, 0x27, 0x3F, 0xC2, 0x4D }|VOID*|0x40000013
> +
> +[Protocols]
> + gPhytiumSpiMasterProtocolGuid = { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}}
> + gPhytiumFlashProtocolGuid = { 0x00b4af42, 0xfbd0, 0x11ea, { 0x80, 0x3a, 0x27, 0xea, 0x5e, 0x65, 0xe3, 0xf6}}
> diff --git a/Silicon/Phytium/Phytium.dsc.inc b/Silicon/Phytium/Phytium.dsc.inc
> new file mode 100644
> index 000000000000..15b66f6bd55d
> --- /dev/null
> +++ b/Silicon/Phytium/Phytium.dsc.inc
> @@ -0,0 +1,388 @@
> +## @file
> +# This package provides common open source Phytium silicon modules.
> +#
> +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
> +#
> +# SPDX-License-Identifier:BSD-2-Clause-Patent
> +#
> +##
> +
> +
> +[LibraryClasses.common]
> + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> +
> +!if $(TARGET) == RELEASE
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> +!else
> + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> +!endif
> +
> + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
> + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> +
> + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
> + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
> + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
> + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
> +
> + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> + HttpLib|NetworkPkg/Library/DxeHttpLib/DxeHttpLib.inf
> +
> + #
> + # Assume everything is fixed at build
> + #
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + #BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
Could delete commented-out line.
> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> +
> + # ARM Architectural Libraries
> + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
> + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
> + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
> + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
> + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
> + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
> + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
> + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
> + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
> + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
> +
> + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
> +
> + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
> + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
> +
> + #
> + # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
> + # in the debugger will show load and unload commands for symbols. You can cut and paste this
> + # into the command window to load symbols. We should be able to use a script to do this, but
> + # the version of RVD I have does not support scripts accessing system memory.
> + #
> + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
> + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
> + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
> + AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
> + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> +
> + #
> + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
> + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
> + PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
> + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
> + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> +
> + # Scsi Requirements
> + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
> +
> + # USB Requirements
> + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> +
> + # Networking Requirements
> + NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf
> + DpcLib|NetworkPkg/Library/DxeDpcLib/DxeDpcLib.inf
> + UdpIoLib|NetworkPkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
> + IpIoLib|NetworkPkg/Library/DxeIpIoLib/DxeIpIoLib.inf
> +
> + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> + RngLib|MdePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf
> +
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf
> + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
> +
> + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> +
> +[LibraryClasses.common.SEC]
> + DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
> + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
> + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
> + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
> + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
> + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
> + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
> +
> +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM]
> + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
> +
> +[LibraryClasses.common.DXE_CORE]
> + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
> + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
> +
> +[LibraryClasses.common.DXE_DRIVER]
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf
> +
> +[LibraryClasses.common.UEFI_APPLICATION]
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> +
> + # UiApp dependencies
> + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> +
> +[LibraryClasses.common.UEFI_DRIVER]
> + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> +
> +[LibraryClasses.common.DXE_RUNTIME_DRIVER]
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
> +!endif
> +
> +!if $(TARGET) != RELEASE
> + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf
> +!endif
> + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf
> +[LibraryClasses.AARCH64.DXE_RUNTIME_DRIVER]
> + #
> + # PSCI support in EL3 may not be available if we are not running under a PSCI
> + # compliant secure firmware, but since the default VExpress EfiResetSystemLib
> + # cannot be supported at runtime (due to the fact that the syscfg MMIO registers
> + # cannot be runtime remapped), it is our best bet to get ResetSystem functionality
> + # on these platforms.
> + #
The above comment should not be true anymore.
Presumably, you have a working PSCI implementation?
> + EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
> +
> +[LibraryClasses.ARM, LibraryClasses.AARCH64]
> + #
> + # It is not possible to prevent the ARM compiler for generic intrinsic functions.
> + # This library provides the instrinsic functions generate by a given compiler.
> + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
> + #
> + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> +
> + # Add support for GCC stack protector
> + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
> +
> +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> +
> +[BuildOptions]
> + RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
> + GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
> +
> +[BuildOptions.AARCH64.EDKII.DXE_RUNTIME_DRIVER]
> + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +
> +[PcdsFeatureFlag.common]
> + # If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
> + # It could be set FALSE to save size.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
> +
> + # Force the UEFI GIC driver to use GICv2 legacy mode. To use
> + # GICv3 without GICv2 legacy in UEFI, the ARM Trusted Firmware needs
> + # to configure the Non-Secure interrupts in the GIC Redistributors
> + # which is not supported at the moment.
> + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE
> + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|FALSE
> + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
> + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
> +
> + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
> +
> + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
> + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
> +
> + # Indicates if EFI 1.1 ISO 639-2 language supports are obsolete
> + # TRUE - Deprecate global variable LangCodes.
> + # FALSE - Does not deprecate global variable LangCodes.
> + # Deprecate Global Variable LangCodes.
> + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangDeprecate|TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
> +
> +[PcdsFixedAtBuild.common]
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
> + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
> + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
> + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0
> + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
> + gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE
> +
> + # DEBUG_ASSERT_ENABLED 0x01
> + # DEBUG_PRINT_ENABLED 0x02
> + # DEBUG_CODE_ENABLED 0x04
> + # CLEAR_MEMORY_ENABLED 0x08
> + # ASSERT_BREAKPOINT_ENABLED 0x10
> + # ASSERT_DEADLOOP_ENABLED 0x20
> +!if $(TARGET) == RELEASE
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
> +!else
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
> +!endif
> +
> + # DEBUG_INIT 0x00000001 // Initialization
> + # DEBUG_WARN 0x00000002 // Warnings
> + # DEBUG_LOAD 0x00000004 // Load events
> + # DEBUG_FS 0x00000008 // EFI File system
> + # DEBUG_POOL 0x00000010 // Alloc & Free's
> + # DEBUG_PAGE 0x00000020 // Alloc & Free's
> + # DEBUG_INFO 0x00000040 // Verbose
> + # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
> + # DEBUG_VARIABLE 0x00000100 // Variable
> + # DEBUG_BM 0x00000400 // Boot Manager
> + # DEBUG_BLKIO 0x00001000 // BlkIo Driver
> + # DEBUG_NET 0x00004000 // SNI Driver
> + # DEBUG_UNDI 0x00010000 // UNDI Driver
> + # DEBUG_LOADFILE 0x00020000 // UNDI Driver
> + # DEBUG_EVENT 0x00080000 // Event messages
> + # DEBUG_GCD 0x00100000 // Global Coherency Database changes
> + # DEBUG_CACHE 0x00200000 // Memory range cachability changes
> + # DEBUG_ERROR 0x80000000 // Error
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> +
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +
> + #gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
> + #gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
> + #gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
The above threee lines can be deleted (the Pcds no longer exist in edk2).
> + # 20ms
> + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|200000
> +
> + #
> + # Optional feature to help prevent EFI memory map fragments
> + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
> + # Values are in EFI Pages (4K). DXE Core will make sure that
> + # at least this much of each type of memory can be allocated
> + # from a single memory range. This way you only end up with
> + # maximum of two fragements for each type in the memory map
> + # (the memory used, and the free memory that was prereserved
> + # but not used).
> + #
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
> +
> + # RunAxf support via Dynamic Shell Command protocol
> + # We want to use the Shell Libraries but don't want it to initialise
> + # automatically. We initialise the libraries when the command is called by the
> + # Shell.
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot
> + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04
> + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04
> + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04
> +!endif
> +
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
> +!else
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000
> +!endif
> +
> + # Default platform supported RFC 4646 languages: English & French & Chinese Simplified.
> + # Default Value of PlatformLangCodes Variable.
> + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US;zh-Hans"
> +
> + # Default current RFC 4646 language: Chinese Simplified.
> + # Default Value of PlatformLang Variable.
> + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang|"en-US"
> + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
> + #
> + # ACPI Table Version
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
> + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|67
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
> +
> +[PcdsDynamicDefault.common.DEFAULT]
> + ## This PCD defines the video horizontal resolution.
> + # This PCD could be set to 0 then video resolution could be at highest resolution.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|640
> + ## This PCD defines the video vertical resolution.
> + # This PCD could be set to 0 then video resolution could be at highest resolution.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|480
> +
> + ## This PCD defines the Console output row and the default value is 80 according to UEFI spec.
> + # This PCD could be set to 0 then console output could be at max column and max row.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|128
> + ## This PCD defines the Console output column and the default value is 25 according to UEFI spec.
> + # This PCD could be set to 0 then console output could be at max column and max row.
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|40
> +
> + ## Specify the video horizontal resolution of text setup.
> + # @Prompt Video Horizontal Resolution of Text Setup
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
> +
> + ## Specify the video vertical resolution of text setup.
> + # @Prompt Video Vertical Resolution of Text Setup
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
> +
> + ## Specify the console output column of text setup.
> + # @Prompt Console Output Column of Text Setup
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|128
> + ## Specify the console output row of text setup.
> + # @Prompt Console Output Row of Text Setup
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|40
> +
> + ## The number of seconds that the firmware will wait before initiating the original default boot selection.
> + # A value of 0 indicates that the default boot selection is to be initiated immediately on boot.
> + # The value of 0xFFFF then firmware will wait for user input before booting.
> + # @Prompt Boot Timeout (s)
> + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|5
> diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
> new file mode 100644
> index 000000000000..ef01cc217ace
> --- /dev/null
> +++ b/Platform/Phytium/Durian/DurianPkg.dsc
> @@ -0,0 +1,302 @@
> +## @file
> +# This package provides common open source Phytium Platform modules.
> +#
> +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
> +#
> +# SPDX-License-Identifier:BSD-2-Clause-Patent
> +#
> +##
> +
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + PLATFORM_NAME = DurianPkg
> + PLATFORM_GUID = 8f7ac876-3e7c-11eb-86cb-33f68535d613
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x00010005
> + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
> + SUPPORTED_ARCHITECTURES = AARCH64
> + BUILD_TARGETS = DEBUG|RELEASE
Could you also add NOOPT?
> + SKUID_IDENTIFIER = DEFAULT
> + FLASH_DEFINITION = Platform/Phytium/Durian/DurianPkg.fdf
> +
> +!include Silicon/Phytium/Phytium.dsc.inc
> +
> +[LibraryClasses.common]
> + # Phytium Platform library
> + ArmPlatformLib|Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf
> +
> + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
> +
> + # PL011 UART Driver and Dependency Libraries
> + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
> + PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartClockLib.inf
> + PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
> +
> +[LibraryClasses.common.DXE_DRIVER]
> +
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsFixedAtBuild.common]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Durian Platform"
> +
> + gArmTokenSpaceGuid.PcdVFPEnabled|1
> + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0x303
> +
> + gArmPlatformTokenSpaceGuid.PcdCoreCount|4
> + gArmPlatformTokenSpaceGuid.PcdClusterCount|2
> +
> + #
> + # NV Storage PCDs.
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xe00000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xe10000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xe20000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
> +
> + # Size of the region used by UEFI in permanent memory (Reserved 64MB)
> + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
> +
> + #
> + # PL011 - Serial Terminal
> + #
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x28001000
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
> + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|48000000
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
> +
> +
> + #
> + # ARM General Interrupt Controller
> + #
> + gArmTokenSpaceGuid.PcdGicDistributorBase|0x29900000
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x29980000
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x29c00000
> +
> + # System IO space
> + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase|0x0
> + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize|0x40000000
> +
> + # System Memory (2GB ~ 4GB - 64MB), the top 64MB is reserved for PBF
What is PBF? The EL3 firmware? Please clarify in comment.
> + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7B000000
> +
> + # Stack Size
> + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
> +
> + #
> + # Designware PCI Root Complex
> + #
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000
> + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|28
> + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x40000000
> + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x10000000
> + gArmTokenSpaceGuid.PcdPciBusMin|0
> + gArmTokenSpaceGuid.PcdPciBusMax|255
> + gArmTokenSpaceGuid.PcdPciIoBase|0x00000
> + gArmTokenSpaceGuid.PcdPciIoSize|0xf00000
> + gArmTokenSpaceGuid.PcdPciIoTranslation|0x50000000
> + gArmTokenSpaceGuid.PcdPciMmio32Base|0x58000000
> + gArmTokenSpaceGuid.PcdPciMmio32Size|0x28000000
> + gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
> + gArmTokenSpaceGuid.PcdPciMmio64Base|0x1000000000
> + gArmTokenSpaceGuid.PcdPciMmio64Size|0x1000000000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
> +
> + #
> + # SPI Flash Control Register Base Address and Size
> + #
> + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase|0x0
> + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x1000000
> + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x28014000
> + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x1000
> +
> + #
> + # RTC I2C Controller Register Base Address and Speed
> + #
> + gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress|0x2800D000
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"V1.0"
Could make sense to move the firmware version string next to the
firmware vendor one.
> +
> +################################################################################
> +#
> +# Components Section - list of all EDK II Modules needed by this Platform
> +#
> +################################################################################
> +[Components.common]
> + #
> + # PCD database
> + #
> + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
> + ShellPkg/Application/Shell/Shell.inf {
> + <LibraryClasses>
> + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
> + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
> + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
> + }
> +
> + ArmPlatformPkg/PrePi/PeiMPCore.inf {
> + <LibraryClasses>
> + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
> + }
> +
> + #
> + #Dxe core entry
> + #
> + MdeModulePkg/Core/Dxe/DxeMain.inf {
> + <LibraryClasses>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
> + }
> +
> + #DXE driver
> + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> + }
> + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
> +
> + #
> + # Common Arm Timer and Gic Components
> + #
> + ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> + ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> +
> + #
> + # security system
> + #
> + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
> + <LibraryClasses>
> + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
> + }
> +
> + #
> + #network, mod for https boot.
> + #
> + NetworkPkg/SnpDxe/SnpDxe.inf
> + NetworkPkg/DpcDxe/DpcDxe.inf
> + NetworkPkg/MnpDxe/MnpDxe.inf
> + NetworkPkg/ArpDxe/ArpDxe.inf
> + NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf
> + NetworkPkg/Ip4Dxe/Ip4Dxe.inf
> + NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf
> + NetworkPkg/Udp4Dxe/Udp4Dxe.inf
> + NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf
> +
> + NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> + NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> + NetworkPkg/TcpDxe/TcpDxe.inf
> +
> + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> +
> + NetworkPkg/DnsDxe/DnsDxe.inf
> + NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
> + NetworkPkg/HttpDxe/HttpDxe.inf
> + #NetworkPkg/HttpBootDxe/HttpBootDxe.inf
> +
> + # FV Filesystem
> + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
> +
> + #
> + # Common Console Components
> + #
> + # ConIn,ConOut,StdErr
> + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
> +
> + #
> + # Hii database init
> + #
> + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> + FatPkg/EnhancedFatDxe/Fat.inf
> +
> + #
> + # Generic Watchdog Timer
> + #
> + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
> +
> + #
> + # Usb Support
> + #
> + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
> + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> +
> + #
> + # IDE/AHCI Support
> + #
> + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +
> + #
> + # The following 2 module perform the same work except one operate variable.
> + # Only one of both should be put into fdf.
> + #
> + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> +
> + #
> + # NVME Support
> + #
> + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +
> + #
> + # Bds
> + #
> + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf
> + MdeModulePkg/Application/UiApp/UiApp.inf {
> + <LibraryClasses>
> + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
> + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
> + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
> + }
> + MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
> +
> diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Durian/DurianPkg.fdf
> new file mode 100644
> index 000000000000..f2f4cbc9ac7f
> --- /dev/null
> +++ b/Platform/Phytium/Durian/DurianPkg.fdf
> @@ -0,0 +1,199 @@
> +## @file
> +# This package provides common open source Phytium Platform modules.
> +#
> +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
> +#
> +# SPDX-License-Identifier:BSD-2-Clause-Patent
> +#
> +##
> +
> +################################################################################
> +#
> +# FD Section
> +# The [FD] Section is made up of the definition statements and a
> +# description of what goes into the Flash Device Image. Each FD section
> +# defines one flash "device" image. A flash device image may be one of
> +# the following: Removable media bootable image (like a boot floppy
> +# image,) an Option ROM image (that would be "flashed" into an add-in
> +# card,) a System "Flash" image (that would be burned into a system's
> +# flash) or an Update ("Capsule") image that will be used to update and
> +# existing system flash.
> +#
> +################################################################################
> +
> +[FD.PHYTIUM]
> +BaseAddress = 0x88000000|gArmTokenSpaceGuid.PcdFdBaseAddress
> +Size = 0x01000000|gArmTokenSpaceGuid.PcdFdSize
> +ErasePolarity = 1
> +
> +# This one is tricky, it must be: BlockSize * NumBlocks = Size
> +BlockSize = 0x10000
> +NumBlocks = 0x100
> +
> +################################################################################
> +#
> +# Following are lists of FD Region layout which correspond to the locations of different
> +# images within the flash device.
> +#
> +# Regions must be defined in ascending order and may not overlap.
> +#
> +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> +# "0x" characters. Like:
> +# Offset|Size
> +# PcdOffsetCName|PcdSizeCName
> +# RegionType <FV, DATA, or FILE>
> +#
> +################################################################################
> +
> +0x00000000|0x200000
> +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> +FV = FVMAIN_COMPACT
> +
> +################################################################################
> +#
> +# FV Section
> +#
> +# [FV] section is used to define what components or modules are placed within a flash
> +# device file. This section also defines order the components and modules are positioned
> +# within the image. The [FV] section consists of define statements, set statements and
> +# module statements.
> +#
> +################################################################################
> +
> +[FV.FvMain]
> +BlockSize = 0x40
> +NumBlocks = 0 # This FV gets compressed so make it just big enough
> +FvAlignment = 16 # FV alignment and FV attributes setting.
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + APRIORI DXE {
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> + }
> +
> + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +
> + #
> + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> + #
> + #INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
> + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> +
> + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> +
> + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
> +
> + # Variable services
> + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> +
> + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> +
> + #
> + # Multiple Console IO support
> + #
> + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> +
> + #
> + # FAT filesystem + GPT/MBR partitioning
> + #
> + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> + INF FatPkg/EnhancedFatDxe/Fat.inf
> + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> +
> + #
> + # SATA Controller
> + #
> + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +
> + #
> + # NVMe boot devices
> + #
> + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +
> + #
> + # NetWork
> + #
> + INF NetworkPkg/SnpDxe/SnpDxe.inf
> + INF NetworkPkg/DpcDxe/DpcDxe.inf
> + INF NetworkPkg/MnpDxe/MnpDxe.inf
> + INF NetworkPkg/ArpDxe/ArpDxe.inf
> + INF NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf
> + INF NetworkPkg/Ip4Dxe/Ip4Dxe.inf
> + INF NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf
> + INF NetworkPkg/Udp4Dxe/Udp4Dxe.inf
> + INF NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf
> +
> + #
> + # UEFI applications
> + #
> + INF ShellPkg/Application/Shell/Shell.inf
> +
> + #
> + # Bds
> + #
> + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> + INF MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf
> + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> + INF MdeModulePkg/Application/UiApp/UiApp.inf
> +
> +[FV.FVMAIN_COMPACT]
> +FvAlignment = 16
> +ERASE_POLARITY = 1
> +MEMORY_MAPPED = TRUE
> +STICKY_WRITE = TRUE
> +LOCK_CAP = TRUE
> +LOCK_STATUS = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP = TRUE
> +WRITE_STATUS = TRUE
> +WRITE_LOCK_CAP = TRUE
> +WRITE_LOCK_STATUS = TRUE
> +READ_DISABLED_CAP = TRUE
> +READ_ENABLED_CAP = TRUE
> +READ_STATUS = TRUE
> +READ_LOCK_CAP = TRUE
> +READ_LOCK_STATUS = TRUE
> +
> + INF ArmPlatformPkg/PrePi/PeiMPCore.inf
> +
> + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> + SECTION FV_IMAGE = FVMAIN
> + }
> + }
> +
> +!include Silicon/Phytium/Phytium.fdf.inc
> diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf
> new file mode 100644
> index 000000000000..7ad0f31549ef
> --- /dev/null
> +++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf
> @@ -0,0 +1,66 @@
> +#/** @file
> +# Library for Phytium Platform.
> +#
> +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x00010019
> + BASE_NAME = PhytiumPlatformLib
> + FILE_GUID = fac08f56-40fe-11eb-a2a3-27b46864b1f3
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + Silicon/Phytium/Phytium.dec
Can you please sort paths alphabetically - throughout all of the .inf
files in all the patches?
> +
> +[LibraryClasses]
> + IoLib
> + ArmLib
> + ArmSmcLib
> + MemoryAllocationLib
> + SerialPortLib
> + HobLib
> + BaseMemoryLib
And again for all the libraryclasses, sources, guids, fixedpcd, pcd...?
It makes it much quicker to read through the list.
> +
> +[Sources.common]
> + PhytiumPlatformLib.c
> + PhytiumPlatformLibMem.c
> +
> +[Sources.AARCH64]
> + AArch64/PhytiumPlatformHelper.S
> +
> +[Guids]
> + gPhytiumPlatformMemoryInforGuid
> + gPhytiumPlatformCpuInforGuid
> + gPhytiumPlatformPciHostInforGuid
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdSystemMemoryBase
> + gArmTokenSpaceGuid.PcdSystemMemorySize
> + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase
> + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize
> + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase
> + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize
> + gArmTokenSpaceGuid.PcdPciBusMin
> + gArmTokenSpaceGuid.PcdPciBusMax
> + gArmTokenSpaceGuid.PcdPciIoBase
> + gArmTokenSpaceGuid.PcdPciIoSize
> + gArmTokenSpaceGuid.PcdPciIoTranslation
> + gArmTokenSpaceGuid.PcdPciMmio32Base
> + gArmTokenSpaceGuid.PcdPciMmio32Size
> + gArmTokenSpaceGuid.PcdPciMmio32Translation
> + gArmTokenSpaceGuid.PcdPciMmio64Base
> + gArmTokenSpaceGuid.PcdPciMmio64Size
> +
> +[Pcd]
> + gArmPlatformTokenSpaceGuid.PcdCoreCount
> diff --git a/Silicon/Phytium/Include/PhytiumSystemServiceInterface.h b/Silicon/Phytium/Include/PhytiumSystemServiceInterface.h
> new file mode 100644
> index 000000000000..ddea33dbc275
> --- /dev/null
> +++ b/Silicon/Phytium/Include/PhytiumSystemServiceInterface.h
> @@ -0,0 +1,112 @@
> +/** @file
> +
> + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __OEMSVC_H_
> +#define __OEMSVC_H_
Please don't use leading __ (or _) in macro names - they are reserved
for toolchain use.
> +
> +/* SMC function IDs for OEM Service queries */
> +#define PHYTIUM_OEM_SVC_PSSI_VERSION 0x8200ff03
> +#define PHYTIUM_OEM_SVC_PBF_VERSION 0x82000001
> +#define PHYTIUM_OEM_SVC_CPU_VERSION 0xc2000002
> +#define PHYTIUM_OEM_SVC_CPU_MAPS 0xc2000003
> +#define PHYTIUM_OEM_SVC_CPU_CONF 0xc2000004
> +#define PHYTIUM_OEM_SVC_MEM_REGIONS 0xc2000005
> +#define PHYTIUM_OEM_SVC_MCU_DIMMS 0xc2000006
> +#define PHYTIUM_OEM_SVC_PCI_CONTROLLER 0xc2000007
> +#define PHYTIUM_OEM_SVC_HOST_BRIDGE 0xc2000008
> +#define PHYTIUM_OEM_SVC_GET_FLASH_CMD 0xC200000C
> +
> +#define PHYTIUM_IOBASE_MASK 0xfffffff
> +#define PHYTIUM_MEMIO32_MASK 0xffffffff
> +#define PHYTIUM_MEMIO64_MASK 0xffffffffff
> +
> +#pragma pack(1)
> +
> +typedef struct {
> + UINT64 CpuMapCount;
> + UINT64 CpuMap[1];
> +} PHYTIUM_CPU_MAP_INFOR;
I see this abbreviation of "information" to "infor" in many places.
Could this be shortened to "info", which is a more common
abbreviation? In all locations.
> +
> +
> +typedef struct {
> + UINT64 CpuFreq; // Hz
> + UINT64 CpuL3CacheSize; // Byte
> + UINT64 CpuL3CacheLineSize; // Byte
> +} PHYTIUM_CPU_COURE_INFOR;
> +
> +typedef struct {
> + UINT64 CupVersion; //cpu version
> + PHYTIUM_CPU_COURE_INFOR CpuCoreInfo; //cpu core info
> + PHYTIUM_CPU_MAP_INFOR CpuMapInfo; //cpu map info
> +}PHYTIUM_CPU_INFO;
> +
> +typedef struct {
> + UINT64 MemSize; // MB
> + UINT64 MemDramId;
> + UINT64 MemModuleId;
> + UINT64 MemSerial;
> + UINT64 MemSlotNumber;
> + UINT64 MemFeatures;
> +} MCU_DIMM;
Could all of these struct names have PHYTIUM_ prefix?
Some of them are very generic, and could potentially clash with common
code in future.
> +
> +#define MCU_DIMM_MAXCOUNT 2
> +
> +typedef struct {
> + UINT64 MemFreq; // MHz
> + UINT64 MemDimmCount;
> + MCU_DIMM McuDimm[1];
> +} MCU_DIMMS;
> +
> +typedef struct {
> + UINT64 MemStart;
> + UINT64 MemSize;
> + UINT64 MemNodeId;
> +} MEMORY_BLOCK;
> +
> +typedef struct {
> + UINT64 MemBlockCount;
> + MEMORY_BLOCK MemBlock[1];
> +} MEMORY_INFOR;
> +
> +typedef struct {
> + UINT8 PciLane;
> + UINT8 PciSpeed;
> + UINT8 Reserved[6];
> +} PCI_BLOCK;
> +
> +typedef struct {
> + UINT64 PciCount;
> + PCI_BLOCK PciBlock[1];
> +} PHYTIUM_PCI_CONTROLLER;
> +
> +typedef struct {
> + UINT8 BusStart;
> + UINT8 BusEnd;
> + UINT8 Reserved[6];
> + UINT64 PciConfigBase;
> + UINT64 IoBase;
> + UINT64 IoSize;
> + UINT64 Mem32Base;
> + UINT64 Mem32Size;
> + UINT64 Mem64Base;
> + UINT64 Mem64Size;
> + UINT16 IntA;
> + UINT16 IntB;
> + UINT16 IntC;
> + UINT16 IntD;
> +} PCI_HOST_BLOCK;
> +
> +typedef struct {
> + UINT64 PciHostCount;
> + PCI_HOST_BLOCK PciHostBlock[1];
> +} PHYTIUM_PCI_HOST_BRIDGE;
> +
> +#pragma pack ()
> +
> +
> +#endif /* __OEMSVC_H_ */
> diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c
> new file mode 100644
> index 000000000000..2affc9c131b9
> --- /dev/null
> +++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c
> @@ -0,0 +1,135 @@
> +/** @file
> + Library for Phytium platform.
> +
> + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Library/IoLib.h>
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
Can we sort include statements alphabetically as well?
In this case, Library/IoLib.h after Library/DebugLib.h?
> +
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +ARM_CORE_INFO mPhytiumMpCoreInfoTable[] = {
> + {
> + // Cluster 0, Core 0
> + 0x0, 0x0,
> +
> + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (UINT64)0xFFFFFFFF
> + }
> +};
> +
> +/*
> + This function geted the current Boot Mode.
> +
> + This function returns the boot reason on the platform.
> +
> + @return Return the current Boot Mode of the platform.
> +
> +*/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +
> +/**
> + Initialize controllers that must setup in the normal world.
> +
> + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
> + in the PEI phase.
> +
> + @retval EFI_SUCCESS ArmPlatformInitialize() is executed successfully.
> +
> +**/
> +RETURN_STATUS
> +ArmPlatformInitialize (
> + IN UINTN MpId
> + )
> +{
> + return RETURN_SUCCESS;
> +}
> +
> +
> +/**
> + This function Inited the system (or sometimes called permanent) memory.
> +
> + This memory is generally represented by the DRAM.
> +
> + @param[in] None.
> +
> + @retval None.
> +
> +**/
> +VOID
> +ArmPlatformInitializeSystemMemory (
> + VOID
> + )
> +{
> + // Nothing to do here
> +}
> +
> +
> +/**
> + This function geted the information of core.
> +
> + @param[out] CoreCount The count of CoreInfoTable.
> + @param[out] ArmCoreTable The pointer of CoreInfoTable.
> +
> + @retval EFI_SUCCESS PrePeiCoreGetMpCoreInfo() is executed successfully.
> +
> +**/
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> + OUT UINTN *CoreCount,
> + OUT ARM_CORE_INFO **ArmCoreTable
> + )
> +{
> + *CoreCount = PcdGet32 (PcdCoreCount);
> + *ArmCoreTable = mPhytiumMpCoreInfoTable;
> + return EFI_SUCCESS;
> +}
> +
> +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
> +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
> +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +
> +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =
> +{
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &mArmMpCoreInfoPpiGuid,
> + &mMpCoreInfoPpi
> + }
> +};
> +
> +
> +/**
> + This function geted the information of Ppitable.
> +
> + @param[out] PpiListSize The size of Ppitable.
> + @param[out] PpiList The pointer of Ppitable.
> +
> + @retval None.
> +
> +**/
> +VOID
> +ArmPlatformGetPlatformPpiList (
> + OUT UINTN *PpiListSize,
> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> + )
> +{
> + *PpiListSize = sizeof(gPlatformPpiTable);
> + *PpiList = gPlatformPpiTable;
> +}
> diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c
> new file mode 100644
> index 000000000000..ff70cb28a20a
> --- /dev/null
> +++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c
> @@ -0,0 +1,148 @@
> +/** @file
> + Library of memory map for Phytium platform.
> +
> + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/ArmSmcLib.h>
Sort alphabetically?
> +#include <PhytiumSystemServiceInterface.h>
> +
> +// Number of Virtual Memory Map Descriptors
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 32
> +
> +// DDR attributes
> +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
> +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
> +
> +/**
> + Return the Virtual Memory Map of your platform
> +
> + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
> +
> + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> + Virtual Memory mapping. This array must be ended by a zero-filled
> + entry
> +**/
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
> + )
> +{
> + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
> + MEMORY_BLOCK *MemBlock = NULL;
> + MEMORY_INFOR *MemInfor = NULL;
Coding style says no to initialize variables on defintion.
You can set these to NULL if SMC call fails.
> + ARM_SMC_ARGS ArmSmcArgs;
> + UINT32 MemBlockCnt = 0, Index, Index1;
Coding style also says only one variable defined per line.
And having Index and Index1 becomes tricky to read. Just call the
second one J.
> +
> + CacheAttributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + ASSERT (VirtualMemoryMap != NULL);
> + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> + if (VirtualMemoryTable == NULL) {
> + return;
> + }
> +
> + ResourceAttributes =
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> + EFI_RESOURCE_ATTRIBUTE_TESTED;
> +
> + MemInfor = AllocatePages(1);
> + ASSERT(MemInfor != NULL);
Space before (
> +
> + ArmSmcArgs.Arg0 = PHYTIUM_OEM_SVC_MEM_REGIONS;
> + ArmSmcArgs.Arg1 = (UINTN)MemInfor;
> + ArmSmcArgs.Arg2 = EFI_PAGE_SIZE;
> + ArmCallSmc (&ArmSmcArgs);
> + if (ArmSmcArgs.Arg0 == 0) {
> + MemBlockCnt = MemInfor->MemBlockCount;
> + MemBlock = MemInfor->MemBlock;
> + } else {
> + ASSERT(FALSE);
Space before (
> + }
Actually, this SMC call should be broken out into a separate helper
function.
> +
> + //Soc Io Space
> + VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemIoBase);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemIoBase);
> + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemIoSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + //
> + // PCI Configuration Space
> + //
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciConfigBase);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciConfigBase);
> + VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciConfigSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + //
> + // PCI Memory Space
> + //
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciIoBase) + PcdGet64(PcdPciIoTranslation);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciIoBase) + PcdGet64(PcdPciIoTranslation);
> + VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciIoSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + //
> + // PCI Memory Space
> + //
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPciMmio32Base);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPciMmio32Base);
> + VirtualMemoryTable[Index].Length = PcdGet32 (PcdPciMmio32Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + //
> + // 64-bit PCI Memory Space
> + //
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciMmio64Base);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciMmio64Base);
> + VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciMmio64Size);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + //DDR
> + for (Index1 = 0; Index1 < MemBlockCnt; Index1++) {
> + VirtualMemoryTable[++Index].PhysicalBase = MemBlock->MemStart;
> + VirtualMemoryTable[Index].VirtualBase = MemBlock->MemStart;
> + VirtualMemoryTable[Index].Length = MemBlock->MemSize;
> + VirtualMemoryTable[Index].Attributes = CacheAttributes;
> +
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_SYSTEM_MEMORY,
> + ResourceAttributes,
> + MemBlock->MemStart,
> + MemBlock->MemSize);
> +
> + MemBlock ++;
No space before ++.
> + }
> +
> + // End of Table
> + VirtualMemoryTable[++Index].PhysicalBase = 0;
> + VirtualMemoryTable[Index].VirtualBase = 0;
> + VirtualMemoryTable[Index].Length = 0;
> + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
> +
> + ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> + for (Index1 = 0; Index1 < Index; Index1++) {
> + DEBUG((DEBUG_ERROR, "PhysicalBase %12lx VirtualBase %12lx Length %12lx Attributes %12lx\n", VirtualMemoryTable[Index1].PhysicalBase,\
Please break long line after ",
> + VirtualMemoryTable[Index1].VirtualBase, VirtualMemoryTable[Index1].Length, VirtualMemoryTable[Index1].Attributes));
Please break long line.
> + }
Actually, this loop should also be a static helper function.
> +
> + *VirtualMemoryMap = VirtualMemoryTable;
> +}
> diff --git a/Maintainers.txt b/Maintainers.txt
> index 56e16fc48cb4..a23dab394a61 100644
> --- a/Maintainers.txt
> +++ b/Maintainers.txt
> @@ -310,3 +310,10 @@ F: Silicon/SiFive/
> M: Abner Chang <abner.chang@hpe.com>
> M: Gilbert Chen <gilbert.chen@hpe.com>
> R: Daniel Schaefer <daniel.schaefer@hpe.com>
> +
> +Phytium platforms and silicon
> +F: Platform/Phytium/
> +F: Silicon/silicon/
> +M: Peng Xie <xiepeng@phytium.com.cn>
> +M: Ling Jia <jialing@phytium.com.cn>
Can you change these to R: for now?
We use M to indicate who has responsibility for actually getting the
patches into the repo. So could you add me as M for now?
/
Leif
> +R: Yiqi Shu <shuyiqi@phytium.com.cn>
> diff --git a/Silicon/Phytium/Phytium.fdf.inc b/Silicon/Phytium/Phytium.fdf.inc
> new file mode 100644
> index 000000000000..641266c6012f
> --- /dev/null
> +++ b/Silicon/Phytium/Phytium.fdf.inc
> @@ -0,0 +1,119 @@
> +## @file
> +# This package provides common open source Phytium silicon modules.
> +#
> +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
> +#
> +# SPDX-License-Identifier:BSD-2-Clause-Patent
> +#
> +##
> +
> +############################################################################
> +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
> +############################################################################
> +#
> +#[Rule.Common.DXE_DRIVER]
> +# FILE DRIVER = $(NAMED_GUID) {
> +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> +# COMPRESS PI_STD {
> +# GUIDED {
> +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> +# UI STRING="$(MODULE_NAME)" Optional
> +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> +# }
> +# }
> +# }
> +#
> +############################################################################
> +
> +[Rule.Common.SEC]
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
> + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> + }
> +
> +[Rule.Common.PEI_CORE]
> + FILE PEI_CORE = $(NAMED_GUID) FIXED {
> + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING ="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.PEIM]
> + FILE PEIM = $(NAMED_GUID) FIXED {
> + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.PEIM.TIANOCOMPRESSED]
> + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
> + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> + }
> +
> +[Rule.Common.DXE_CORE]
> + FILE DXE_CORE = $(NAMED_GUID) {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.UEFI_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.DXE_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.DXE_RUNTIME_DRIVER]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="$(MODULE_NAME)" Optional
> + }
> +
> +[Rule.Common.UEFI_APPLICATION]
> + FILE APPLICATION = $(NAMED_GUID) {
> + UI STRING ="$(MODULE_NAME)" Optional
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + }
> +
> +[Rule.Common.UEFI_DRIVER.BINARY]
> + FILE DRIVER = $(NAMED_GUID) {
> + DXE_DEPEX DXE_DEPEX Optional |.depex
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.UEFI_APPLICATION.BINARY]
> + FILE APPLICATION = $(NAMED_GUID) {
> + PE32 PE32 |.efi
> + UI STRING="$(MODULE_NAME)" Optional
> + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.USER_DEFINED.BIOSINFO]
> + FILE FREEFORM = $(NAMED_GUID) {
> + RAW BIN Align = 16 $(INF_OUTPUT)/$(MODULE_NAME).acpi
> + }
> +
> +[Rule.Common.UEFI_APPLICATION.UI]
> + FILE APPLICATION = $(NAMED_GUID) {
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + UI STRING="Enter Setup"
> + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> + }
> +
> +[Rule.Common.USER_DEFINED.ACPITABLE]
> + FILE FREEFORM = $(NAMED_GUID) {
> + RAW ACPI |.acpi
> + RAW ASL |.aml
> + }
> diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S
> new file mode 100644
> index 000000000000..cce23b786197
> --- /dev/null
> +++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S
> @@ -0,0 +1,76 @@
> +#
> +# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Base.h>
> +#include <Library/ArmLib.h>
> +#include <Library/PcdLib.h>
> +#include <AutoGen.h>
> +
> +.text
> +.align 2
> +
> +GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
> +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
> +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
> +GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
> +
> +PrimaryCoreMpid: .word 0x0
> +
> +
> +ASM_PFX(ArmPlatformPeiBootAction):
> + // Save MPIDR_EL1[23:0] in a variable.
> + mov x20, x30
> + bl ASM_PFX(ArmReadMpidr)
> + lsl w0, w0, #8
> + lsr w0, w0, #8
> + ldr x1, =PrimaryCoreMpid
> + str w0, [x1]
> + ret x20
> +
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +// VOID
> +// );
> +ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
> + ldr x0, =PrimaryCoreMpid
> + ldr w0, [x0]
> + ret
> +
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +// IN UINTN MpId
> +// );
> +ASM_PFX(ArmPlatformIsPrimaryCore):
> + mov x20, x30
> + bl ASM_PFX(ArmReadMpidr)
> + lsl w0, w0, #8
> + lsr w0, w0, #8
> + ldr x1, =PrimaryCoreMpid
> + ldr w1, [x1]
> + cmp w0, w1
> + cset x0, eq
> + ret x20
> +
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +// IN UINTN MpId
> +// );
> +// With this function: CorePos = (ClusterId * 4) + CoreId
> +ASM_PFX(ArmPlatformGetCorePosition):
> + and x1, x0, #ARM_CORE_MASK
> + and x0, x0, #ARM_CLUSTER_MASK
> + add x0, x1, x0, LSR #6
> + ret
> +
> +ASM_FUNCTION_REMOVE_IF_UNREFERENCED
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v1 01/10] Silicon/Phytium/: added PhytiumPlatformLib to Phytium2000-4
2021-01-22 13:13 ` Leif Lindholm
@ 2021-01-25 8:56 ` 贾玲
0 siblings, 0 replies; 15+ messages in thread
From: 贾玲 @ 2021-01-25 8:56 UTC (permalink / raw)
To: Leif Lindholm; +Cc: devel, Peng Xie, Yiqi Shu
Hi Leif,
Thank you for your reply. We are very happy about it!
Your suggestions are very detailed. We see that there are a lot of problems, and then we don't quite understand some of them. We'll send an email for details later. Thank you very much!
Best Regards,
Ling
> -----原始邮件-----
> 发件人: "Leif Lindholm" <leif@nuviainc.com>
> 发送时间: 2021-01-22 21:13:53 (星期五)
> 收件人: "Ling Jia" <jialing@phytium.com.cn>
> 抄送: devel@edk2.groups.io, "Peng Xie" <xiepeng@phytium.com.cn>, "Yiqi Shu" <shuyiqi@phytium.com.cn>
> 主题: Re: [PATCH v1 01/10] Silicon/Phytium/: added PhytiumPlatformLib to Phytium2000-4
>
> On Fri, Jan 15, 2021 at 08:47:53 +0000, Ling Jia wrote:
> > From: Ling <jialing@phytium.com.cn>
> >
> > The PhytiumPlatformLib supported the system
> > library for Phytium2000-4 chip.
> > Maintainers.txt: Adds maintainers and reviewers for the DurianPkg.
> >
> > Cc: Leif Lindholm <leif@nuviainc.com>
> > Signed-off-by: Ling Jia <jialing@phytium.com.cn>
> > Signed-off-by: Peng Xie <xiepeng@phytium.com.cn>
> > Reviewed-by: Yiqi Shu <shuyiqi@phytium.com.cn>
>
> Please include only your own Signed-off-by:.
> This indicates the poster confirming the submission's conformance with
> the developer certificate of origin. The poster cannot make the same
> claim on the behalf of someone else.
>
> Also, please do not include any internal "Reviewed-by:" statements in
> the posted patch. Reviewed-by: is added to subsequent submissions
> after reviewers have given them in replies to the mailing list. Or by
> the maintainer pushing the patches, for the final version.
>
> > ---
> > Silicon/Phytium/Phytium.dec | 60 +++
> > Silicon/Phytium/Phytium.dsc.inc | 388 ++++++++++++++++++++
> > Platform/Phytium/Durian/DurianPkg.dsc | 302 +++++++++++++++
> > Platform/Phytium/Durian/DurianPkg.fdf | 199 ++++++++++
> > Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf | 66 ++++
> > Silicon/Phytium/Include/PhytiumSystemServiceInterface.h | 112 ++++++
> > Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c | 135 +++++++
> > Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c | 148 ++++++++
> > Maintainers.txt | 7 +
> > Silicon/Phytium/Phytium.fdf.inc | 119 ++++++
> > Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S | 76 ++++
> > 11 files changed, 1612 insertions(+)
> >
> > diff --git a/Silicon/Phytium/Phytium.dec b/Silicon/Phytium/Phytium.dec
> > new file mode 100644
> > index 000000000000..a064fd60a9c5
> > --- /dev/null
> > +++ b/Silicon/Phytium/Phytium.dec
> > @@ -0,0 +1,60 @@
> > +## @file
> > +# This package provides common open source Phytium silicon modules.
> > +#
> > +# Copyright (C) 2020, Phytium Technology Co,Ltd. All rights reserved.
> > +#
> > +# SPDX-License-Identifier:BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +[Defines]
> > + DEC_SPECIFICATION = 0x00010005
>
> This is correct, but a very old version.
> Unless you are building with a *very* old version of BaseTools, it
> would make sense to specify a recent version.
>
> These can be found for all tianocore configuration file formats at
> https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Documentation
>
> Note that these versions can also be expressed in decimal form.
> 0x00010005 corresponds to 1.5.
> The current .dec format, 1.27, would be written in hexadecimal as
> 0x0001001b.
>
> Please consider updating this across all config files.
>
> > + PACKAGE_NAME = PhytiumPkg
>
> This is the file I would like to see as
> Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec.
> If it is renamed, this PACKAGE_NAME should be changed to PhytiumCommonPkg.
>
> > + PACKAGE_GUID = b34af0b4-3e7c-11eb-a9d0-0738806d2dec
> > + PACKAGE_VERSION = 0.1
> > +
> > +################################################################################
> > +#
> > +# Include Section - list of Include Paths that are provided by this package.
> > +# Comments are used for Keywords and Module Types.
> > +#
> > +# Supported Module Types:
> > +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
> > +#
> > +################################################################################
> > +[Includes]
> > + Include # Root include for the package
> > +
> > +[Guids.common]
> > + gPhytiumPlatformTokenSpaceGuid = { 0x8c3abed4, 0x1fc8, 0x46d3, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xde, 0x76 } }
> > + gPhytiumPlatformMemoryInforGuid = { 0xe5d0f31b, 0x18b2, 0x4ec1, { 0xba, 0x20, 0x9c, 0x6d, 0xb7, 0x87, 0x91, 0x79 } }
>
> This does not appear to be used?
> It is declared in some .inf files, but never referenced.
>
> > + gPhytiumPlatformCpuInforGuid = { 0x60c3c4b0, 0xe189, 0x4cbb, { 0x88, 0x6a, 0x96, 0x87, 0x21, 0xe0, 0xe0, 0xb0 } }
>
> Same as above.
>
> > + gPhytiumPlatformPciHostInforGuid = { 0x24b99cf4, 0x2e51, 0x440e, { 0x8c, 0x7a, 0xea, 0xa2, 0xe0, 0x29, 0x32, 0xf } }
>
> Same as above.
>
> > + gShellSfHiiGuid = {0x7e57433d, 0x1016, 0x407a, { 0x9d, 0xb8, 0xf9, 0x56, 0x12, 0x19, 0x66, 0x16 } }
>
> This does not appear to be used at all, even in .inf?
>
> > +
> > +[PcdsFixedAtBuild.common]
> > + #
> > + # PCI configuration address space
>
> Not PCI?
>
> > + #
> > + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase|0x0|UINT64|0x00000000
> > + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize|0x0|UINT64|0x00000001
> > +
> > + #
> > + # PCI configuration address space
> > + #
> > + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x0|UINT64|0x00000002
> > + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x0|UINT64|0x00000003
> > +
> > + #
> > + # SPI Flash Controller Register Base Address and Size
> > + #
> > + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase|0x0|UINT64|0x00000004
> > + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x0|UINT64|0x00000005
> > + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x0|UINT64|0x00000006
> > + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x0|UINT64|0x00000007
> > + gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress|0x0|UINT32|0x00000008
> > + gPhytiumPlatformTokenSpaceGuid.PcdLogoFile |{ 0x99, 0x8b, 0xAA, 0x7B, 0xBB, 0x61, 0xD5, 0x11, 0x9A, 0x5D, 0xBB, 0x90, 0x27, 0x3F, 0xC2, 0x4D }|VOID*|0x40000013
> > +
> > +[Protocols]
> > + gPhytiumSpiMasterProtocolGuid = { 0xdf093560, 0xf955, 0x11ea, { 0x96, 0x42, 0x43, 0x9d, 0x80, 0xdd, 0x0b, 0x7c}}
> > + gPhytiumFlashProtocolGuid = { 0x00b4af42, 0xfbd0, 0x11ea, { 0x80, 0x3a, 0x27, 0xea, 0x5e, 0x65, 0xe3, 0xf6}}
> > diff --git a/Silicon/Phytium/Phytium.dsc.inc b/Silicon/Phytium/Phytium.dsc.inc
> > new file mode 100644
> > index 000000000000..15b66f6bd55d
> > --- /dev/null
> > +++ b/Silicon/Phytium/Phytium.dsc.inc
> > @@ -0,0 +1,388 @@
> > +## @file
> > +# This package provides common open source Phytium silicon modules.
> > +#
> > +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
> > +#
> > +# SPDX-License-Identifier:BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +
> > +[LibraryClasses.common]
> > + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> > + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> > +
> > +!if $(TARGET) == RELEASE
> > + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> > +!else
> > + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> > +!endif
> > +
> > + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
> > + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> > + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> > + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
> > + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> > + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> > + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> > + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> > + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> > +
> > + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> > + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> > + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
> > + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> > + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
> > + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
> > + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
> > + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> > + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> > + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
> > +
> > + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> > + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> > + HttpLib|NetworkPkg/Library/DxeHttpLib/DxeHttpLib.inf
> > +
> > + #
> > + # Assume everything is fixed at build
> > + #
> > + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> > + #BaseMemoryLib|MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf
>
> Could delete commented-out line.
>
> > + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> > +
> > + # ARM Architectural Libraries
> > + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
> > + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
> > + CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
> > + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
> > + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
> > + ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
> > + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
> > + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
> > + ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
> > + ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
> > +
> > + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
> > +
> > + TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
> > + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
> > +
> > + #
> > + # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
> > + # in the debugger will show load and unload commands for symbols. You can cut and paste this
> > + # into the command window to load symbols. We should be able to use a script to do this, but
> > + # the version of RVD I have does not support scripts accessing system memory.
> > + #
> > + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
> > + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
> > + DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
> > + AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
> > + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
> > + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> > + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> > + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> > +
> > + #
> > + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
> > + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
> > + PlatformSecureLib|SecurityPkg/Library/PlatformSecureLibNull/PlatformSecureLibNull.inf
> > + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
> > + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf
> > + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> > +
> > + # Scsi Requirements
> > + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
> > +
> > + # USB Requirements
> > + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> > +
> > + # Networking Requirements
> > + NetLib|NetworkPkg/Library/DxeNetLib/DxeNetLib.inf
> > + DpcLib|NetworkPkg/Library/DxeDpcLib/DxeDpcLib.inf
> > + UdpIoLib|NetworkPkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
> > + IpIoLib|NetworkPkg/Library/DxeIpIoLib/DxeIpIoLib.inf
> > +
> > + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
> > + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
> > + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
> > + RngLib|MdePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf
> > +
> > + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
> > + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
> > + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> > + BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLib.inf
> > + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
> > +
> > + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> > + PlatformBootManagerLib|ArmPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> > + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> > +
> > +[LibraryClasses.common.SEC]
> > + DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
> > + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
> > + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
> > + LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> > + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
> > + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
> > + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
> > + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
> > + ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
> > +
> > +[LibraryClasses.common.SEC, LibraryClasses.common.PEIM]
> > + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
> > +
> > +[LibraryClasses.common.DXE_CORE]
> > + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> > + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
> > + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> > + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> > + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> > + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
> > +
> > +[LibraryClasses.common.DXE_DRIVER]
> > + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> > + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
> > + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> > + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> > + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf
> > +
> > +[LibraryClasses.common.UEFI_APPLICATION]
> > + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> > + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> > + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> > +
> > + # UiApp dependencies
> > + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
> > + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> > +
> > +[LibraryClasses.common.UEFI_DRIVER]
> > + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> > + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
> > + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> > + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> > +
> > +[LibraryClasses.common.DXE_RUNTIME_DRIVER]
> > + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> > + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> > + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> > + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
> > +
> > +!if $(SECURE_BOOT_ENABLE) == TRUE
> > + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
> > +!endif
> > +
> > +!if $(TARGET) != RELEASE
> > + DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf
> > +!endif
> > + VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf
> > +[LibraryClasses.AARCH64.DXE_RUNTIME_DRIVER]
> > + #
> > + # PSCI support in EL3 may not be available if we are not running under a PSCI
> > + # compliant secure firmware, but since the default VExpress EfiResetSystemLib
> > + # cannot be supported at runtime (due to the fact that the syscfg MMIO registers
> > + # cannot be runtime remapped), it is our best bet to get ResetSystem functionality
> > + # on these platforms.
> > + #
>
> The above comment should not be true anymore.
> Presumably, you have a working PSCI implementation?
>
> > + EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf
> > +
> > +[LibraryClasses.ARM, LibraryClasses.AARCH64]
> > + #
> > + # It is not possible to prevent the ARM compiler for generic intrinsic functions.
> > + # This library provides the instrinsic functions generate by a given compiler.
> > + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
> > + #
> > + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
> > +
> > + # Add support for GCC stack protector
> > + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
> > +
> > +[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]
> > + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> > +
> > +[BuildOptions]
> > + RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
> > + GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
> > +
> > +[BuildOptions.AARCH64.EDKII.DXE_RUNTIME_DRIVER]
> > + GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
> > +
> > +################################################################################
> > +#
> > +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> > +#
> > +################################################################################
> > +
> > +[PcdsFeatureFlag.common]
> > + # If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
> > + # It could be set FALSE to save size.
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
> > +
> > + # Force the UEFI GIC driver to use GICv2 legacy mode. To use
> > + # GICv3 without GICv2 legacy in UEFI, the ARM Trusted Firmware needs
> > + # to configure the Non-Secure interrupts in the GIC Redistributors
> > + # which is not supported at the moment.
> > + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE
> > + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|FALSE
> > + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
> > + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
> > + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
> > +
> > + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
> > +
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
> > +
> > + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
> > + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
> > +
> > + # Indicates if EFI 1.1 ISO 639-2 language supports are obsolete
> > + # TRUE - Deprecate global variable LangCodes.
> > + # FALSE - Does not deprecate global variable LangCodes.
> > + # Deprecate Global Variable LangCodes.
> > + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangDeprecate|TRUE
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
> > +
> > +[PcdsFixedAtBuild.common]
> > + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
> > + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
> > + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
> > + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
> > + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
> > + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0
> > + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
> > + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
> > + gEfiNetworkPkgTokenSpaceGuid.PcdAllowHttpConnections|TRUE
> > +
> > + # DEBUG_ASSERT_ENABLED 0x01
> > + # DEBUG_PRINT_ENABLED 0x02
> > + # DEBUG_CODE_ENABLED 0x04
> > + # CLEAR_MEMORY_ENABLED 0x08
> > + # ASSERT_BREAKPOINT_ENABLED 0x10
> > + # ASSERT_DEADLOOP_ENABLED 0x20
> > +!if $(TARGET) == RELEASE
> > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
> > +!else
> > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
> > +!endif
> > +
> > + # DEBUG_INIT 0x00000001 // Initialization
> > + # DEBUG_WARN 0x00000002 // Warnings
> > + # DEBUG_LOAD 0x00000004 // Load events
> > + # DEBUG_FS 0x00000008 // EFI File system
> > + # DEBUG_POOL 0x00000010 // Alloc & Free's
> > + # DEBUG_PAGE 0x00000020 // Alloc & Free's
> > + # DEBUG_INFO 0x00000040 // Verbose
> > + # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
> > + # DEBUG_VARIABLE 0x00000100 // Variable
> > + # DEBUG_BM 0x00000400 // Boot Manager
> > + # DEBUG_BLKIO 0x00001000 // BlkIo Driver
> > + # DEBUG_NET 0x00004000 // SNI Driver
> > + # DEBUG_UNDI 0x00010000 // UNDI Driver
> > + # DEBUG_LOADFILE 0x00020000 // UNDI Driver
> > + # DEBUG_EVENT 0x00080000 // Event messages
> > + # DEBUG_GCD 0x00100000 // Global Coherency Database changes
> > + # DEBUG_CACHE 0x00200000 // Memory range cachability changes
> > + # DEBUG_ERROR 0x80000000 // Error
> > + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
> > +
> > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> > +
> > + #gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
> > + #gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
> > + #gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
>
> The above threee lines can be deleted (the Pcds no longer exist in edk2).
>
> > + # 20ms
> > + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|200000
> > +
> > + #
> > + # Optional feature to help prevent EFI memory map fragments
> > + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
> > + # Values are in EFI Pages (4K). DXE Core will make sure that
> > + # at least this much of each type of memory can be allocated
> > + # from a single memory range. This way you only end up with
> > + # maximum of two fragements for each type in the memory map
> > + # (the memory used, and the free memory that was prereserved
> > + # but not used).
> > + #
> > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
> > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
> > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
> > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
> > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65
> > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
> > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
> > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
> > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
> > +
> > + # RunAxf support via Dynamic Shell Command protocol
> > + # We want to use the Shell Libraries but don't want it to initialise
> > + # automatically. We initialise the libraries when the command is called by the
> > + # Shell.
> > + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> > +
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
> > +
> > +!if $(SECURE_BOOT_ENABLE) == TRUE
> > + # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot
> > + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04
> > + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04
> > + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04
> > +!endif
> > +
> > +!if $(SECURE_BOOT_ENABLE) == TRUE
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
> > +!else
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x4000
> > +!endif
> > +
> > + # Default platform supported RFC 4646 languages: English & French & Chinese Simplified.
> > + # Default Value of PlatformLangCodes Variable.
> > + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US;zh-Hans"
> > +
> > + # Default current RFC 4646 language: Chinese Simplified.
> > + # Default Value of PlatformLang Variable.
> > + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLang|"en-US"
> > + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|4
> > + #
> > + # ACPI Table Version
> > + #
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
> > + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|67
> > +
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
> > +
> > +[PcdsDynamicDefault.common.DEFAULT]
> > + ## This PCD defines the video horizontal resolution.
> > + # This PCD could be set to 0 then video resolution could be at highest resolution.
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|640
> > + ## This PCD defines the video vertical resolution.
> > + # This PCD could be set to 0 then video resolution could be at highest resolution.
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|480
> > +
> > + ## This PCD defines the Console output row and the default value is 80 according to UEFI spec.
> > + # This PCD could be set to 0 then console output could be at max column and max row.
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|128
> > + ## This PCD defines the Console output column and the default value is 25 according to UEFI spec.
> > + # This PCD could be set to 0 then console output could be at max column and max row.
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|40
> > +
> > + ## Specify the video horizontal resolution of text setup.
> > + # @Prompt Video Horizontal Resolution of Text Setup
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
> > +
> > + ## Specify the video vertical resolution of text setup.
> > + # @Prompt Video Vertical Resolution of Text Setup
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
> > +
> > + ## Specify the console output column of text setup.
> > + # @Prompt Console Output Column of Text Setup
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|128
> > + ## Specify the console output row of text setup.
> > + # @Prompt Console Output Row of Text Setup
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|40
> > +
> > + ## The number of seconds that the firmware will wait before initiating the original default boot selection.
> > + # A value of 0 indicates that the default boot selection is to be initiated immediately on boot.
> > + # The value of 0xFFFF then firmware will wait for user input before booting.
> > + # @Prompt Boot Timeout (s)
> > + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|5
> > diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
> > new file mode 100644
> > index 000000000000..ef01cc217ace
> > --- /dev/null
> > +++ b/Platform/Phytium/Durian/DurianPkg.dsc
> > @@ -0,0 +1,302 @@
> > +## @file
> > +# This package provides common open source Phytium Platform modules.
> > +#
> > +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
> > +#
> > +# SPDX-License-Identifier:BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +################################################################################
> > +#
> > +# Defines Section - statements that will be processed to create a Makefile.
> > +#
> > +################################################################################
> > +[Defines]
> > + PLATFORM_NAME = DurianPkg
> > + PLATFORM_GUID = 8f7ac876-3e7c-11eb-86cb-33f68535d613
> > + PLATFORM_VERSION = 0.1
> > + DSC_SPECIFICATION = 0x00010005
> > + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
> > + SUPPORTED_ARCHITECTURES = AARCH64
> > + BUILD_TARGETS = DEBUG|RELEASE
>
> Could you also add NOOPT?
>
> > + SKUID_IDENTIFIER = DEFAULT
> > + FLASH_DEFINITION = Platform/Phytium/Durian/DurianPkg.fdf
> > +
> > +!include Silicon/Phytium/Phytium.dsc.inc
> > +
> > +[LibraryClasses.common]
> > + # Phytium Platform library
> > + ArmPlatformLib|Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf
> > +
> > + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
> > +
> > + # PL011 UART Driver and Dependency Libraries
> > + SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
> > + PL011UartClockLib|ArmPlatformPkg/Library/PL011UartClockLib/PL011UartClockLib.inf
> > + PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
> > +
> > +[LibraryClasses.common.DXE_DRIVER]
> > +
> > +
> > +################################################################################
> > +#
> > +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> > +#
> > +################################################################################
> > +[PcdsFixedAtBuild.common]
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|L"Durian Platform"
> > +
> > + gArmTokenSpaceGuid.PcdVFPEnabled|1
> > + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0x303
> > +
> > + gArmPlatformTokenSpaceGuid.PcdCoreCount|4
> > + gArmPlatformTokenSpaceGuid.PcdClusterCount|2
> > +
> > + #
> > + # NV Storage PCDs.
> > + #
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xe00000
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xe10000
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xe20000
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
> > +
> > + # Size of the region used by UEFI in permanent memory (Reserved 64MB)
> > + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
> > +
> > + #
> > + # PL011 - Serial Terminal
> > + #
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x28001000
> > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth|0
> > + gArmPlatformTokenSpaceGuid.PL011UartClkInHz|48000000
> > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
> > +
> > +
> > + #
> > + # ARM General Interrupt Controller
> > + #
> > + gArmTokenSpaceGuid.PcdGicDistributorBase|0x29900000
> > + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x29980000
> > + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x29c00000
> > +
> > + # System IO space
> > + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase|0x0
> > + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize|0x40000000
> > +
> > + # System Memory (2GB ~ 4GB - 64MB), the top 64MB is reserved for PBF
>
> What is PBF? The EL3 firmware? Please clarify in comment.
>
> > + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
> > + gArmTokenSpaceGuid.PcdSystemMemorySize|0x7B000000
> > +
> > + # Stack Size
> > + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
> > +
> > + #
> > + # Designware PCI Root Complex
> > + #
> > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000
> > + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|28
> > + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase|0x40000000
> > + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize|0x10000000
> > + gArmTokenSpaceGuid.PcdPciBusMin|0
> > + gArmTokenSpaceGuid.PcdPciBusMax|255
> > + gArmTokenSpaceGuid.PcdPciIoBase|0x00000
> > + gArmTokenSpaceGuid.PcdPciIoSize|0xf00000
> > + gArmTokenSpaceGuid.PcdPciIoTranslation|0x50000000
> > + gArmTokenSpaceGuid.PcdPciMmio32Base|0x58000000
> > + gArmTokenSpaceGuid.PcdPciMmio32Size|0x28000000
> > + gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0
> > + gArmTokenSpaceGuid.PcdPciMmio64Base|0x1000000000
> > + gArmTokenSpaceGuid.PcdPciMmio64Size|0x1000000000
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
> > +
> > + #
> > + # SPI Flash Control Register Base Address and Size
> > + #
> > + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase|0x0
> > + gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize|0x1000000
> > + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase|0x28014000
> > + gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize|0x1000
> > +
> > + #
> > + # RTC I2C Controller Register Base Address and Speed
> > + #
> > + gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress|0x2800D000
> > + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"V1.0"
>
> Could make sense to move the firmware version string next to the
> firmware vendor one.
>
> > +
> > +################################################################################
> > +#
> > +# Components Section - list of all EDK II Modules needed by this Platform
> > +#
> > +################################################################################
> > +[Components.common]
> > + #
> > + # PCD database
> > + #
> > + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > +
> > + ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf
> > + ShellPkg/Application/Shell/Shell.inf {
> > + <LibraryClasses>
> > + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> > + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> > + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
> > + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> > + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
> > + NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.inf
> > + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
> > + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
> > + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> > + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> > + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> > + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
> > + }
> > +
> > + ArmPlatformPkg/PrePi/PeiMPCore.inf {
> > + <LibraryClasses>
> > + ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
> > + }
> > +
> > + #
> > + #Dxe core entry
> > + #
> > + MdeModulePkg/Core/Dxe/DxeMain.inf {
> > + <LibraryClasses>
> > + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> > + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
> > + }
> > +
> > + #DXE driver
> > + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> > + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> > + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
> > + <LibraryClasses>
> > + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> > + }
> > + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> > + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
> > +
> > + #
> > + # Common Arm Timer and Gic Components
> > + #
> > + ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> > + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> > + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> > + ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> > +
> > + #
> > + # security system
> > + #
> > + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
> > + <LibraryClasses>
> > + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
> > + }
> > +
> > + #
> > + #network, mod for https boot.
> > + #
> > + NetworkPkg/SnpDxe/SnpDxe.inf
> > + NetworkPkg/DpcDxe/DpcDxe.inf
> > + NetworkPkg/MnpDxe/MnpDxe.inf
> > + NetworkPkg/ArpDxe/ArpDxe.inf
> > + NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf
> > + NetworkPkg/Ip4Dxe/Ip4Dxe.inf
> > + NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf
> > + NetworkPkg/Udp4Dxe/Udp4Dxe.inf
> > + NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf
> > +
> > + NetworkPkg/Ip6Dxe/Ip6Dxe.inf
> > + NetworkPkg/Udp6Dxe/Udp6Dxe.inf
> > + NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
> > + NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
> > + NetworkPkg/TcpDxe/TcpDxe.inf
> > +
> > + NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
> > +
> > + NetworkPkg/DnsDxe/DnsDxe.inf
> > + NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
> > + NetworkPkg/HttpDxe/HttpDxe.inf
> > + #NetworkPkg/HttpBootDxe/HttpBootDxe.inf
> > +
> > + # FV Filesystem
> > + MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
> > +
> > + #
> > + # Common Console Components
> > + #
> > + # ConIn,ConOut,StdErr
> > + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> > + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> > + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> > + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> > + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> > +
> > + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
> > +
> > + #
> > + # Hii database init
> > + #
> > + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> > +
> > + #
> > + # FAT filesystem + GPT/MBR partitioning
> > + #
> > + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> > + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> > + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> > + FatPkg/EnhancedFatDxe/Fat.inf
> > +
> > + #
> > + # Generic Watchdog Timer
> > + #
> > + ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
> > +
> > + #
> > + # Usb Support
> > + #
> > + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> > + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> > + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> > + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> > + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> > + MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
> > + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> > +
> > + #
> > + # IDE/AHCI Support
> > + #
> > + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> > + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> > + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> > + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> > + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> > +
> > + #
> > + # The following 2 module perform the same work except one operate variable.
> > + # Only one of both should be put into fdf.
> > + #
> > + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> > +
> > + #
> > + # NVME Support
> > + #
> > + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> > +
> > + #
> > + # Bds
> > + #
> > + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> > + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> > + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> > + MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf
> > + MdeModulePkg/Application/UiApp/UiApp.inf {
> > + <LibraryClasses>
> > + NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
> > + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
> > + NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
> > + }
> > + MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
> > +
> > diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Durian/DurianPkg.fdf
> > new file mode 100644
> > index 000000000000..f2f4cbc9ac7f
> > --- /dev/null
> > +++ b/Platform/Phytium/Durian/DurianPkg.fdf
> > @@ -0,0 +1,199 @@
> > +## @file
> > +# This package provides common open source Phytium Platform modules.
> > +#
> > +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
> > +#
> > +# SPDX-License-Identifier:BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +################################################################################
> > +#
> > +# FD Section
> > +# The [FD] Section is made up of the definition statements and a
> > +# description of what goes into the Flash Device Image. Each FD section
> > +# defines one flash "device" image. A flash device image may be one of
> > +# the following: Removable media bootable image (like a boot floppy
> > +# image,) an Option ROM image (that would be "flashed" into an add-in
> > +# card,) a System "Flash" image (that would be burned into a system's
> > +# flash) or an Update ("Capsule") image that will be used to update and
> > +# existing system flash.
> > +#
> > +################################################################################
> > +
> > +[FD.PHYTIUM]
> > +BaseAddress = 0x88000000|gArmTokenSpaceGuid.PcdFdBaseAddress
> > +Size = 0x01000000|gArmTokenSpaceGuid.PcdFdSize
> > +ErasePolarity = 1
> > +
> > +# This one is tricky, it must be: BlockSize * NumBlocks = Size
> > +BlockSize = 0x10000
> > +NumBlocks = 0x100
> > +
> > +################################################################################
> > +#
> > +# Following are lists of FD Region layout which correspond to the locations of different
> > +# images within the flash device.
> > +#
> > +# Regions must be defined in ascending order and may not overlap.
> > +#
> > +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
> > +# the pipe "|" character, followed by the size of the region, also in hex with the leading
> > +# "0x" characters. Like:
> > +# Offset|Size
> > +# PcdOffsetCName|PcdSizeCName
> > +# RegionType <FV, DATA, or FILE>
> > +#
> > +################################################################################
> > +
> > +0x00000000|0x200000
> > +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
> > +FV = FVMAIN_COMPACT
> > +
> > +################################################################################
> > +#
> > +# FV Section
> > +#
> > +# [FV] section is used to define what components or modules are placed within a flash
> > +# device file. This section also defines order the components and modules are positioned
> > +# within the image. The [FV] section consists of define statements, set statements and
> > +# module statements.
> > +#
> > +################################################################################
> > +
> > +[FV.FvMain]
> > +BlockSize = 0x40
> > +NumBlocks = 0 # This FV gets compressed so make it just big enough
> > +FvAlignment = 16 # FV alignment and FV attributes setting.
> > +ERASE_POLARITY = 1
> > +MEMORY_MAPPED = TRUE
> > +STICKY_WRITE = TRUE
> > +LOCK_CAP = TRUE
> > +LOCK_STATUS = TRUE
> > +WRITE_DISABLED_CAP = TRUE
> > +WRITE_ENABLED_CAP = TRUE
> > +WRITE_STATUS = TRUE
> > +WRITE_LOCK_CAP = TRUE
> > +WRITE_LOCK_STATUS = TRUE
> > +READ_DISABLED_CAP = TRUE
> > +READ_ENABLED_CAP = TRUE
> > +READ_STATUS = TRUE
> > +READ_LOCK_CAP = TRUE
> > +READ_LOCK_STATUS = TRUE
> > +
> > + APRIORI DXE {
> > + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > + }
> > +
> > + INF MdeModulePkg/Core/Dxe/DxeMain.inf
> > + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > +
> > + #
> > + # PI DXE Drivers producing Architectural Protocols (EFI Services)
> > + #
> > + #INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> > + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> > + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> > + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
> > + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> > +
> > + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> > + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> > +
> > + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
> > + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
> > + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
> > + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
> > +
> > + # Variable services
> > + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> > + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> > +
> > + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> > +
> > + #
> > + # Multiple Console IO support
> > + #
> > + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> > + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> > + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
> > + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> > + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> > +
> > + #
> > + # FAT filesystem + GPT/MBR partitioning
> > + #
> > + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> > + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> > + INF FatPkg/EnhancedFatDxe/Fat.inf
> > + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> > +
> > + #
> > + # SATA Controller
> > + #
> > + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> > + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> > + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> > + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> > + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> > +
> > + #
> > + # NVMe boot devices
> > + #
> > + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> > +
> > + #
> > + # NetWork
> > + #
> > + INF NetworkPkg/SnpDxe/SnpDxe.inf
> > + INF NetworkPkg/DpcDxe/DpcDxe.inf
> > + INF NetworkPkg/MnpDxe/MnpDxe.inf
> > + INF NetworkPkg/ArpDxe/ArpDxe.inf
> > + INF NetworkPkg/Dhcp4Dxe/Dhcp4Dxe.inf
> > + INF NetworkPkg/Ip4Dxe/Ip4Dxe.inf
> > + INF NetworkPkg/Mtftp4Dxe/Mtftp4Dxe.inf
> > + INF NetworkPkg/Udp4Dxe/Udp4Dxe.inf
> > + INF NetworkPkg/VlanConfigDxe/VlanConfigDxe.inf
> > +
> > + #
> > + # UEFI applications
> > + #
> > + INF ShellPkg/Application/Shell/Shell.inf
> > +
> > + #
> > + # Bds
> > + #
> > + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> > + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> > + INF MdeModulePkg/Universal/DriverSampleDxe/DriverSampleDxe.inf
> > + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> > + INF MdeModulePkg/Application/UiApp/UiApp.inf
> > +
> > +[FV.FVMAIN_COMPACT]
> > +FvAlignment = 16
> > +ERASE_POLARITY = 1
> > +MEMORY_MAPPED = TRUE
> > +STICKY_WRITE = TRUE
> > +LOCK_CAP = TRUE
> > +LOCK_STATUS = TRUE
> > +WRITE_DISABLED_CAP = TRUE
> > +WRITE_ENABLED_CAP = TRUE
> > +WRITE_STATUS = TRUE
> > +WRITE_LOCK_CAP = TRUE
> > +WRITE_LOCK_STATUS = TRUE
> > +READ_DISABLED_CAP = TRUE
> > +READ_ENABLED_CAP = TRUE
> > +READ_STATUS = TRUE
> > +READ_LOCK_CAP = TRUE
> > +READ_LOCK_STATUS = TRUE
> > +
> > + INF ArmPlatformPkg/PrePi/PeiMPCore.inf
> > +
> > + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> > + SECTION FV_IMAGE = FVMAIN
> > + }
> > + }
> > +
> > +!include Silicon/Phytium/Phytium.fdf.inc
> > diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf
> > new file mode 100644
> > index 000000000000..7ad0f31549ef
> > --- /dev/null
> > +++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf
> > @@ -0,0 +1,66 @@
> > +#/** @file
> > +# Library for Phytium Platform.
> > +#
> > +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +#**/
> > +
> > +[Defines]
> > + INF_VERSION = 0x00010019
> > + BASE_NAME = PhytiumPlatformLib
> > + FILE_GUID = fac08f56-40fe-11eb-a2a3-27b46864b1f3
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = ArmPlatformLib
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > + MdeModulePkg/MdeModulePkg.dec
> > + EmbeddedPkg/EmbeddedPkg.dec
> > + ArmPkg/ArmPkg.dec
> > + ArmPlatformPkg/ArmPlatformPkg.dec
> > + Silicon/Phytium/Phytium.dec
>
> Can you please sort paths alphabetically - throughout all of the .inf
> files in all the patches?
>
> > +
> > +[LibraryClasses]
> > + IoLib
> > + ArmLib
> > + ArmSmcLib
> > + MemoryAllocationLib
> > + SerialPortLib
> > + HobLib
> > + BaseMemoryLib
>
> And again for all the libraryclasses, sources, guids, fixedpcd, pcd...?
> It makes it much quicker to read through the list.
>
> > +
> > +[Sources.common]
> > + PhytiumPlatformLib.c
> > + PhytiumPlatformLibMem.c
> > +
> > +[Sources.AARCH64]
> > + AArch64/PhytiumPlatformHelper.S
> > +
> > +[Guids]
> > + gPhytiumPlatformMemoryInforGuid
> > + gPhytiumPlatformCpuInforGuid
> > + gPhytiumPlatformPciHostInforGuid
> > +
> > +[FixedPcd]
> > + gArmTokenSpaceGuid.PcdSystemMemoryBase
> > + gArmTokenSpaceGuid.PcdSystemMemorySize
> > + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoBase
> > + gPhytiumPlatformTokenSpaceGuid.PcdSystemIoSize
> > + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigBase
> > + gPhytiumPlatformTokenSpaceGuid.PcdPciConfigSize
> > + gArmTokenSpaceGuid.PcdPciBusMin
> > + gArmTokenSpaceGuid.PcdPciBusMax
> > + gArmTokenSpaceGuid.PcdPciIoBase
> > + gArmTokenSpaceGuid.PcdPciIoSize
> > + gArmTokenSpaceGuid.PcdPciIoTranslation
> > + gArmTokenSpaceGuid.PcdPciMmio32Base
> > + gArmTokenSpaceGuid.PcdPciMmio32Size
> > + gArmTokenSpaceGuid.PcdPciMmio32Translation
> > + gArmTokenSpaceGuid.PcdPciMmio64Base
> > + gArmTokenSpaceGuid.PcdPciMmio64Size
> > +
> > +[Pcd]
> > + gArmPlatformTokenSpaceGuid.PcdCoreCount
> > diff --git a/Silicon/Phytium/Include/PhytiumSystemServiceInterface.h b/Silicon/Phytium/Include/PhytiumSystemServiceInterface.h
> > new file mode 100644
> > index 000000000000..ddea33dbc275
> > --- /dev/null
> > +++ b/Silicon/Phytium/Include/PhytiumSystemServiceInterface.h
> > @@ -0,0 +1,112 @@
> > +/** @file
> > +
> > + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#ifndef __OEMSVC_H_
> > +#define __OEMSVC_H_
>
> Please don't use leading __ (or _) in macro names - they are reserved
> for toolchain use.
>
> > +
> > +/* SMC function IDs for OEM Service queries */
> > +#define PHYTIUM_OEM_SVC_PSSI_VERSION 0x8200ff03
> > +#define PHYTIUM_OEM_SVC_PBF_VERSION 0x82000001
> > +#define PHYTIUM_OEM_SVC_CPU_VERSION 0xc2000002
> > +#define PHYTIUM_OEM_SVC_CPU_MAPS 0xc2000003
> > +#define PHYTIUM_OEM_SVC_CPU_CONF 0xc2000004
> > +#define PHYTIUM_OEM_SVC_MEM_REGIONS 0xc2000005
> > +#define PHYTIUM_OEM_SVC_MCU_DIMMS 0xc2000006
> > +#define PHYTIUM_OEM_SVC_PCI_CONTROLLER 0xc2000007
> > +#define PHYTIUM_OEM_SVC_HOST_BRIDGE 0xc2000008
> > +#define PHYTIUM_OEM_SVC_GET_FLASH_CMD 0xC200000C
> > +
> > +#define PHYTIUM_IOBASE_MASK 0xfffffff
> > +#define PHYTIUM_MEMIO32_MASK 0xffffffff
> > +#define PHYTIUM_MEMIO64_MASK 0xffffffffff
> > +
> > +#pragma pack(1)
> > +
> > +typedef struct {
> > + UINT64 CpuMapCount;
> > + UINT64 CpuMap[1];
> > +} PHYTIUM_CPU_MAP_INFOR;
>
> I see this abbreviation of "information" to "infor" in many places.
> Could this be shortened to "info", which is a more common
> abbreviation? In all locations.
>
> > +
> > +
> > +typedef struct {
> > + UINT64 CpuFreq; // Hz
> > + UINT64 CpuL3CacheSize; // Byte
> > + UINT64 CpuL3CacheLineSize; // Byte
> > +} PHYTIUM_CPU_COURE_INFOR;
> > +
> > +typedef struct {
> > + UINT64 CupVersion; //cpu version
> > + PHYTIUM_CPU_COURE_INFOR CpuCoreInfo; //cpu core info
> > + PHYTIUM_CPU_MAP_INFOR CpuMapInfo; //cpu map info
> > +}PHYTIUM_CPU_INFO;
> > +
> > +typedef struct {
> > + UINT64 MemSize; // MB
> > + UINT64 MemDramId;
> > + UINT64 MemModuleId;
> > + UINT64 MemSerial;
> > + UINT64 MemSlotNumber;
> > + UINT64 MemFeatures;
> > +} MCU_DIMM;
>
> Could all of these struct names have PHYTIUM_ prefix?
> Some of them are very generic, and could potentially clash with common
> code in future.
>
> > +
> > +#define MCU_DIMM_MAXCOUNT 2
> > +
> > +typedef struct {
> > + UINT64 MemFreq; // MHz
> > + UINT64 MemDimmCount;
> > + MCU_DIMM McuDimm[1];
> > +} MCU_DIMMS;
> > +
> > +typedef struct {
> > + UINT64 MemStart;
> > + UINT64 MemSize;
> > + UINT64 MemNodeId;
> > +} MEMORY_BLOCK;
> > +
> > +typedef struct {
> > + UINT64 MemBlockCount;
> > + MEMORY_BLOCK MemBlock[1];
> > +} MEMORY_INFOR;
> > +
> > +typedef struct {
> > + UINT8 PciLane;
> > + UINT8 PciSpeed;
> > + UINT8 Reserved[6];
> > +} PCI_BLOCK;
> > +
> > +typedef struct {
> > + UINT64 PciCount;
> > + PCI_BLOCK PciBlock[1];
> > +} PHYTIUM_PCI_CONTROLLER;
> > +
> > +typedef struct {
> > + UINT8 BusStart;
> > + UINT8 BusEnd;
> > + UINT8 Reserved[6];
> > + UINT64 PciConfigBase;
> > + UINT64 IoBase;
> > + UINT64 IoSize;
> > + UINT64 Mem32Base;
> > + UINT64 Mem32Size;
> > + UINT64 Mem64Base;
> > + UINT64 Mem64Size;
> > + UINT16 IntA;
> > + UINT16 IntB;
> > + UINT16 IntC;
> > + UINT16 IntD;
> > +} PCI_HOST_BLOCK;
> > +
> > +typedef struct {
> > + UINT64 PciHostCount;
> > + PCI_HOST_BLOCK PciHostBlock[1];
> > +} PHYTIUM_PCI_HOST_BRIDGE;
> > +
> > +#pragma pack ()
> > +
> > +
> > +#endif /* __OEMSVC_H_ */
> > diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c
> > new file mode 100644
> > index 000000000000..2affc9c131b9
> > --- /dev/null
> > +++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c
> > @@ -0,0 +1,135 @@
> > +/** @file
> > + Library for Phytium platform.
> > +
> > + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#include <Library/IoLib.h>
> > +#include <Library/ArmPlatformLib.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/PcdLib.h>
>
> Can we sort include statements alphabetically as well?
> In this case, Library/IoLib.h after Library/DebugLib.h?
>
> > +
> > +#include <Ppi/ArmMpCoreInfo.h>
> > +
> > +ARM_CORE_INFO mPhytiumMpCoreInfoTable[] = {
> > + {
> > + // Cluster 0, Core 0
> > + 0x0, 0x0,
> > +
> > + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> > + (EFI_PHYSICAL_ADDRESS)0,
> > + (EFI_PHYSICAL_ADDRESS)0,
> > + (EFI_PHYSICAL_ADDRESS)0,
> > + (UINT64)0xFFFFFFFF
> > + }
> > +};
> > +
> > +/*
> > + This function geted the current Boot Mode.
> > +
> > + This function returns the boot reason on the platform.
> > +
> > + @return Return the current Boot Mode of the platform.
> > +
> > +*/
> > +EFI_BOOT_MODE
> > +ArmPlatformGetBootMode (
> > + VOID
> > + )
> > +{
> > + return BOOT_WITH_FULL_CONFIGURATION;
> > +}
> > +
> > +
> > +/**
> > + Initialize controllers that must setup in the normal world.
> > +
> > + This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
> > + in the PEI phase.
> > +
> > + @retval EFI_SUCCESS ArmPlatformInitialize() is executed successfully.
> > +
> > +**/
> > +RETURN_STATUS
> > +ArmPlatformInitialize (
> > + IN UINTN MpId
> > + )
> > +{
> > + return RETURN_SUCCESS;
> > +}
> > +
> > +
> > +/**
> > + This function Inited the system (or sometimes called permanent) memory.
> > +
> > + This memory is generally represented by the DRAM.
> > +
> > + @param[in] None.
> > +
> > + @retval None.
> > +
> > +**/
> > +VOID
> > +ArmPlatformInitializeSystemMemory (
> > + VOID
> > + )
> > +{
> > + // Nothing to do here
> > +}
> > +
> > +
> > +/**
> > + This function geted the information of core.
> > +
> > + @param[out] CoreCount The count of CoreInfoTable.
> > + @param[out] ArmCoreTable The pointer of CoreInfoTable.
> > +
> > + @retval EFI_SUCCESS PrePeiCoreGetMpCoreInfo() is executed successfully.
> > +
> > +**/
> > +EFI_STATUS
> > +PrePeiCoreGetMpCoreInfo (
> > + OUT UINTN *CoreCount,
> > + OUT ARM_CORE_INFO **ArmCoreTable
> > + )
> > +{
> > + *CoreCount = PcdGet32 (PcdCoreCount);
> > + *ArmCoreTable = mPhytiumMpCoreInfoTable;
> > + return EFI_SUCCESS;
> > +}
> > +
> > +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
> > +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
> > +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> > +
> > +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =
> > +{
> > + {
> > + EFI_PEI_PPI_DESCRIPTOR_PPI,
> > + &mArmMpCoreInfoPpiGuid,
> > + &mMpCoreInfoPpi
> > + }
> > +};
> > +
> > +
> > +/**
> > + This function geted the information of Ppitable.
> > +
> > + @param[out] PpiListSize The size of Ppitable.
> > + @param[out] PpiList The pointer of Ppitable.
> > +
> > + @retval None.
> > +
> > +**/
> > +VOID
> > +ArmPlatformGetPlatformPpiList (
> > + OUT UINTN *PpiListSize,
> > + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> > + )
> > +{
> > + *PpiListSize = sizeof(gPlatformPpiTable);
> > + *PpiList = gPlatformPpiTable;
> > +}
> > diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c
> > new file mode 100644
> > index 000000000000..ff70cb28a20a
> > --- /dev/null
> > +++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c
> > @@ -0,0 +1,148 @@
> > +/** @file
> > + Library of memory map for Phytium platform.
> > +
> > + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#include <Library/ArmPlatformLib.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/HobLib.h>
> > +#include <Library/PcdLib.h>
> > +#include <Library/IoLib.h>
> > +#include <Library/MemoryAllocationLib.h>
> > +#include <Library/BaseMemoryLib.h>
> > +#include <Library/ArmSmcLib.h>
>
> Sort alphabetically?
>
> > +#include <PhytiumSystemServiceInterface.h>
> > +
> > +// Number of Virtual Memory Map Descriptors
> > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 32
> > +
> > +// DDR attributes
> > +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
> > +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
> > +
> > +/**
> > + Return the Virtual Memory Map of your platform
> > +
> > + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
> > +
> > + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> > + Virtual Memory mapping. This array must be ended by a zero-filled
> > + entry
> > +**/
> > +VOID
> > +ArmPlatformGetVirtualMemoryMap (
> > + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
> > + )
> > +{
> > + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
> > + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;
> > + MEMORY_BLOCK *MemBlock = NULL;
> > + MEMORY_INFOR *MemInfor = NULL;
>
> Coding style says no to initialize variables on defintion.
> You can set these to NULL if SMC call fails.
>
> > + ARM_SMC_ARGS ArmSmcArgs;
> > + UINT32 MemBlockCnt = 0, Index, Index1;
>
> Coding style also says only one variable defined per line.
> And having Index and Index1 becomes tricky to read. Just call the
> second one J.
>
> > +
> > + CacheAttributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> > +
> > + ASSERT (VirtualMemoryMap != NULL);
> > + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> > + if (VirtualMemoryTable == NULL) {
> > + return;
> > + }
> > +
> > + ResourceAttributes =
> > + EFI_RESOURCE_ATTRIBUTE_PRESENT |
> > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
> > + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
> > + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
> > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
> > + EFI_RESOURCE_ATTRIBUTE_TESTED;
> > +
> > + MemInfor = AllocatePages(1);
> > + ASSERT(MemInfor != NULL);
>
> Space before (
>
> > +
> > + ArmSmcArgs.Arg0 = PHYTIUM_OEM_SVC_MEM_REGIONS;
> > + ArmSmcArgs.Arg1 = (UINTN)MemInfor;
> > + ArmSmcArgs.Arg2 = EFI_PAGE_SIZE;
> > + ArmCallSmc (&ArmSmcArgs);
> > + if (ArmSmcArgs.Arg0 == 0) {
> > + MemBlockCnt = MemInfor->MemBlockCount;
> > + MemBlock = MemInfor->MemBlock;
> > + } else {
> > + ASSERT(FALSE);
>
> Space before (
>
> > + }
>
> Actually, this SMC call should be broken out into a separate helper
> function.
>
> > +
> > + //Soc Io Space
> > + VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemIoBase);
> > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemIoBase);
> > + VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemIoSize);
> > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > +
> > + //
> > + // PCI Configuration Space
> > + //
> > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciConfigBase);
> > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciConfigBase);
> > + VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciConfigSize);
> > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > +
> > + //
> > + // PCI Memory Space
> > + //
> > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciIoBase) + PcdGet64(PcdPciIoTranslation);
> > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciIoBase) + PcdGet64(PcdPciIoTranslation);
> > + VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciIoSize);
> > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > +
> > + //
> > + // PCI Memory Space
> > + //
> > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdPciMmio32Base);
> > + VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdPciMmio32Base);
> > + VirtualMemoryTable[Index].Length = PcdGet32 (PcdPciMmio32Size);
> > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > +
> > + //
> > + // 64-bit PCI Memory Space
> > + //
> > + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciMmio64Base);
> > + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciMmio64Base);
> > + VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciMmio64Size);
> > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> > +
> > + //DDR
> > + for (Index1 = 0; Index1 < MemBlockCnt; Index1++) {
> > + VirtualMemoryTable[++Index].PhysicalBase = MemBlock->MemStart;
> > + VirtualMemoryTable[Index].VirtualBase = MemBlock->MemStart;
> > + VirtualMemoryTable[Index].Length = MemBlock->MemSize;
> > + VirtualMemoryTable[Index].Attributes = CacheAttributes;
> > +
> > + BuildResourceDescriptorHob (
> > + EFI_RESOURCE_SYSTEM_MEMORY,
> > + ResourceAttributes,
> > + MemBlock->MemStart,
> > + MemBlock->MemSize);
> > +
> > + MemBlock ++;
>
> No space before ++.
>
> > + }
> > +
> > + // End of Table
> > + VirtualMemoryTable[++Index].PhysicalBase = 0;
> > + VirtualMemoryTable[Index].VirtualBase = 0;
> > + VirtualMemoryTable[Index].Length = 0;
> > + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
> > +
> > + ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> > +
> > + for (Index1 = 0; Index1 < Index; Index1++) {
> > + DEBUG((DEBUG_ERROR, "PhysicalBase %12lx VirtualBase %12lx Length %12lx Attributes %12lx\n", VirtualMemoryTable[Index1].PhysicalBase,\
>
> Please break long line after ",
>
> > + VirtualMemoryTable[Index1].VirtualBase, VirtualMemoryTable[Index1].Length, VirtualMemoryTable[Index1].Attributes));
>
> Please break long line.
>
> > + }
>
> Actually, this loop should also be a static helper function.
>
> > +
> > + *VirtualMemoryMap = VirtualMemoryTable;
> > +}
> > diff --git a/Maintainers.txt b/Maintainers.txt
> > index 56e16fc48cb4..a23dab394a61 100644
> > --- a/Maintainers.txt
> > +++ b/Maintainers.txt
> > @@ -310,3 +310,10 @@ F: Silicon/SiFive/
> > M: Abner Chang <abner.chang@hpe.com>
> > M: Gilbert Chen <gilbert.chen@hpe.com>
> > R: Daniel Schaefer <daniel.schaefer@hpe.com>
> > +
> > +Phytium platforms and silicon
> > +F: Platform/Phytium/
> > +F: Silicon/silicon/
> > +M: Peng Xie <xiepeng@phytium.com.cn>
> > +M: Ling Jia <jialing@phytium.com.cn>
>
> Can you change these to R: for now?
> We use M to indicate who has responsibility for actually getting the
> patches into the repo. So could you add me as M for now?
>
> /
> Leif
>
> > +R: Yiqi Shu <shuyiqi@phytium.com.cn>
> > diff --git a/Silicon/Phytium/Phytium.fdf.inc b/Silicon/Phytium/Phytium.fdf.inc
> > new file mode 100644
> > index 000000000000..641266c6012f
> > --- /dev/null
> > +++ b/Silicon/Phytium/Phytium.fdf.inc
> > @@ -0,0 +1,119 @@
> > +## @file
> > +# This package provides common open source Phytium silicon modules.
> > +#
> > +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
> > +#
> > +# SPDX-License-Identifier:BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +############################################################################
> > +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
> > +############################################################################
> > +#
> > +#[Rule.Common.DXE_DRIVER]
> > +# FILE DRIVER = $(NAMED_GUID) {
> > +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> > +# COMPRESS PI_STD {
> > +# GUIDED {
> > +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> > +# UI STRING="$(MODULE_NAME)" Optional
> > +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > +# }
> > +# }
> > +# }
> > +#
> > +############################################################################
> > +
> > +[Rule.Common.SEC]
> > + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
> > + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> > + }
> > +
> > +[Rule.Common.PEI_CORE]
> > + FILE PEI_CORE = $(NAMED_GUID) FIXED {
> > + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> > + UI STRING ="$(MODULE_NAME)" Optional
> > + }
> > +
> > +[Rule.Common.PEIM]
> > + FILE PEIM = $(NAMED_GUID) FIXED {
> > + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> > + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
> > + UI STRING="$(MODULE_NAME)" Optional
> > + }
> > +
> > +[Rule.Common.PEIM.TIANOCOMPRESSED]
> > + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
> > + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> > + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
> > + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> > + UI STRING="$(MODULE_NAME)" Optional
> > + }
> > + }
> > +
> > +[Rule.Common.DXE_CORE]
> > + FILE DXE_CORE = $(NAMED_GUID) {
> > + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> > + UI STRING="$(MODULE_NAME)" Optional
> > + }
> > +
> > +[Rule.Common.UEFI_DRIVER]
> > + FILE DRIVER = $(NAMED_GUID) {
> > + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> > + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> > + UI STRING="$(MODULE_NAME)" Optional
> > + }
> > +
> > +[Rule.Common.DXE_DRIVER]
> > + FILE DRIVER = $(NAMED_GUID) {
> > + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> > + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> > + UI STRING="$(MODULE_NAME)" Optional
> > + }
> > +
> > +[Rule.Common.DXE_RUNTIME_DRIVER]
> > + FILE DRIVER = $(NAMED_GUID) {
> > + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
> > + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> > + UI STRING="$(MODULE_NAME)" Optional
> > + }
> > +
> > +[Rule.Common.UEFI_APPLICATION]
> > + FILE APPLICATION = $(NAMED_GUID) {
> > + UI STRING ="$(MODULE_NAME)" Optional
> > + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> > + }
> > +
> > +[Rule.Common.UEFI_DRIVER.BINARY]
> > + FILE DRIVER = $(NAMED_GUID) {
> > + DXE_DEPEX DXE_DEPEX Optional |.depex
> > + PE32 PE32 |.efi
> > + UI STRING="$(MODULE_NAME)" Optional
> > + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > + }
> > +
> > +[Rule.Common.UEFI_APPLICATION.BINARY]
> > + FILE APPLICATION = $(NAMED_GUID) {
> > + PE32 PE32 |.efi
> > + UI STRING="$(MODULE_NAME)" Optional
> > + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > + }
> > +
> > +[Rule.Common.USER_DEFINED.BIOSINFO]
> > + FILE FREEFORM = $(NAMED_GUID) {
> > + RAW BIN Align = 16 $(INF_OUTPUT)/$(MODULE_NAME).acpi
> > + }
> > +
> > +[Rule.Common.UEFI_APPLICATION.UI]
> > + FILE APPLICATION = $(NAMED_GUID) {
> > + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> > + UI STRING="Enter Setup"
> > + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > + }
> > +
> > +[Rule.Common.USER_DEFINED.ACPITABLE]
> > + FILE FREEFORM = $(NAMED_GUID) {
> > + RAW ACPI |.acpi
> > + RAW ASL |.aml
> > + }
> > diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S
> > new file mode 100644
> > index 000000000000..cce23b786197
> > --- /dev/null
> > +++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S
> > @@ -0,0 +1,76 @@
> > +#
> > +# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
> > +#
> > +# This program and the accompanying materials
> > +# are licensed and made available under the terms and conditions of the BSD License
> > +# which accompanies this distribution. The full text of the license may be found at
> > +# http://opensource.org/licenses/bsd-license.php
> > +#
> > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> > +#
> > +#
> > +
> > +#include <AsmMacroIoLibV8.h>
> > +#include <Base.h>
> > +#include <Library/ArmLib.h>
> > +#include <Library/PcdLib.h>
> > +#include <AutoGen.h>
> > +
> > +.text
> > +.align 2
> > +
> > +GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
> > +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
> > +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
> > +GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
> > +
> > +PrimaryCoreMpid: .word 0x0
> > +
> > +
> > +ASM_PFX(ArmPlatformPeiBootAction):
> > + // Save MPIDR_EL1[23:0] in a variable.
> > + mov x20, x30
> > + bl ASM_PFX(ArmReadMpidr)
> > + lsl w0, w0, #8
> > + lsr w0, w0, #8
> > + ldr x1, =PrimaryCoreMpid
> > + str w0, [x1]
> > + ret x20
> > +
> > +//UINTN
> > +//ArmPlatformGetPrimaryCoreMpId (
> > +// VOID
> > +// );
> > +ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
> > + ldr x0, =PrimaryCoreMpid
> > + ldr w0, [x0]
> > + ret
> > +
> > +//UINTN
> > +//ArmPlatformIsPrimaryCore (
> > +// IN UINTN MpId
> > +// );
> > +ASM_PFX(ArmPlatformIsPrimaryCore):
> > + mov x20, x30
> > + bl ASM_PFX(ArmReadMpidr)
> > + lsl w0, w0, #8
> > + lsr w0, w0, #8
> > + ldr x1, =PrimaryCoreMpid
> > + ldr w1, [x1]
> > + cmp w0, w1
> > + cset x0, eq
> > + ret x20
> > +
> > +//UINTN
> > +//ArmPlatformGetCorePosition (
> > +// IN UINTN MpId
> > +// );
> > +// With this function: CorePos = (ClusterId * 4) + CoreId
> > +ASM_PFX(ArmPlatformGetCorePosition):
> > + and x1, x0, #ARM_CORE_MASK
> > + and x0, x0, #ARM_CLUSTER_MASK
> > + add x0, x1, x0, LSR #6
> > + ret
> > +
> > +ASM_FUNCTION_REMOVE_IF_UNREFERENCED
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v1 02/10] Silicon/Phytium: Added Acpi support to Phytium2000-4
2021-01-15 8:47 added support for DurianPkg Ling Jia
2021-01-15 8:47 ` [PATCH v1 01/10] Silicon/Phytium/: added PhytiumPlatformLib to Phytium2000-4 Ling Jia
@ 2021-01-15 8:47 ` Ling Jia
2021-01-15 8:47 ` [PATCH v1 03/10] Silicon/Phytium: Added SMBIOS " Ling Jia
` (9 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ling Jia @ 2021-01-15 8:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling, Peng Xie, Yiqi Shu
From: Ling <jialing@phytium.com.cn>
Added Acpi driver and table to Phytium2000-4,
the ACPI Tables providing library AcpiTables.inf uses
a lot of information that is available in the form of PCDs
for differnt platforms.
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Signed-off-by: Peng Xie <xiepeng@phytium.com.cn>
Reviewed-by: Yiqi Shu <shuyiqi@phytium.com.cn>
---
Platform/Phytium/Durian/DurianPkg.dsc | 7 +
Platform/Phytium/Durian/DurianPkg.fdf | 7 +
Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 58 +++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf | 61 +++++
Silicon/Phytium/Include/PhytiumPlatform.h | 93 +++++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 254 ++++++++++++++++++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiSsdtRootPci.asl | 234 ++++++++++++++++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dbg2.aslc | 85 +++++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Cpu.asl | 85 +++++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Dsdt.asl | 15 ++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Uart.asl | 65 +++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Fadt.aslc | 81 +++++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Gtdt.aslc | 87 +++++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Iort.aslc | 89 +++++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Madt.aslc | 66 +++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Mcfg.aslc | 69 ++++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Pptt.aslc | 219 +++++++++++++++++
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Spcr.aslc | 83 +++++++
18 files changed, 1658 insertions(+)
diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
index ef01cc217ace..45375383b22c 100644
--- a/Platform/Phytium/Durian/DurianPkg.dsc
+++ b/Platform/Phytium/Durian/DurianPkg.dsc
@@ -284,6 +284,13 @@ [Components.common]
#
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+ #
+ # ACPI Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf
+ Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
#
# Bds
#
diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Durian/DurianPkg.fdf
index f2f4cbc9ac7f..b4804c27aec4 100644
--- a/Platform/Phytium/Durian/DurianPkg.fdf
+++ b/Platform/Phytium/Durian/DurianPkg.fdf
@@ -109,6 +109,13 @@ [FV.FvMain]
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ #
+ # ACPI Support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF RuleOverride=ACPITABLE Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf
+ INF Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
#
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
new file mode 100644
index 000000000000..c1b1756f269f
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -0,0 +1,58 @@
+#/** @file
+# Sample ACPI Platform Driver.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = AcpiPlatform
+ FILE_GUID = d51068e8-40dc-11eb-9322-1f6d234e9e6e
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = AcpiPlatformEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ AcpiPlatform.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Phytium/Phytium.dec
+
+[LibraryClasses]
+ UefiLib
+ DxeServicesLib
+ PcdLib
+ BaseMemoryLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ HobLib
+
+[Guids]
+ gPhytiumPlatformPciHostInforGuid
+ gPhytiumPlatformCpuInforGuid
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile ## CONSUMES
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+[Depex]
+ gEfiAcpiTableProtocolGuid
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf
new file mode 100644
index 000000000000..677ac31d3acc
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf
@@ -0,0 +1,61 @@
+#/** @file
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = AcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt/Dsdt.asl
+ Spcr.aslc
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Mcfg.aslc
+ Iort.aslc
+ Pptt.aslc
+ AcpiSsdtRootPci.asl
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Phytium/Phytium.dec
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+ #
+ # PL011 UART Settings for Serial Port Console Redirection
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+
+ gArmPlatformTokenSpaceGuid.PcdWatchdogCount
diff --git a/Silicon/Phytium/Include/PhytiumPlatform.h b/Silicon/Phytium/Include/PhytiumPlatform.h
new file mode 100644
index 000000000000..495c5611eb15
--- /dev/null
+++ b/Silicon/Phytium/Include/PhytiumPlatform.h
@@ -0,0 +1,93 @@
+/** @file
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PHYTIUM_H__
+#define __PHYTIUM_H__
+#include <IndustryStandard/Acpi.h>
+
+#define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) \
+ { \
+ EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicITSHwId, GicITSBase, EFI_ACPI_RESERVED_DWORD \
+ }
+
+#define EFI_ACPI_5_1_GICR_STRUCTURE_INIT( \
+ GicRBase, GicRlength) \
+ { \
+ EFI_ACPI_5_1_GICR, sizeof (EFI_ACPI_5_1_GICR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicRBase, GicRlength \
+ }
+
+#define EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT( \
+ ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \
+ { \
+ 3, sizeof (EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE),ProximityDomain , \
+ ACPIProcessorUID, Flags, ClockDomain \
+ }
+
+#define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( \
+ ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags) \
+ { \
+ 1, sizeof (EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD, \
+ AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, EFI_ACPI_RESERVED_DWORD, Flags, \
+ EFI_ACPI_RESERVED_QWORD \
+ }
+
+#define EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr, Flags, PmuIrq, \
+ GicBase, GicVBase, GicHBase, GsivId, GicRBase, ProcessorPowerEfficiencyClass) \
+ { \
+ EFI_ACPI_6_1_GIC, sizeof (EFI_ACPI_6_1_GIC_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicId, AcpiCpuUid, Flags, 0, PmuIrq, 0, GicBase, GicVBase, GicHBase, \
+ GsivId, GicRBase, Mpidr, ProcessorPowerEfficiencyClass, {0, 0, 0} \
+ }
+
+#define EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(GicDistHwId, GicDistBase, GicDistVector, GicVersion) \
+ { \
+ EFI_ACPI_6_1_GICD, sizeof (EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+ GicDistHwId, GicDistBase, GicDistVector, GicVersion, \
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE} \
+ }
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_PHYTIUM_OEM_ID 'F','T','-','L','T','D' // OEMID 6 bytes long
+#define EFI_ACPI_PHYTIUM_OEM_TABLE_ID SIGNATURE_64('P','H','Y','T','I','U','M',' ') // OEM table id 8 bytes long
+#define EFI_ACPI_PHYTIUM_OEM_REVISION 0x20201111
+#define EFI_ACPI_PHYTIUM_CREATOR_ID SIGNATURE_32('P','H','Y','T')
+#define EFI_ACPI_PHYTIUM_CREATOR_REVISION 0x20201111
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define PHYTIUM_ACPI_HEADER(Signature, Type, Revision) { \
+ Signature, /* UINT32 Signature */ \
+ sizeof (Type), /* UINT32 Length */ \
+ Revision, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ { EFI_ACPI_PHYTIUM_OEM_ID }, /* UINT8 OemId[6] */ \
+ EFI_ACPI_PHYTIUM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ EFI_ACPI_PHYTIUM_OEM_REVISION, /* UINT32 OemRevision */ \
+ EFI_ACPI_PHYTIUM_CREATOR_ID, /* UINT32 CreatorId */ \
+ EFI_ACPI_PHYTIUM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[4];
+ EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_1_GIC_ITS_STRUCTURE GicITS[1];
+} EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+#endif
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatform.c b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatform.c
new file mode 100644
index 000000000000..b212585d694e
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatform.c
@@ -0,0 +1,254 @@
+/** @file
+ Sample ACPI Platform Driver.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+
+#include <Protocol/AcpiTable.h>
+#include <Protocol/FirmwareVolume2.h>
+
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiLib.h>
+#include <Library/HobLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <IndustryStandard/Acpi.h>
+
+/**
+ Locate the first instance of a protocol. If the protocol requested is an
+ FV protocol, then it will return the first FV that contains the ACPI table
+ storage file.
+
+ @param[out] Instance Return pointer to the first instance of the protocol.
+
+ @return EFI_SUCCESS The function completed successfully.
+
+ @return EFI_NOT_FOUND The protocol could not be located.
+
+ @return EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
+
+**/
+EFI_STATUS
+LocateFvInstanceWithTables (
+ OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN Index;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance;
+
+ FvStatus = 0;
+
+ //
+ // Locate protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Defined errors at this time are not found and out of resources.
+ //
+ return Status;
+ }
+
+ //
+ // Looking for FV with ACPI storage file
+ //
+
+ for (Index = 0; Index < NumberOfHandles; Index++) {
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID**) &FvInstance
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // See if it has the ACPI storage file
+ //
+ Status = FvInstance->ReadFile (
+ FvInstance,
+ (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ //
+ // If we found it, then we are done
+ //
+ if (Status == EFI_SUCCESS) {
+ *Instance = FvInstance;
+ break;
+ }
+ }
+
+ //
+ // Free any allocated buffers
+ //
+ gBS->FreePool (HandleBuffer);
+
+ return Status;
+}
+
+
+/**
+ This function calculates and updates an UINT8 checksum.
+
+ @param[in] Buffer Pointer to buffer to checksum.
+
+ @param[in] Size Number of bytes to checksum.
+
+**/
+VOID
+AcpiPlatformChecksum (
+ IN UINT8 *Buffer,
+ IN UINTN Size
+ )
+{
+ UINTN ChecksumOffset;
+
+ ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
+
+ //
+ // Set checksum to 0 first
+ //
+ Buffer[ChecksumOffset] = 0;
+
+ //
+ // Update checksum value
+ //
+ Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
+}
+
+
+/**
+ This function is the entrypoint of the acpi platform.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+AcpiPlatformEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ INTN Instance;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINTN TableHandle;
+ UINT32 FvStatus;
+ UINTN TableSize;
+ UINTN Size;
+
+ Instance = 0;
+ CurrentTable = NULL;
+ TableHandle = 0;
+
+ //
+ // Find the AcpiTable protocol
+ //
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
+ if (EFI_ERROR (Status)) {
+ return EFI_ABORTED;
+ }
+
+ //
+ // Locate the firmware volume protocol
+ //
+ Status = LocateFvInstanceWithTables (&FwVol);
+ if (EFI_ERROR (Status)) {
+ return EFI_ABORTED;
+ }
+ //
+ // Read tables from the storage file.
+ //
+ while (Status == EFI_SUCCESS) {
+
+ Status = FwVol->ReadSection (
+ FwVol,
+ (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID**) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+ if (!EFI_ERROR(Status)) {
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+
+ TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length;
+ ASSERT (Size >= TableSize);
+
+ //
+ // Checksum ACPI table
+ //
+ AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize);
+
+ //
+ // Install ACPI table
+ //
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ TableSize,
+ &TableHandle
+ );
+
+ //
+ // Free memory allocated by ReadSection
+ //
+ gBS->FreePool (CurrentTable);
+
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ CurrentTable = NULL;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiSsdtRootPci.asl
new file mode 100644
index 000000000000..0661f2c4f779
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiSsdtRootPci.asl
@@ -0,0 +1,234 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PhytiumPlatform.h>
+/*
+ See ACPI 6.1 Section 6.2.13
+
+ There are two ways that _PRT can be used. ...
+
+ In the first model, a PCI Link device is used to provide additional
+ configuration information such as whether the interrupt is Level or
+ Edge triggered, it is active High or Low, Shared or Exclusive, etc.
+
+ In the second model, the PCI interrupts are hardwired to specific
+ interrupt inputs on the interrupt controller and are not
+ configurable. In this case, the Source field in _PRT does not
+ reference a device, but instead contains the value zero, and the
+ Source Index field contains the global system interrupt to which the
+ PCI interrupt is hardwired.
+
+ We use the first model with link indirection to set the correct
+ interrupt type as PCI defaults (Level Triggered, Active Low) are not
+ compatible with GICv2.
+*/
+
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
+ Link, /* Interrupt allocated via Link device. */ \
+ Zero /* global system interrupt number (no used) */ \
+ }
+
+/*
+ See Reference [1] 6.1.1
+ "High word–Device #, Low word–Function #. (for example, device 3, function 2 is
+ 0x00030002). To refer to all the functions on a device #, use a function number of FFFF)."
+*/
+#define ROOT_PRT_ENTRY(Dev, Pin, Link) PRT_ENTRY(Dev * 0x10000 + 0xFFFF, Pin, Link)
+
+
+DefinitionBlock("SsdtPci.aml", "SSDT", 2, "FT-LTD", "PHYTIUM ", EFI_ACPI_PHYTIUM_OEM_REVISION) {
+ Scope(_SB) {
+ //
+ // PCI Root Complex
+ //
+ LNK_DEVICE(1, LNKA, 60)
+ LNK_DEVICE(2, LNKB, 61)
+ LNK_DEVICE(3, LNKC, 62)
+ LNK_DEVICE(4, LNKD, 63)
+
+ // reserve ECAM memory range
+ Device(RES0)
+ {
+ Name(_HID, EISAID("PNP0C02"))
+ Name(_UID, 0)
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0, // Granularity
+ 0x40000000, // Range Minimum
+ 0x4FFFFFFF, // Range Maximum
+ 0, // Translation Offset
+ 0x10000000, // Length
+ ,,)
+ })
+ }
+
+ Device(PCI0)
+ {
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, 0) // PCI Base Bus Number
+ Name(_CCA, 1) // Initially mark the PCI coherent (for JunoR1)
+
+ // Root Complex
+ Device (RP0) {
+ Name(_ADR, 0x00000000) // Dev 0, Func 0
+ }
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, 0, LNKA), // INTA
+ ROOT_PRT_ENTRY(0, 1, LNKB), // INTB
+ ROOT_PRT_ENTRY(0, 2, LNKC), // INTC
+ ROOT_PRT_ENTRY(0, 3, LNKD), // INTD
+
+ ROOT_PRT_ENTRY(1, 0, LNKA), // INTA
+ ROOT_PRT_ENTRY(1, 1, LNKB), // INTB
+ ROOT_PRT_ENTRY(1, 2, LNKC), // INTC
+ ROOT_PRT_ENTRY(1, 3, LNKD), // INTD
+
+ ROOT_PRT_ENTRY(2, 0, LNKA), // INTA
+ ROOT_PRT_ENTRY(2, 1, LNKB), // INTB
+ ROOT_PRT_ENTRY(2, 2, LNKC), // INTC
+ ROOT_PRT_ENTRY(2, 3, LNKD), // INTD
+
+ ROOT_PRT_ENTRY(3, 0, LNKA), // INTA
+ ROOT_PRT_ENTRY(3, 1, LNKB), // INTB
+ ROOT_PRT_ENTRY(3, 2, LNKC), // INTC
+ ROOT_PRT_ENTRY(3, 3, LNKD), // INTD
+
+ ROOT_PRT_ENTRY(4, 0, LNKA), // INTA
+ ROOT_PRT_ENTRY(4, 1, LNKB), // INTB
+ ROOT_PRT_ENTRY(4, 2, LNKC), // INTC
+ ROOT_PRT_ENTRY(4, 3, LNKD), // INTD
+
+ ROOT_PRT_ENTRY(5, 0, LNKA), // INTA
+ ROOT_PRT_ENTRY(5, 1, LNKB), // INTB
+ ROOT_PRT_ENTRY(5, 2, LNKC), // INTC
+ ROOT_PRT_ENTRY(5, 3, LNKD), // INTD
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber (
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x58000000, // Min Base Address
+ 0x7FFFFFFF, // Max Base Address
+ 0x00000000, // Translate
+ 0x28000000 // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x1000000000, // Min Base Address
+ 0x1FFFFFFFFF, // Max Base Address
+ 0x0000000000, // Translate
+ 0x1000000000 // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Min Base Address
+ 0x00efffff, // Max Base Address
+ 0x50000000, // Translate
+ 0x00f00000, // Length
+ ,,,TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ Return (RBUF)
+ } // Method(_CRS)
+
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ /*
+ See [1] 6.2.10, [2] 4.5
+ */
+ Method(_OSC,4) {
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+
+ // Only allow native hot plug control if OS supports:
+ // * ASPM
+ // * Clock PM
+ // * MSI/MSI-X
+ If(LNotEqual(And(SUPP, 0x16), 0x16)) {
+ And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
+ }
+
+ // Do not allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x10,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ }
+ }
+ }
+}
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dbg2.aslc b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dbg2.aslc
new file mode 100644
index 000000000000..ede0fe3c62c6
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dbg2.aslc
@@ -0,0 +1,85 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/DebugPort2Table.h>
+#include <PhytiumPlatform.h>
+
+#define NUMBER_DEBUG_DEVICE_INFO 1
+#define NUMBER_OF_GENERIC_ADDRESS 1
+#define NAMESPACE_STRING_SIZE 8
+
+#pragma pack(1)
+
+typedef struct {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader;
+ EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS];
+ UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS];
+ CHAR8 NamespaceString[NAMESPACE_STRING_SIZE];
+} EFI_ACPI_DBG2_DDI_STRUCT;
+
+typedef struct {
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc;
+ EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO];
+} EFI_ACPI_DEBUG_PORT_2_TABLE;
+
+#pragma pack()
+
+EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = {
+ {
+ PHYTIUM_ACPI_HEADER(
+ EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE,
+ EFI_ACPI_DEBUG_PORT_2_TABLE,
+ EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION
+ ),
+ OFFSET_OF(EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi),
+ NUMBER_DEBUG_DEVICE_INFO
+ },
+ {
+ {
+ {
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ sizeof(EFI_ACPI_DBG2_DDI_STRUCT),
+ NUMBER_OF_GENERIC_ADDRESS,
+ NAMESPACE_STRING_SIZE,
+ OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString),
+ 0,
+ 0,
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART,
+ {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
+ OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, Address),
+ OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, AddressSize),
+ },
+ {
+ {
+ EFI_ACPI_6_1_SYSTEM_MEMORY,
+ 32,
+ 0,
+ EFI_ACPI_6_1_DWORD,
+ FixedPcdGet64(PcdSerialRegisterBase)
+ }
+ },
+ {
+ 0x1000
+ },
+ "COM0"
+ }
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Dbg2;
+
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Cpu.asl b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Cpu.asl
new file mode 100644
index 000000000000..4a761149c508
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Cpu.asl
@@ -0,0 +1,85 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Scope(_SB)
+{
+ Device (CLU0) {
+ Name(_HID, "ACPI0010")
+ Name(_UID, 1)
+ Method (_STA, 0, NotSerialized) {
+ Return(0x0F)
+ }
+ Device(CPU0) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-name","c0"},
+ Package () {"clock-domain",0},
+ }
+ })
+ Method (_STA, 0, NotSerialized) {
+ Return(0x0F)
+ }
+ }
+
+ Device(CPU1) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-name","c0"},
+ Package () {"clock-domain",0},
+ }
+ })
+ Method (_STA, 0, NotSerialized) {
+ Return(0x0F)
+ }
+ }
+ }
+
+ Device (CLU1) {
+ Name(_HID, "ACPI0010")
+ Name(_UID, 2)
+ Method (_STA, 0, NotSerialized) {
+ Return(0x0F)
+ }
+ Device(CPU2) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-name","c1"},
+ Package () {"clock-domain",1},
+ }
+ })
+ Method (_STA, 0, NotSerialized) {
+ Return(0x0F)
+ }
+ }
+
+ Device(CPU3) {
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () {"clock-name","c1"},
+ Package () {"clock-domain",1},
+ }
+ })
+ Method (_STA, 0, NotSerialized) {
+ Return(0x0F)
+ }
+ }
+ }
+}
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Dsdt.asl b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Dsdt.asl
new file mode 100644
index 000000000000..01c48defa00f
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Dsdt.asl
@@ -0,0 +1,15 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PhytiumPlatform.h>
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "FT-LTD", "PHYTIUM ", EFI_ACPI_PHYTIUM_OEM_REVISION) {
+ include ("Cpu.asl")
+ include ("Uart.asl")
+}
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Uart.asl b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Uart.asl
new file mode 100644
index 000000000000..3e99c3c39f42
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Uart.asl
@@ -0,0 +1,65 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Scope(_SB)
+{
+ //UART 1
+ Device(UAR1) {
+ Name(_HID, "ARMH0011")
+ Name(_UID, 1)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x28001000, 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {39}
+ })
+
+ Method (_STA, 0, NotSerialized) { Return(0x0F) }
+ }
+
+ //UART 0
+ Device(UAR0) {
+ Name(_HID, "ARMH0011")
+ Name(_UID, 0)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x28000000, 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 38 }
+ })
+
+ Method (_STA, 0, NotSerialized) {
+ Return(0x0F)
+ }
+ }
+
+ //UART 2
+ Device(UAR2) {
+ Name(_HID, "ARMH0011")
+ Name(_UID, 2)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x28002000, 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {40}
+ })
+
+ Method (_STA, 0, NotSerialized) {
+ Return(0x0F)
+ }
+ }
+
+ //UART 3
+ Device(UAR3) {
+ Name(_HID, "ARMH0011")
+ Name(_UID, 3)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, 0x28003000, 0x1000)
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) {41}
+ })
+
+ Method (_STA, 0, NotSerialized) {
+ Return(0x0F)
+ }
+ }
+}
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Fadt.aslc b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Fadt.aslc
new file mode 100644
index 000000000000..275f057ebfba
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Fadt.aslc
@@ -0,0 +1,81 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <PhytiumPlatform.h>
+
+EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ PHYTIUM_ACPI_HEADER (
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ ),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_6_1_PM_PROFILE_ENTERPRISE_SERVER, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS, // EFI_ACPI_6_1__GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+ 0 // UINT64 Hypervisor Vendor Identify
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Gtdt.aslc b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Gtdt.aslc
new file mode 100644
index 000000000000..534a93e120ba
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Gtdt.aslc
@@ -0,0 +1,87 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <PhytiumPlatform.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
+#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL 0
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+#define GTDT_TIMER_ALWAYS_ON_CAPABILITY EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
+
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED | EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY)
+
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[2];
+} EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+ {
+ PHYTIUM_ACPI_HEADER(
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLES,
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ ),
+ 0xFFFFFFFFFFFFFFFF, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
+ 0xFFFFFFFFFFFFFFFF, // UINT64 CntReadBasePhysicalAddress
+ 2,
+ sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE)
+ },
+
+ {
+ {
+ 1, //Type
+ 28, //Size of this structure
+ 0, //reserved
+ 0x2800a000, //RefreshFrame Physical Address
+ 0x2800b000, //WatchdogControlFrame Physical Address
+ 48, //Watchdog Timer GSIV
+ 0, //Watchdog Timer Flags high level
+ },
+
+ {
+ 1,
+ 28,
+ 0,
+ 0x28016000,
+ 0x28017000,
+ 49,
+ 0,
+ }
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
+
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Iort.aslc b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Iort.aslc
new file mode 100644
index 000000000000..a684806e69f0
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Iort.aslc
@@ -0,0 +1,89 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/IoRemappingTable.h>
+#include <PhytiumPlatform.h>
+
+#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node;
+ UINT32 Identifiers[1];
+} PHYTIUM_ITS_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Node;
+ EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping;
+} PHYTIUM_RC_NODE;
+
+typedef struct {
+ EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort;
+ PHYTIUM_ITS_NODE ItsNode;
+ PHYTIUM_RC_NODE RcNode[1];
+} PHYTIUM_IO_REMAPPING_STRUCTURE;
+
+#define __PHYTIUM_ID_MAPPING(In, Num, Out, Ref, Flags) \
+ { \
+ In, \
+ Num, \
+ Out, \
+ FIELD_OFFSET(PHYTIUM_IO_REMAPPING_STRUCTURE, Ref), \
+ Flags \
+ }
+
+STATIC PHYTIUM_IO_REMAPPING_STRUCTURE Iort = {
+ {
+ PHYTIUM_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE,
+ PHYTIUM_IO_REMAPPING_STRUCTURE,
+ EFI_ACPI_IO_REMAPPING_TABLE_REVISION),
+ 2, // NumNodes
+ sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset
+ 0 // Reserved
+ }, {
+ // ItsNode
+ {
+ {
+ EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type
+ sizeof(PHYTIUM_ITS_NODE), // Length
+ 0x0, // Revision
+ 0x0, // Reserved
+ 0x0, // NumIdMappings
+ 0x0, // IdReference
+ },
+ 1,
+ }, {
+ 0x0
+ },
+ }, {
+ {
+ // PciRcNode
+ {
+ {
+ EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type
+ sizeof(PHYTIUM_RC_NODE), // Length
+ 0x0, // Revision
+ 0x0, // Reserved
+ 0x1, // NumIdMappings
+ FIELD_OFFSET(PHYTIUM_RC_NODE, RcIdMapping), // IdReference
+ },
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, // CacheCoherent
+ 0x0, // AllocationHints
+ 0x0, // Reserved
+ EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM, // MemoryAccessFlags
+ EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute
+ 0x0, // PciSegmentNumber
+ },
+ __PHYTIUM_ID_MAPPING(0x0, 0xffff, 0x0, ItsNode, 0),
+ }
+ }
+};
+#pragma pack()
+#
+VOID* CONST ReferenceAcpiTable = &Iort;
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Madt.aslc b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Madt.aslc
new file mode 100644
index 000000000000..53ff85e7cd52
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Madt.aslc
@@ -0,0 +1,66 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <PhytiumPlatform.h>
+
+
+// Differs from Juno, we have another affinity level beyond cluster and core
+// 0x20000 is only for socket 0
+#define PLATFORM_GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
+
+// Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
+// GsivId, GicRBase, Mpidr)
+// Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
+// ACPI v5.1).
+// The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
+// the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
+
+#define EFI_GICC_STRUCTURE(AcpiCpuUid, Mpidr, GicRBaseOffset) \
+ EFI_ACPI_6_1_GICC_STRUCTURE_INIT(0, AcpiCpuUid, Mpidr, EFI_ACPI_6_1_GIC_ENABLED, 23, \
+ FixedPcdGet64 (PcdGicInterruptInterfaceBase), FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x20000, \
+ FixedPcdGet64 (PcdGicInterruptInterfaceBase) + 0x10000, 25, FixedPcdGet64 (PcdGicRedistributorsBase) + GicRBaseOffset, 0)
+//
+// Multiple APIC Description Table
+//
+EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ PHYTIUM_ACPI_HEADER (
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ //
+ // MADT specific fields
+ //
+ 0, // LocalApicAddress
+ 0, // Flags
+ },
+ {
+ EFI_GICC_STRUCTURE(0x00, PLATFORM_GET_MPID(0x00, 0), 0x000000),
+ EFI_GICC_STRUCTURE(0x01, PLATFORM_GET_MPID(0x00, 1), 0x020000),
+ EFI_GICC_STRUCTURE(0x02, PLATFORM_GET_MPID(0x01, 0), 0x040000),
+ EFI_GICC_STRUCTURE(0x03, PLATFORM_GET_MPID(0x01, 1), 0x060000),
+ },
+
+ EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0, 0x3),
+ {
+ EFI_ACPI_6_1_GIC_ITS_INIT(0, FixedPcdGet64(PcdGicDistributorBase) + 0x20000),
+ }
+};
+
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Mcfg.aslc b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Mcfg.aslc
new file mode 100644
index 000000000000..9eb89062ffb1
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Mcfg.aslc
@@ -0,0 +1,69 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <PhytiumPlatform.h>
+
+#define ACPI_6_1_MCFG_VERSION 0x1
+
+#pragma pack(1)
+typedef struct
+{
+ UINT64 ullBaseAddress;
+ UINT16 usSegGroupNum;
+ UINT8 ucStartBusNum;
+ UINT8 ucEndBusNum;
+ UINT32 Reserved2;
+}EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE;
+
+typedef struct
+{
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 Reserved1;
+}EFI_ACPI_6_1_MCFG_TABLE_CONFIG;
+
+typedef struct
+{
+ EFI_ACPI_6_1_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
+ EFI_ACPI_6_1_MCFG_CONFIG_STRUCTURE Config_Structure[1];
+}EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
+#pragma pack()
+
+EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
+{
+ {
+ {
+ EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
+ ACPI_6_1_MCFG_VERSION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_PHYTIUM_OEM_ID},
+ EFI_ACPI_PHYTIUM_OEM_TABLE_ID,
+ EFI_ACPI_PHYTIUM_OEM_REVISION,
+ EFI_ACPI_PHYTIUM_CREATOR_ID,
+ EFI_ACPI_PHYTIUM_CREATOR_REVISION
+ },
+ 0x0000000000000000, //Reserved
+ },
+ {
+ {
+ 0x40000000, //Base Address
+ 0, //Segment Group Number
+ 0, //Start Bus Number
+ 0xff, //End Bus Number
+ 0x00000000, //Reserved
+ },
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Pptt.aslc b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Pptt.aslc
new file mode 100644
index 000000000000..cc5d82b5585b
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Pptt.aslc
@@ -0,0 +1,219 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <PhytiumPlatform.h>
+
+#define FIELD_OFFSET(type, name) __builtin_offsetof(type, name)
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 Offset[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE ICache;
+} PHYTIUM_PPTT_CORE;
+
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 Offset[1];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L2Cache;
+ PHYTIUM_PPTT_CORE Cores[2];
+} PHYTIUM_PPTT_CLUSTER;
+
+typedef struct {
+ EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset[1];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE L3Cache;
+ PHYTIUM_PPTT_CLUSTER Clusters[2];
+ EFI_ACPI_6_2_PPTT_STRUCTURE_ID ID;
+} PHYTIUM_PPTT_PACKAGE;
+
+typedef struct {
+ EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Pptt;
+ PHYTIUM_PPTT_PACKAGE Packages[1];
+} PHYTIUM_PPTT_TABLE;
+#pragma pack()
+
+#define PPTT_CORE(pid, cid, id) { \
+ { \
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \
+ FIELD_OFFSET (PHYTIUM_PPTT_CORE, DCache), \
+ {}, \
+ { \
+ 0, /* PhysicalPackage */ \
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorIdValid */ \
+ }, \
+ FIELD_OFFSET (PHYTIUM_PPTT_TABLE, \
+ Packages[pid].Clusters[cid]), /* Parent */ \
+ 8 * (pid) + 4 * (cid) + (id), /* AcpiProcessorId */ \
+ 2, /* NumberOfPrivateResources */\
+ }, { \
+ FIELD_OFFSET (PHYTIUM_PPTT_TABLE, \
+ Packages[pid].Clusters[cid].Cores[id].DCache), \
+ FIELD_OFFSET (PHYTIUM_PPTT_TABLE, \
+ Packages[pid].Clusters[cid].Cores[id].ICache), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_32KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 2, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 0, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_32KB, /* Size */ \
+ 256, /* NumberOfSets */ \
+ 2, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ, /* AllocationType */ \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ 0, /* WritePolicy */ \
+ }, \
+ 64 /* LineSize */ \
+ } \
+}
+
+#define PPTT_CLUSTER(pid, cid) { \
+ { \
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \
+ FIELD_OFFSET (PHYTIUM_PPTT_CLUSTER, L2Cache), \
+ {}, \
+ { \
+ 0, /* PhysicalPackage */ \
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
+ }, \
+ FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid]), /* Parent */ \
+ 0, /* AcpiProcessorId */ \
+ 1, /* NumberOfPrivateResources */ \
+ }, { \
+ FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid].Clusters[cid].L2Cache), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 1, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* NumberOfSets */ \
+ 16, /* Associativity */ \
+ { \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }, { \
+ PPTT_CORE(pid, cid, 0), \
+ PPTT_CORE(pid, cid, 1), \
+ } \
+}
+
+#define PPTT_PANEL(pid) { \
+ { \
+ EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR, \
+ FIELD_OFFSET (PHYTIUM_PPTT_PACKAGE, L3Cache), \
+ {}, \
+ { \
+ 1, /* PhysicalPackage */ \
+ EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
+ }, \
+ 0, /* Parent */ \
+ 0, /* AcpiProcessorId */ \
+ 1, /* NumberOfPrivateResources */ \
+ }, { \
+ FIELD_OFFSET (PHYTIUM_PPTT_TABLE, Packages[pid].L3Cache), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE), \
+ {}, \
+ { \
+ 1, /* SizePropertyValid */ \
+ 1, /* NumberOfSetsValid */ \
+ 1, /* AssociativityValid */ \
+ 0, /* AllocationTypeValid */ \
+ 1, /* CacheTypeValid */ \
+ 1, /* WritePolicyValid */ \
+ 1, /* LineSizeValid */ \
+ }, \
+ 0, /* NextLevelOfCache */ \
+ SIZE_4MB, /* Size */ \
+ 4096, /* NumberOfSets */ \
+ 16, /* Associativity */ \
+ { \
+ 0, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ }, \
+ 64 /* LineSize */ \
+ }, { \
+ PPTT_CLUSTER (pid, 0), \
+ PPTT_CLUSTER (pid, 1), \
+ }, { \
+ EFI_ACPI_6_2_PPTT_TYPE_ID, \
+ sizeof(EFI_ACPI_6_2_PPTT_STRUCTURE_ID), \
+ {0}, \
+ 0x54594850, \
+ 0x3, \
+ 0x1, \
+ 0, \
+ 0, \
+ 0, \
+ } \
+}
+
+
+STATIC PHYTIUM_PPTT_TABLE mPhytiumPpttTable = {
+ {
+ PHYTIUM_ACPI_HEADER(EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ PHYTIUM_PPTT_TABLE,
+ EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION),
+ },
+ {
+ PPTT_PANEL(0)
+ }
+};
+
+VOID * CONST ReferenceAcpiTable = &mPhytiumPpttTable;
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Spcr.aslc b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Spcr.aslc
new file mode 100644
index 000000000000..114ec9933738
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Spcr.aslc
@@ -0,0 +1,83 @@
+/** @file
+ Phytium ACPI ASL Sources.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <PhytiumPlatform.h>
+
+/**
+ * References:
+ * Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015
+ **/
+
+
+///
+/// SPCR Flow Control
+///
+#define SPCR_FLOW_CONTROL_NONE 0
+
+
+STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
+ PHYTIUM_ACPI_HEADER (EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
+ // UINT8 InterfaceType;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
+ // UINT8 Reserved1[3];
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
+ ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)),
+ // UINT8 InterruptType;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
+ // UINT8 Irq;
+ 0, // Not used on ARM
+ // UINT32 GlobalSystemInterrupt;
+ FixedPcdGet32 (PL011UartInterrupt),
+ // UINT8 BaudRate;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
+ // UINT8 Parity;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
+ // UINT8 StopBits;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
+ // UINT8 FlowControl;
+ SPCR_FLOW_CONTROL_NONE,
+ // UINT8 TerminalType;
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
+ // UINT8 Reserved2;
+ EFI_ACPI_RESERVED_BYTE,
+ // UINT16 PciDeviceId;
+ 0xFFFF,
+ // UINT16 PciVendorId;
+ 0xFFFF,
+ // UINT8 PciBusNumber;
+ 0x00,
+ // UINT8 PciDeviceNumber;
+ 0x00,
+ // UINT8 PciFunctionNumber;
+ 0x00,
+ // UINT32 PciFlags;
+ 0x00000000,
+ // UINT8 PciSegment;
+ 0x00,
+ // UINT32 Reserved3;
+ EFI_ACPI_RESERVED_DWORD
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Spcr;
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v1 03/10] Silicon/Phytium: Added SMBIOS support to Phytium2000-4
2021-01-15 8:47 added support for DurianPkg Ling Jia
2021-01-15 8:47 ` [PATCH v1 01/10] Silicon/Phytium/: added PhytiumPlatformLib to Phytium2000-4 Ling Jia
2021-01-15 8:47 ` [PATCH v1 02/10] Silicon/Phytium: Added Acpi support " Ling Jia
@ 2021-01-15 8:47 ` Ling Jia
2021-01-15 8:47 ` [PATCH v1 04/10] Silicon/Phytium/Phytium2000-4/Library: Added PciSegmentLib " Ling Jia
` (8 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ling Jia @ 2021-01-15 8:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling, Peng Xie, Yiqi Shu
From: Ling <jialing@phytium.com.cn>
This driver installs SMBIOS information for Phytium2000-4.
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Signed-off-by: Peng Xie <xiepeng@phytium.com.cn>
Reviewed-by: Yiqi Shu <shuyiqi@phytium.com.cn>
---
Platform/Phytium/Durian/DurianPkg.dsc | 6 +
Platform/Phytium/Durian/DurianPkg.fdf | 6 +
Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 55 ++
Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 959 ++++++++++++++++++++
4 files changed, 1026 insertions(+)
diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
index 45375383b22c..f260bab450f3 100644
--- a/Platform/Phytium/Durian/DurianPkg.dsc
+++ b/Platform/Phytium/Durian/DurianPkg.dsc
@@ -291,6 +291,12 @@ [Components.common]
Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf
Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ #
+ # SMBIOS
+ #
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+
#
# Bds
#
diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Durian/DurianPkg.fdf
index b4804c27aec4..98d3e07999ee 100644
--- a/Platform/Phytium/Durian/DurianPkg.fdf
+++ b/Platform/Phytium/Durian/DurianPkg.fdf
@@ -167,6 +167,12 @@ [FV.FvMain]
#
INF ShellPkg/Application/Shell/Shell.inf
+ #
+ # SMBIOS/DMI
+ #
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+
#
# Bds
#
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf b/Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
new file mode 100644
index 000000000000..0935c9e72e72
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
@@ -0,0 +1,55 @@
+#/** @file
+# This driver installs SMBIOS information for Phytium.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = SmbiosPlatformDxe
+ FILE_GUID = d64f09f8-40dc-11eb-9be6-f7a038f956ba
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SmbiosTablePublishEntry
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+[Sources]
+ SmbiosPlatformDxe.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Silicon/Phytium/Phytium.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ HobLib
+ IoLib
+ MemoryAllocationLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Guids]
+ gEfiGlobalVariableGuid
+
+[Protocols]
+ gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+
+[Guids]
+ gPhytiumPlatformMemoryInforGuid
+
+[Depex]
+ gEfiSmbiosProtocolGuid
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c b/Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
new file mode 100644
index 000000000000..5be37e02e061
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
@@ -0,0 +1,959 @@
+/** @file
+ This driver installs SMBIOS information for Phytium Durian platforms.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PhytiumPlatform.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Protocol/Smbios.h>
+
+
+// SMBIOS tables often reference each other using
+// fixed constants, define a list of these constants
+// for our hardcoded tables
+
+#define TYPE0_STRINGS \
+ "PHYTIUM LTD\0" /* Vendor */ \
+ "V1.0\0" /* BiosVersion */ \
+ __DATE__"\0" /* BiosReleaseDate */
+
+#define TYPE1_STRINGS \
+ "PHYTIUM LTD\0" /* Manufacturer */ \
+ "Phytium Durian Development Platform\0" /* Product Name */ \
+ "None\0" /* Version */ \
+ "Not Set\0" /* SerialNumber */ \
+ "Not set\0" /* SKUNumber */ \
+ "FT-2000/4\0" /* Family */ \
+
+#define TYPE2_STRINGS \
+ "PHYTIUM LTD\0" /* Manufacturer */ \
+ "Phytium Durian Development Platform\0" /* Product Name */ \
+ "None\0" /* Version */ \
+ "Not Set\0" /* Serial */ \
+ "Not Set\0" /* BaseBoardAssetTag */ \
+ "Not Set\0" /* BaseBoardChassisLocation */
+
+#define TYPE3_STRINGS \
+ "PHYTIUM LTD\0" /* Manufacturer */ \
+ "None\0" /* Version */ \
+ "Not Set\0" /* Serial */ \
+ "Not Set\0" /* AssetTag */
+
+#if 1
+#define TYPE4_STRINGS \
+ "FT-2000/4\0" /* socket type */ \
+ "PHYTIUM LTD\0" /* manufactuer */ \
+ "FT-2000/4\0" /* processor version */ \
+ "Not Set\0" /* SerialNumber */ \
+ "Not Set\0" /* processor 2 description */ \
+ "Not Set\0" /* AssetTag */
+#endif
+
+#if 0
+#define TYPE4_STRINGS \
+ "FT-2000/4\0" /* socket type */ \
+ "PHYTIUM LTD\0" /* manufactuer */ \
+ "FT-2000/4\0" /* processor version */ \
+ "Not Set\0" /* SerialNumber */ \
+ "Not Set\0" /* processor 2 description */ \
+ "Not Set\0" /* AssetTag */
+#endif
+
+#define TYPE7_STRINGS \
+ "L1 Instruction\0" /* L1I */ \
+ "L1 Data\0" /* L1D */ \
+ "L2\0" /* L2 */
+
+#define TYPE7_L1DATA_STRINGS \
+ "L1 Data Cache\0" /* L1 data */
+
+
+#define TYPE7_L1INS_STRINGS \
+ "L1 Instruction Cache\0" /* L1 ins */
+
+#define TYPE7_L2_STRINGS \
+ "L2 Cache\0" /* L2 */
+
+#define TYPE7_L3_STRINGS \
+ "L3 Cache\0" /* L3 */
+
+
+#define TYPE9_STRINGS \
+ "PCIE_SLOT0\0" /* Slot0 */ \
+ "PCIE_SLOT1\0" /* Slot1 */ \
+ "PCIE_SLOT2\0" /* Slot2 */ \
+ "PCIE_SLOT3\0" /* Slot3 */
+
+#define TYPE9_STRINGS_PCIE0X16 \
+ "PCIE0_X16\0"
+
+#define TYPE9_STRINGS_PCIE0X1 \
+ "PCIE0_X1\0"
+
+#define TYPE9_STRINGS_PCIE1X16 \
+ "PCIE1_X16\0"
+
+#define TYPE9_STRINGS_PCIE1X1 \
+ "PCIE1_X1\0"
+
+#define TYPE13_STRINGS \
+ "en|US|iso8859-1\0" \
+ "zh|CN|unicode\0"
+
+
+#define TYPE16_STRINGS \
+ "\0" /* nothing */
+
+#define TYPE17_STRINGS_CHANNEL0 \
+ "SOCKET 0 CHANNEL 0 DIMM 0\0" /* location */ \
+ "Bank0\0" /* bank description */ \
+ "Not Set\0" \
+ "Not Set\0" \
+ "Not Set\0" \
+ "Not Set\0"
+
+#define TYPE17_STRINGS_CHANNEL1 \
+ "SOCKET 0 CHANNEL 1 DIMM 0\0" /* location */ \
+ "Bank0\0" \
+ "Not Set\0" \
+ "Not Set\0" \
+ "Not Set\0" \
+ "Not Set\0"
+
+
+#define TYPE19_STRINGS \
+ "\0" /* nothing */
+
+#define TYPE32_STRINGS \
+ "\0" /* nothing */
+
+#define TYPE39_STRINGS \
+ "Not specified\0" /* not specified*/ \
+ "Not specified\0" /* not specified*/ \
+ "Not specified\0" /* not specified*/ \
+ "Not specified\0" /* not specified*/ \
+ "Not specified\0" /* not specified*/ \
+ "Not specified\0" /* not specified*/ \
+ "Not specified\0" /* not specified*/
+
+#define TYPE38_STRINGS \
+ "\0"
+
+//
+// Type definition and contents of the default SMBIOS table.
+// This table covers only the minimum structures required by
+// the SMBIOS specification (section 6.2, version 3.0)
+//
+#pragma pack(1)
+typedef struct {
+ SMBIOS_TABLE_TYPE0 Base;
+ INT8 Strings[sizeof(TYPE0_STRINGS)];
+} ARM_TYPE0;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE1 Base;
+ UINT8 Strings[sizeof(TYPE1_STRINGS)];
+} ARM_TYPE1;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE2 Base;
+ UINT8 Strings[sizeof(TYPE2_STRINGS)];
+} ARM_TYPE2;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE3 Base;
+ UINT8 Strings[sizeof(TYPE3_STRINGS)];
+} ARM_TYPE3;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE4 Base;
+ UINT8 Strings[sizeof(TYPE4_STRINGS)];
+} ARM_TYPE4;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE7 Base;
+ UINT8 Strings[sizeof(TYPE7_L1DATA_STRINGS)];
+} ARM_TYPE7_L1DATA;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE7 Base;
+ UINT8 Strings[sizeof(TYPE7_L1INS_STRINGS)];
+} ARM_TYPE7_L1INS;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE7 Base;
+ UINT8 Strings[sizeof(TYPE7_L2_STRINGS)];
+} ARM_TYPE7_L2;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE7 Base;
+ UINT8 Strings[sizeof(TYPE7_L3_STRINGS)];
+} ARM_TYPE7_L3;
+
+
+typedef struct {
+ SMBIOS_TABLE_TYPE9 Base;
+ UINT8 Strings[sizeof(TYPE9_STRINGS)];
+} ARM_TYPE9;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE9 Base;
+ UINT8 Strings[sizeof(TYPE9_STRINGS_PCIE0X16)];
+} ARM_TYPE9_PCIE0X16;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE9 Base;
+ UINT8 Strings[sizeof(TYPE9_STRINGS_PCIE0X1)];
+} ARM_TYPE9_PCIE0X1;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE9 Base;
+ UINT8 Strings[sizeof(TYPE9_STRINGS_PCIE1X16)];
+} ARM_TYPE9_PCIE1X16;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE9 Base;
+ UINT8 Strings[sizeof(TYPE9_STRINGS_PCIE1X1)];
+} ARM_TYPE9_PCIE1X1;
+
+
+typedef struct {
+ SMBIOS_TABLE_TYPE13 Base;
+ UINT8 Strings[sizeof(TYPE13_STRINGS)];
+} ARM_TYPE13;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE16 Base;
+ UINT8 Strings[sizeof(TYPE16_STRINGS)];
+} ARM_TYPE16;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE17 Base;
+ UINT8 Strings[sizeof(TYPE17_STRINGS_CHANNEL0)];
+} ARM_TYPE17_CHANNEL0;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE17 Base;
+ UINT8 Strings[sizeof(TYPE17_STRINGS_CHANNEL1)];
+} ARM_TYPE17_CHANNEL1;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE19 Base;
+ UINT8 Strings[sizeof(TYPE19_STRINGS)];
+} ARM_TYPE19;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE32 Base;
+ UINT8 Strings[sizeof(TYPE32_STRINGS)];
+} ARM_TYPE32;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE38 Base;
+ UINT8 Strings[sizeof(TYPE38_STRINGS)];
+} ARM_TYPE38;
+
+typedef struct {
+ SMBIOS_TABLE_TYPE39 Base;
+ UINT8 Strings[sizeof(TYPE39_STRINGS)];
+} ARM_TYPE39;
+
+enum SMBIOS_REFRENCE_HANDLES {
+ SMBIOS_HANDLE_L1I = 0x1000,
+ SMBIOS_HANDLE_L1D,
+ SMBIOS_HANDLE_L2,
+ SMBIOS_HANDLE_L3,
+ SMBIOS_HANDLE_MOTHERBOARD,
+ SMBIOS_HANDLE_CHASSIS,
+ SMBIOS_HANDLE_CLUSTER,
+ SMBIOS_HANDLE_MEMORY,
+ SMBIOS_HANDLE_DIMM_0,
+ SMBIOS_HANDLE_DIMM_1
+};
+
+#define SERIAL_LEN 10 //this must be less than the buffer len allocated in the type1 structure
+
+#pragma pack()
+
+//BIOS Information (Type 0)
+ARM_TYPE0 BiosInfo_Type0 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_BIOS_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE0), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 1, //Vendor
+ 2, //BiosVersion
+ 0x8800, //BiosSegment
+ 3, //BiosReleaseDate
+ 0xFF, //BiosSize
+ { //BiosCharacteristics
+ 0, // Reserved :2
+ 0, // Unknown :1
+ 0, // BiosCharacteristicsNotSupported :1
+ 0, // IsaIsSupported :1
+ 0, // McaIsSupported :1
+ 0, // EisaIsSupported :1
+ 1, // PciIsSupported :1
+ 0, // PcmciaIsSupported :1
+ 0, // PlugAndPlayIsSupported :1
+ 0, // ApmIsSupported :1
+ 1, // BiosIsUpgradable :1
+ 0, // BiosShadowingAllowed :1
+ 0, // VlVesaIsSupported :1
+ 0, // EscdSupportIsAvailable :1
+ 1, // BootFromCdIsSupported :1
+ 1, // SelectableBootIsSupported :1
+ 0, // RomBiosIsSocketed :1
+ 0, // BootFromPcmciaIsSupported :1
+ 0, // EDDSpecificationIsSupported :1
+ 0, // JapaneseNecFloppyIsSupported :1
+ 0, // JapaneseToshibaFloppyIsSupported :1
+ 0, // Floppy525_360IsSupported :1
+ 0, // Floppy525_12IsSupported :1
+ 0, // Floppy35_720IsSupported :1
+ 0, // Floppy35_288IsSupported :1
+ 0, // PrintScreenIsSupported :1
+ 0, // Keyboard8042IsSupported :1
+ 0, // SerialIsSupported :1
+ 0, // PrinterIsSupported :1
+ 0, // CgaMonoIsSupported :1
+ 0, // NecPc98 :1
+ 0 // ReservedForVendor :3
+ },
+ {
+ 0x03, //BIOSCharacteristicsExtensionBytes[0]
+ 0x0D //BIOSCharacteristicsExtensionBytes[1]
+ },
+ 0xFF, //SystemBiosMajorRelease;
+ 0xFF, //SystemBiosMinorRelease;
+ 0xFF, //EmbeddedControllerFirmwareMajorRelease;
+ 0xFF, //EmbeddedControllerFirmwareMinorRelease;
+ },
+ TYPE0_STRINGS
+};
+
+//System Information (Type 1).
+ARM_TYPE1 SystemInfo_Type1 = {
+ {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type,
+ sizeof (SMBIOS_TABLE_TYPE1), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED // Handle
+ },
+ 1, // Manufacturer
+ 2, // ProductName
+ 3, // Version
+ 4, // SerialNumber
+ { // Uuid
+ 0x12345678, 0x1234, 0x5678, {0x90, 0xab, 0xcd, 0xde, 0xef, 0xaa, 0xbb, 0xcc}
+ },
+ SystemWakeupTypePowerSwitch, // SystemWakeupType
+ 5, // SKUNumber,
+ 6 // Family
+ },
+ TYPE1_STRINGS
+};
+
+//Base Board (or Module) Information (Type 2)
+ARM_TYPE2 BaseboardInfo_Type2 = {
+ {
+ { // Hdr
+ EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // Type,
+ sizeof (SMBIOS_TABLE_TYPE2), // UINT8 Length
+ SMBIOS_HANDLE_MOTHERBOARD // Handle
+ },
+ 1, // BaseBoardManufacturer
+ 2, // BaseBoardProductName
+ 3, // BaseBoardVersion
+ 4, // BaseBoardSerialNumber
+ 5, // BaseBoardAssetTag
+ { // FeatureFlag
+ 1, // Motherboard :1
+ 0, // RequiresDaughterCard :1
+ 0, // Removable :1
+ 1, // Replaceable :1
+ 0, // HotSwappable :1
+ 0 // Reserved :3
+ },
+ 6, // BaseBoardChassisLocation
+ 0, // ChassisHandle;
+ BaseBoardTypeMotherBoard, // BoardType;
+ 0, // NumberOfContainedObjectHandles;
+ {
+ 0
+ } // ContainedObjectHandles[1];
+ },
+ TYPE2_STRINGS
+};
+
+//System Enclosure or Chassis (Type 3)
+ARM_TYPE3 SystemEnclosure_Type3 = {
+ {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE , // Type,
+ sizeof (SMBIOS_TABLE_TYPE3), // UINT8 Length
+ SMBIOS_HANDLE_CHASSIS // Handle
+ },
+ 1, // Manufactrurer
+ MiscChassisTypeMainServerChassis, // Type
+ 2, // Version
+ 3, // SerialNumber
+ 4, // AssetTag
+ ChassisStateSafe, // BootupState
+ ChassisStateSafe, // PowerSupplyState
+ ChassisStateSafe, // ThermalState
+ ChassisSecurityStatusNone, // SecurityState
+ {
+ 0, // OemDefined[0]
+ 0, // OemDefined[1]
+ 0, // OemDefined[2]
+ 0 // OemDefined[3]
+ },
+ 2, // Height
+ 1, // NumberofPowerCords
+ 0, // ContainedElementCount
+ 0, // ContainedElementRecordLength
+ { // ContainedElements[0]
+ {
+ 0, // ContainedElementType
+ 0, // ContainedElementMinimum
+ 0 // ContainedElementMaximum
+ }
+ }
+ },
+ TYPE3_STRINGS
+};
+
+//Processor Infomation (Type 4)
+ARM_TYPE4 ProcessorInfo_Type4 = {
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, //Type
+ sizeof(SMBIOS_TABLE_TYPE4), //Length
+ SMBIOS_HANDLE_CLUSTER //Handle
+ },
+ 1, //Socket
+ CentralProcessor, //ProcessorType
+ ProcessorFamilyIndicatorFamily2, //ProcessorFamily
+ 2, //ProcessorManufacture
+ { //ProcessorId
+ { //Signature
+ 0
+ },
+ { //FeatureFlags
+ 0
+ }
+ },
+ 3, //ProcessorVersion
+ { //Voltage
+ 0, 0, 0, 1, 0, 1
+ },
+ 1, //ExternalClock
+ 1, //MaxSpeed
+ 0, //CurrentSpeed
+ 0x41, //Status
+ ProcessorUpgradeUnknown, //ProcessorUpgrade
+ SMBIOS_HANDLE_L1D, //L1Ins
+ SMBIOS_HANDLE_L2, //L1Data
+ SMBIOS_HANDLE_L3, //L2
+ 4, //SerialNumber
+ 5, //AssetTag
+ 6, //PartNumber
+
+ 4, //CoreCount
+ 0, //EnabledCoreCount
+ 0, //ThreadCount
+ 0x00EC, //ProcessorCharacteristics
+
+ ProcessorFamilyARMv8, //ProcessorFamily2
+
+ 0, //CoreCount2
+ 0, //EnabledCoreCount2
+ 0 //ThreadCount2
+ },
+ TYPE4_STRINGS
+};
+
+//Cache Information (Type7) L1 DATA
+ARM_TYPE7_L1DATA L1Data_Type7 = {
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type
+ sizeof(SMBIOS_TABLE_TYPE7), //Length
+ SMBIOS_HANDLE_L1D //Handle
+ },
+ 1, //SocketDesignation
+ 0x0180, //CacheConfiguration
+ 0, //MaximumCacheSize
+ 0, //InstalledSize
+ { //SupportedSRAMType
+ 0,0,0,0,0,1,0,0
+ },
+ { //CurrentSRAMType
+ 0,0,0,0,0,1,0,0
+ },
+ 0, //CacheSpeed
+ CacheErrorSingleBit, //ErrorCorrectionType
+ CacheTypeData, //SystemCacheType
+ CacheAssociativity8Way, //Associativity
+ 128,
+ 128
+ },
+ TYPE7_L1DATA_STRINGS
+};
+
+//Cache Information (Type7) L1 INS
+ARM_TYPE7_L1INS L1Ins_Type7 = {
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type
+ sizeof(SMBIOS_TABLE_TYPE7), //Length
+ SMBIOS_HANDLE_L1I //Handle
+ },
+ 1, //SocketDesignation
+ 0x0180, //CacheConfiguration
+ 0, //MaximumCacheSize
+ 0, //InstalledSize
+ { //SupportedSRAMType
+ 0,0,0,0,0,1,0,0
+ },
+ { //CurrentSRAMType
+ 0,0,0,0,0,1,0,0
+ },
+ 0, //CacheSpeed
+ CacheErrorParity, //ErrorCorrectionType
+ CacheTypeInstruction, //SystemCacheType
+ CacheAssociativity8Way, //Associativity
+ 128,
+ 128
+ },
+ TYPE7_L1INS_STRINGS
+};
+
+//Cache Information (Type7) L2
+ARM_TYPE7_L2 L2_Type7 = {
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type
+ sizeof(SMBIOS_TABLE_TYPE7), //Length
+ SMBIOS_HANDLE_L2 //Handle
+ },
+ 1, //SocketDesignation
+ 0x0281, //CacheConfiguration
+ 0, //MaximumCacheSize
+ 0, //InstalledSize
+ { //SupportedSRAMType
+ 0,0,0,0,0,1,0,0
+ },
+ { //CurrentSRAMType
+ 0,0,0,0,0,1,0,0
+ },
+ 0, //CacheSpeed
+ CacheErrorSingleBit, //ErrorCorrectionType
+ CacheTypeUnified, //SystemCacheType
+ CacheAssociativity8Way, //Associativity
+ 4096,
+ 4096
+ },
+ TYPE7_L2_STRINGS
+};
+
+//Cache Information (Type7) L3
+ARM_TYPE7_L3 L3_Type7 = {
+ {
+ { //Header
+ EFI_SMBIOS_TYPE_CACHE_INFORMATION, //Type
+ sizeof(SMBIOS_TABLE_TYPE7), //Length
+ SMBIOS_HANDLE_L3 //Handle
+ },
+ 1, //SocketDesignation
+ 0x0281, //CacheConfiguration
+ 0, //MaximumCacheSize
+ 0, //InstalledSize
+ { //SupportedSRAMType
+ 0,0,0,0,0,1,0,0
+ },
+ { //CurrentSRAMType
+ 0,0,0,0,0,1,0,0
+ },
+ 0, //CacheSpeed
+ CacheErrorSingleBit, //ErrorCorrectionType
+ CacheTypeUnified, //SystemCacheType
+ CacheAssociativity8Way, //Associativity
+ 4096,
+ 4096
+ },
+ TYPE7_L3_STRINGS
+};
+
+//PCIE0_X16 (Type 9)
+ARM_TYPE9_PCIE0X16 Pcie0X16_Type9 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 1,
+ SlotTypePciX,
+ SlotDataBusWidth16X,
+ SlotUsageInUse,
+ SlotLengthLong,
+ 0,
+ {0,0,1,1,0,0,0,0}, //unknown
+ {1,0,0,0,0}, //PME and SMBUS
+ 0,
+ 0,
+ 0,
+ },
+ TYPE9_STRINGS_PCIE0X16
+};
+
+//PCIE0_X1 (Type 9)
+ARM_TYPE9_PCIE0X1 Pcie0X1_Type9 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 1,
+ SlotTypePciX,
+ SlotDataBusWidth1X,
+ SlotUsageAvailable,
+ SlotLengthShort,
+ 1,
+ {0,0,1,1,0,0,0,0}, //unknown
+ {1,0,0,0,0}, //PME and SMBUS
+ 0xFF,
+ 0xFF,
+ 0xFF,
+ },
+ TYPE9_STRINGS_PCIE0X1
+};
+
+//PCIE1_X16 (Type 9)
+ARM_TYPE9_PCIE1X16 Pcie1X16_Type9 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 1,
+ SlotTypePciX,
+ SlotDataBusWidth16X,
+ SlotUsageAvailable,
+ SlotLengthLong,
+ 2,
+ {0,0,1,1,0,0,0,0}, //unknown
+ {1,0,0,0,0}, //PME and SMBUS
+ 0xFF,
+ 0xFF,
+ 0xFF,
+ },
+ TYPE9_STRINGS_PCIE1X16
+};
+
+//PCIE1_X1 (Type 9)
+ARM_TYPE9_PCIE1X1 Pcie1X1_Type9 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE9), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 1,
+ SlotTypePciX,
+ SlotDataBusWidth1X,
+ SlotUsageAvailable,
+ SlotLengthShort,
+ 3,
+ {0,0,1,1,0,0,0,0}, //unknown
+ {1,0,0,0,0}, //PME and SMBUS
+ 0xFF,
+ 0xFF,
+ 0xFF,
+ },
+ TYPE9_STRINGS_PCIE1X1
+};
+
+//Bios Language Information (Type13)
+ARM_TYPE13 BiosLangInfo_Type13 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE13), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 2,
+ 0,
+ {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+ 2
+ },
+ TYPE13_STRINGS
+};
+
+//Physical Memory Array (Type 16)
+ARM_TYPE16 MemArray_Type16 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE16), // UINT8 Length
+ SMBIOS_HANDLE_MEMORY
+ },
+ MemoryArrayLocationSystemBoard,
+ MemoryArrayUseSystemMemory,
+ MemoryErrorCorrectionNone,
+ 0x1000000, //16G
+ 0xFFFE,
+ 2
+ },
+ TYPE16_STRINGS
+};
+
+//Memory Device (Type17)
+ARM_TYPE17_CHANNEL0 MemDev_Type17_0 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length
+ SMBIOS_HANDLE_DIMM_0
+ },
+ SMBIOS_HANDLE_MEMORY, //array to which this module belongs
+ 0xFFFE, //no errors
+ 64, //single DIMM, no ECC is 64bits (for ecc this would be 72)
+ 64, //data width of this device (64-bits)
+ 0x4000, //16GB
+ 0x09, //FormFactor
+ 0, //not part of a set
+ 1, //right side of board
+ 2, //bank 0
+ MemoryTypeDdr4, //LP DDR4
+ {0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0}, //unbuffered
+ 2400, //2400Mhz DDR
+ 3, //Manufacturer
+ 4, //serial
+ 5, //asset tag
+ 6, //part number
+ 0, //attrbute
+ 0x2000, // 8G
+ 2400, //2400MHz
+ 1500, //Max V
+ 1500, //Max V
+ 1500, //Configure V
+ },
+ TYPE17_STRINGS_CHANNEL0
+};
+
+//Memory Device (Type17)
+ARM_TYPE17_CHANNEL1 MemDev_Type17_1 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_MEMORY_DEVICE, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE17), // UINT8 Length
+ SMBIOS_HANDLE_DIMM_1
+ },
+ SMBIOS_HANDLE_MEMORY, //array to which this module belongs
+ 0xFFFE, //no errors
+ 64, //single DIMM, no ECC is 64bits (for ecc this would be 72)
+ 64, //data width of this device (64-bits)
+ 0x2000, //8GB
+ 0x09, //FormFactor
+ 0, //not part of a set
+ 1, //right side of board
+ 2, //bank 0
+ MemoryTypeDdr4, //LP DDR4
+ {0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0}, //unbuffered
+ 2400, //2400Mhz DDR
+ 3, //varies between diffrent production runs
+ 4, //serial
+ 5, //asset tag
+ 6, //part number
+ 0, //attrbute
+ 0x4000, // 16G
+ 2400, //2400MHz
+ 1500, //Max V
+ 1500, //Max V
+ 1500, //Configure V
+ },
+ TYPE17_STRINGS_CHANNEL1
+};
+
+#if 1
+//Memory Array Mapped Address (Type 19)
+ARM_TYPE19 MemArrayMapAddr_Type19 = {
+ {
+ { // SMBIOS_STRUCTURE Hdr
+ EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, // UINT8 Type
+ sizeof (SMBIOS_TABLE_TYPE19), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ 0,
+ 0x1000000, //16G
+ SMBIOS_HANDLE_MEMORY, //handle
+ 2,
+ 0, //starting addr of first 2GB
+ 0, //ending addr of first 2GB
+ },
+ TYPE19_STRINGS
+};
+#endif
+
+//System Boot Information (Type 32)
+ARM_TYPE32 SystemBoot_Type32 = {
+ {
+ { // Hdr
+ EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type,
+ sizeof (SMBIOS_TABLE_TYPE32), // UINT8 Length
+ SMBIOS_HANDLE_PI_RESERVED
+ },
+ { // Reserved[6]
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+ },
+ BootInformationStatusNoError // BootInformationStatus
+ },
+ TYPE32_STRINGS
+};
+
+VOID *DefaultCommonTables[]=
+{
+ &BiosInfo_Type0,
+ &SystemInfo_Type1,
+ &BaseboardInfo_Type2,
+ &SystemEnclosure_Type3,
+ &ProcessorInfo_Type4,
+ &L1Data_Type7,
+ &L1Ins_Type7,
+ &L2_Type7,
+ &L3_Type7,
+ &Pcie0X16_Type9,
+ &Pcie0X1_Type9,
+ &Pcie1X16_Type9,
+ &Pcie1X1_Type9,
+ &MemArray_Type16,
+ &MemDev_Type17_0,
+ &MemDev_Type17_1,
+ &MemArrayMapAddr_Type19,
+ &BiosLangInfo_Type13,
+ &SystemBoot_Type32,
+ NULL
+};
+
+
+/**
+ Installed a whole table worth of structructures.
+
+ @param[in] Smbios The Pointer of Smbios Protocol.
+
+ @retval EFI_SUCCESS Table data successfully installed.
+ @retval Other Table data was not installed.
+
+**/
+EFI_STATUS
+InstallStructures (
+ IN EFI_SMBIOS_PROTOCOL *Smbios,
+ IN VOID *DefaultTables[]
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+
+ UINT32 TableEntry;
+ for ( TableEntry=0; DefaultTables[TableEntry] != NULL; TableEntry++)
+ {
+ SmbiosHandle = ((EFI_SMBIOS_TABLE_HEADER*)DefaultTables[TableEntry])->Handle;
+ Status = Smbios->Add (
+ Smbios,
+ NULL,
+ &SmbiosHandle,
+ (EFI_SMBIOS_TABLE_HEADER*) DefaultTables[TableEntry]
+ );
+ if (EFI_ERROR(Status))
+ break;
+ }
+
+ return Status;
+}
+
+
+/**
+ Installed All SMBIOS information.
+
+ @param[in] Smbios The Pointer of Smbios Protocol.
+
+ @retval EFI_SUCCESS SMBIOS information successfully installed.
+ @retval Other SMBIOS information was not installed.
+
+**/
+STATIC
+EFI_STATUS
+InstallAllStructures (
+ IN EFI_SMBIOS_PROTOCOL *Smbios
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ Status = InstallStructures (Smbios, DefaultCommonTables);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
+/**
+ Find the smbios protocol and installed SMBIOS information
+ for ARM platforms.
+
+ @param[in] ImageHandle Module's image handle.
+ @param[in] SystemTable Pointer of EFI_SYSTEM_TABLE.
+
+ @retval EFI_SUCCESS Smbios data successfully installed.
+ @retval Other Smbios data was not installed.
+
+**/
+EFI_STATUS
+EFIAPI
+SmbiosTablePublishEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_PROTOCOL *Smbios;
+
+ //
+ // Find the SMBIOS protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID**)&Smbios
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Status = InstallAllStructures (Smbios);
+
+ return Status;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v1 04/10] Silicon/Phytium/Phytium2000-4/Library: Added PciSegmentLib to Phytium2000-4
2021-01-15 8:47 added support for DurianPkg Ling Jia
` (2 preceding siblings ...)
2021-01-15 8:47 ` [PATCH v1 03/10] Silicon/Phytium: Added SMBIOS " Ling Jia
@ 2021-01-15 8:47 ` Ling Jia
2021-01-15 8:47 ` [PATCH v1 05/10] Silicon/Phytium: Added PciHostBridgeLib " Ling Jia
` (7 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ling Jia @ 2021-01-15 8:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling, Peng Xie, Yiqi Shu
From: Ling <jialing@phytium.com.cn>
The PCI Segment Library for Phytium platform
with multiple RCs.
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Signed-off-by: Peng Xie <xiepeng@phytium.com.cn>
Reviewed-by: Yiqi Shu <shuyiqi@phytium.com.cn>
---
Platform/Phytium/Durian/DurianPkg.dsc | 3 +-
Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.inf | 28 +
Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.c | 1440 ++++++++++++++++++++
3 files changed, 1470 insertions(+), 1 deletion(-)
diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
index f260bab450f3..a765ce0126b5 100644
--- a/Platform/Phytium/Durian/DurianPkg.dsc
+++ b/Platform/Phytium/Durian/DurianPkg.dsc
@@ -37,7 +37,8 @@ [LibraryClasses.common]
PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf
[LibraryClasses.common.DXE_DRIVER]
-
+ # Pci dependencies
+ PciSegmentLib|Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.inf
################################################################################
#
diff --git a/Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.inf b/Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.inf
new file mode 100644
index 000000000000..059743903356
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.inf
@@ -0,0 +1,28 @@
+#/** @file
+# PCI Segment Library for Phytium platform with multiple RCs.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = PciSegmentLib
+ FILE_GUID = fa5173d2-40fe-11eb-9b2f-cb20dc669fd3
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciSegmentLib
+
+[Sources]
+ PciSegmentLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/Phytium/Phytium.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
diff --git a/Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.c b/Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.c
new file mode 100644
index 000000000000..5f35ef58e6ad
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.c
@@ -0,0 +1,1440 @@
+/** @file
+ PCI Segment Library for SoC with multiple RCs.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+
+#define PCI_SEG_CONFIG_BASE 0x40000000
+#define PCIE_BIF_MODE 0x29100800
+
+typedef enum {
+ PciCfgWidthUint8 = 0,
+ PciCfgWidthUint16,
+ PciCfgWidthUint32,
+ PciCfgWidthMax
+} PCI_CFG_WIDTH;
+
+/**
+ Assert the validity of a PCI Segment address.
+ A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63
+
+ @param[in] A The address to validate.
+ @param[in] M Additional bits to assert to be zero.
+
+**/
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
+
+
+#define EXTRACT_PCIE_ADDRESS(Address, Bus, Device, Function) \
+{ \
+ (Bus) = (((Address) >> 20) & 0xff); \
+ (Device) = (((Address) >> 15) & 0x1f); \
+ (Function) = (((Address) >> 12) & 0x07); \
+}
+
+
+/**
+ This function geted the config base of PCI device.
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The value of the config base of PCI device.
+
+**/
+STATIC
+UINT64
+PciSegmentLibGetConfigBase (
+ IN UINT64 Address
+ )
+{
+ UINT8 Bus, Device, Function;
+ UINT8 RootPortCount, Peu0RootPortCount, Peu1RootPortCount;
+ UINT32 BifMode, Peu0BifMode, Peu1BifMode;
+
+ EXTRACT_PCIE_ADDRESS (Address, Bus, Device, Function);
+ BifMode = MmioRead32(PCIE_BIF_MODE);
+ Peu0BifMode = BifMode & 0x3;
+ Peu1BifMode = (BifMode >> 2) & 0x3;
+
+ if((Peu0BifMode == 1)) {
+ Peu0RootPortCount = 3;
+ } else {
+ Peu0RootPortCount = 2;
+ }
+
+ if((Peu1BifMode == 1)) {
+ Peu1RootPortCount = 3;
+ } else {
+ Peu1RootPortCount = 2;
+ }
+ RootPortCount = Peu0RootPortCount + Peu1RootPortCount;
+ //ignore device > 0 or function > 0 on root port
+ if(RootPortCount == 4) {
+ if((Bus == 1) || (Bus == 2) || (Bus == 3) || (Bus == 4)) {
+ if (Device != 0 || Function != 0) {
+ return 0xFFFFFFFF;
+ }
+ return PCI_SEG_CONFIG_BASE;
+ }
+ } else if(RootPortCount == 5) {
+ if((Bus == 1) || (Bus == 2) || (Bus == 3) || (Bus == 4) || (Bus == 5)) {
+ if (Device != 0 || Function != 0) {
+ return 0xFFFFFFFF;
+ }
+ return PCI_SEG_CONFIG_BASE;
+ }
+ } else if(RootPortCount == 6) {
+ if((Bus == 1) || (Bus == 2) || (Bus == 3) || (Bus == 4) || (Bus == 5) || (Bus == 6)) {
+ if (Device != 0 || Function != 0) {
+ return 0xFFFFFFFF;
+ }
+ return PCI_SEG_CONFIG_BASE;
+ }
+ }
+
+ return PCI_SEG_CONFIG_BASE;
+}
+
+/**
+ Internal worker function to read a PCI configuration register.
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] Width The width of data to read
+
+ @return The value read from the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibReadWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width
+ )
+{
+ UINT64 Base;
+
+ Base = PciSegmentLibGetConfigBase (Address);
+ if(Base == 0xFFFFFFFF) {
+ return 0xFFFFFFFF;
+ }
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ return MmioRead8 (Base + (UINT32)Address);
+ case PciCfgWidthUint16:
+ return MmioRead16 (Base + (UINT32)Address);
+ case PciCfgWidthUint32:
+ return MmioRead32 (Base + (UINT32)Address);
+ default:
+ ASSERT (FALSE);
+ }
+
+ return 0;
+}
+
+
+/**
+ Internal worker function to writes a PCI configuration register.
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param[in] Width The width of data to write
+ @param[in] Data The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+STATIC
+UINT32
+PciSegmentLibWriteWorker (
+ IN UINT64 Address,
+ IN PCI_CFG_WIDTH Width,
+ IN UINT32 Data
+ )
+{
+ UINT64 Base;
+
+ Base = PciSegmentLibGetConfigBase (Address);
+ if(Base == 0xFFFFFFFF) {
+ return 0xFFFFFFFF;
+ }
+
+ switch (Width) {
+ case PciCfgWidthUint8:
+ MmioWrite8 (Base + (UINT32)Address, Data);
+ break;
+ case PciCfgWidthUint16:
+ MmioWrite16 (Base + (UINT32)Address, Data);
+ break;
+ case PciCfgWidthUint32:
+ MmioWrite32 (Base + (UINT32)Address, Data);
+ break;
+ default:
+ ASSERT (FALSE);
+ }
+
+ return Data;
+}
+
+/**
+ Register a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_SUCCESS The PCI device was registered for runtime access.
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ @retval RETURN_UNSUPPORTED The resources required to access the PCI device
+ at runtime could not be mapped.
+ @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
+ complete the registration.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciSegmentRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+
+ @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+PciSegmentRead8 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibReadWorker (Address, PciCfgWidthUint8);
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentWrite8 (
+ IN UINT64 Address,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
+
+ return (UINT8) PciSegmentLibWriteWorker (Address, PciCfgWidthUint8, Value);
+}
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentOr8 (
+ IN UINT64 Address,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAnd8 (
+ IN UINT64 Address,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
+ followed a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 8-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentAndThenOr8 (
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldRead8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldWrite8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAnd8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..7.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..7.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciSegmentBitFieldAndThenOr8 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PciSegmentWrite8 (
+ Address,
+ BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+ @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+PciSegmentRead16 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibReadWorker (Address, PciCfgWidthUint16);
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+PciSegmentWrite16 (
+ IN UINT64 Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
+
+ return (UINT16) PciSegmentLibWriteWorker (Address, PciCfgWidthUint16, Value);
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function and
+ Register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentOr16 (
+ IN UINT64 Address,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAnd16 (
+ IN UINT64 Address,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
+ followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentAndThenOr16 (
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldRead16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldWrite16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
+ and writes the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 16-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+ Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ The ordinal of the least significant bit in a byte is bit 0.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ The ordinal of the most significant bit in a byte is bit 7.
+ @param[in] AndData The value to AND with the read value from the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAnd16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..15.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..15.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciSegmentBitFieldAndThenOr16 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PciSegmentWrite16 (
+ Address,
+ BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+
+ @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+PciSegmentRead32 (
+ IN UINT64 Address
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibReadWorker (Address, PciCfgWidthUint32);
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device,
+ Function, and Register.
+ @param[in] Value The value to write.
+
+ @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+PciSegmentWrite32 (
+ IN UINT64 Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
+
+ return PciSegmentLibWriteWorker (Address, PciCfgWidthUint32, Value);
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise OR between the read result and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function, and Register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentOr32 (
+ IN UINT64 Address,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAnd32 (
+ IN UINT64 Address,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
+ followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address,
+ performs a bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+ and writes the result to the 32-bit PCI configuration register specified by Address.
+ The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are serialized.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param[in] Address The address that encodes the PCI Segment, Bus, Device, Function,
+ and Register.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentAndThenOr32 (
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to read.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldRead32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldWrite32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
+ AND between the read result and the value specified by AndData, and writes the result
+ to the 32-bit PCI configuration register specified by Address. The value written to
+ the PCI configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in AndData are stripped.
+ If any reserved bits in Address are set, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAnd32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If any reserved bits in Address are set, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+ @param[in] Address The PCI configuration register to write.
+ @param[in] StartBit The ordinal of the least significant bit in the bit field.
+ Range 0..31.
+ @param[in] EndBit The ordinal of the most significant bit in the bit field.
+ Range 0..31.
+ @param[in] AndData The value to AND with the PCI configuration register.
+ @param[in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciSegmentBitFieldAndThenOr32 (
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PciSegmentWrite32 (
+ Address,
+ BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)
+ );
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param[in] StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param[in] Size The size in bytes of the transfer.
+ @param[in] Buffer The pointer to a buffer receiving the data read.
+
+ @return Size
+
+**/
+UINTN
+EFIAPI
+PciSegmentReadBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Read a byte if StartAddress is byte aligned
+ //
+ *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Read a word if StartAddress is word aligned
+ //
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Read as many double words as possible
+ //
+ WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Read the last remaining word if exist
+ //
+ WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Read the last remaining byte if exist
+ //
+ *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
+ }
+
+ return ReturnValue;
+}
+
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If any reserved bits in StartAddress are set, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param[in] StartAddress The starting address that encodes the PCI Segment, Bus,
+ Device, Function and Register.
+ @param[in] Size The size in bytes of the transfer.
+ @param[in] Buffer The pointer to a buffer containing the data to write.
+
+ @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+PciSegmentWriteBuffer (
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return 0;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ //
+ // Save Size for return
+ //
+ ReturnValue = Size;
+
+ if ((StartAddress & BIT0) != 0) {
+ //
+ // Write a byte if StartAddress is byte aligned
+ //
+ PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ //
+ // Write a word if StartAddress is word aligned
+ //
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ //
+ // Write as many double words as possible
+ //
+ PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ //
+ // Write the last remaining word if exist
+ //
+ PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16*)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ //
+ // Write the last remaining byte if exist
+ //
+ PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
+ }
+
+ return ReturnValue;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v1 05/10] Silicon/Phytium: Added PciHostBridgeLib to Phytium2000-4
2021-01-15 8:47 added support for DurianPkg Ling Jia
` (3 preceding siblings ...)
2021-01-15 8:47 ` [PATCH v1 04/10] Silicon/Phytium/Phytium2000-4/Library: Added PciSegmentLib " Ling Jia
@ 2021-01-15 8:47 ` Ling Jia
2021-01-15 8:47 ` [PATCH v1 06/10] Silicon/Phytium: Added Logo support to Phytium Silicon Ling Jia
` (6 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ling Jia @ 2021-01-15 8:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling, Peng Xie, Yiqi Shu
From: Ling <jialing@phytium.com.cn>
The Pci host bridge library is mainly
to get Pci bridge information.
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Signed-off-by: Peng Xie <xiepeng@phytium.com.cn>
Reviewed-by: Yiqi Shu <shuyiqi@phytium.com.cn>
---
Platform/Phytium/Durian/DurianPkg.dsc | 9 +
Platform/Phytium/Durian/DurianPkg.fdf | 9 +
Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 55 ++++++
Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.c | 182 ++++++++++++++++++++
4 files changed, 255 insertions(+)
diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
index a765ce0126b5..09c90d590347 100644
--- a/Platform/Phytium/Durian/DurianPkg.dsc
+++ b/Platform/Phytium/Durian/DurianPkg.dsc
@@ -39,6 +39,7 @@ [LibraryClasses.common]
[LibraryClasses.common.DXE_DRIVER]
# Pci dependencies
PciSegmentLib|Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.inf
+ PciHostBridgeLib|Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.inf
################################################################################
#
@@ -274,6 +275,14 @@ [Components.common]
MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ #
+ # PCI Support
+ #
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf
+
#
# The following 2 module perform the same work except one operate variable.
# Only one of both should be put into fdf.
diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Durian/DurianPkg.fdf
index 98d3e07999ee..d50b2116b99a 100644
--- a/Platform/Phytium/Durian/DurianPkg.fdf
+++ b/Platform/Phytium/Durian/DurianPkg.fdf
@@ -109,6 +109,9 @@ [FV.FvMain]
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ # Required by PCI
+ INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+
#
# ACPI Support
#
@@ -135,6 +138,12 @@ [FV.FvMain]
INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ #
+ # PCI Support
+ #
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
#
# SATA Controller
#
diff --git a/Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.inf
new file mode 100644
index 000000000000..70b8496e06d4
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -0,0 +1,55 @@
+#/** @file
+# PCI Host Bridge Library instance for Phytium SOC.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = PciHostBridgeLib
+ FILE_GUID = f965de0e-40fe-11eb-8290-3f9d1f895a80
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = ARM AARCH64
+#
+
+[Sources]
+ PciHostBridgeLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/Phytium/Phytium.dec
+
+[LibraryClasses]
+ ArmLib
+ DebugLib
+ DevicePathLib
+ MemoryAllocationLib
+ HobLib
+
+[Guids]
+ gPhytiumPlatformPciHostInforGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+ gArmTokenSpaceGuid.PcdPciIoBase
+ gArmTokenSpaceGuid.PcdPciIoSize
+ gArmTokenSpaceGuid.PcdPciIoTranslation
+ gArmTokenSpaceGuid.PcdPciMmio32Base
+ gArmTokenSpaceGuid.PcdPciMmio32Size
+ gArmTokenSpaceGuid.PcdPciMmio32Translation
+ gArmTokenSpaceGuid.PcdPciMmio64Base
+ gArmTokenSpaceGuid.PcdPciMmio64Size
+ gArmTokenSpaceGuid.PcdPciMmio64Translation
diff --git a/Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.c
new file mode 100644
index 000000000000..ee9a79d73107
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -0,0 +1,182 @@
+/** @file
+ PCI Host Bridge Library instance for Phytium SOC.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Library/HobLib.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+#pragma pack(1)
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+
+#pragma pack ()
+
+#define END_DEVICE_PATH_DEF { END_DEVICE_PATH_TYPE, \
+ END_ENTIRE_DEVICE_PATH_SUBTYPE, \
+ { END_DEVICE_PATH_LENGTH, 0 } \
+ }
+
+#define ACPI_DEVICE_PATH_DEF(UID) {{ ACPI_DEVICE_PATH, ACPI_DP, \
+ {(UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)} \
+ }, \
+ EISA_PNP_ID (0x0A03), UID \
+ }
+
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = {
+ {
+ ACPI_DEVICE_PATH_DEF(0),
+ END_DEVICE_PATH_DEF
+ },
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+ L"Mem", L"I/O", L"Bus"
+};
+
+STATIC PCI_ROOT_BRIDGE mRootBridge = {
+ 0, // Segment
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ {
+ // Bus
+ FixedPcdGet32 (PcdPciBusMin),
+ FixedPcdGet32 (PcdPciBusMax)
+ }, {
+ // Io
+ FixedPcdGet64 (PcdPciIoBase),
+ FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
+ }, {
+ // Mem
+ FixedPcdGet32 (PcdPciMmio32Base),
+ FixedPcdGet32 (PcdPciMmio32Base) + (FixedPcdGet32 (PcdPciMmio32Size) - 1)
+ //0x7FFFFFFF
+ }, {
+ // MemAbove4G
+ FixedPcdGet64 (PcdPciMmio64Base),
+ FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1
+ }, {
+ // PMem
+ MAX_UINT64,
+ 0
+ }, {
+ // PMemAbove4G
+ MAX_UINT64,
+ 0
+ },
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath
+};
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param[out] Count Return the count of root bridge instances.
+
+ @return All the root bridge instances in an array.
+ The array should be passed into PciHostBridgeFreeRootBridges()
+ when it's not used.
+
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ OUT UINTN *Count
+ )
+{
+ *Count = 1;
+ return &mRootBridge;
+}
+
+
+/**
+ Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
+
+ @param[in] Bridges The root bridge instances array.
+ @param[in] Count The count of the array.
+
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ IN PCI_ROOT_BRIDGE *Bridges,
+ IN UINTN Count
+ )
+{
+
+}
+
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param[in] HostBridgeHandle Handle of the Host Bridge.
+ @param[in] Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the resources
+ for all the root bridges. The resource for each root
+ bridge is terminated with END descriptor and an
+ additional END is appended indicating the end of the
+ entire resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ SubmitResources().
+
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ IN EFI_HANDLE HostBridgeHandle,
+ IN VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex;
+
+ RootBridgeIndex = 0;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (Descriptor->ResType <
+ ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr));
+ DEBUG ((DEBUG_INFO, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen, Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ DEBUG ((DEBUG_INFO, " Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+ //
+ // Skip the end descriptor for root bridge
+ //
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v1 06/10] Silicon/Phytium: Added Logo support to Phytium Silicon
2021-01-15 8:47 added support for DurianPkg Ling Jia
` (4 preceding siblings ...)
2021-01-15 8:47 ` [PATCH v1 05/10] Silicon/Phytium: Added PciHostBridgeLib " Ling Jia
@ 2021-01-15 8:47 ` Ling Jia
2021-01-15 8:47 ` [PATCH v1 07/10] Silicon/Phytium: Added Spi driver support to Phytium2000-4 Ling Jia
` (5 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ling Jia @ 2021-01-15 8:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling, Peng Xie, Yiqi Shu
From: Ling <jialing@phytium.com.cn>
The LogoLib and PhytiumLogo.bmp is used to supported
the function of image display in the setup interface.
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Signed-off-by: Peng Xie <xiepeng@phytium.com.cn>
Reviewed-by: Yiqi Shu <shuyiqi@phytium.com.cn>
---
Platform/Phytium/Durian/DurianPkg.dsc | 1 +
Platform/Phytium/Durian/DurianPkg.fdf | 8 ++
Silicon/Phytium/Library/LogoLib/LogoLib.inf | 58 +++++++++
Silicon/Phytium/Library/LogoLib/Logo.c | 133 ++++++++++++++++++++
Silicon/Phytium/Logo/PhytiumLogo.bmp | Bin 0 -> 32454 bytes
5 files changed, 200 insertions(+)
diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
index 09c90d590347..5c40d9fb5dce 100644
--- a/Platform/Phytium/Durian/DurianPkg.dsc
+++ b/Platform/Phytium/Durian/DurianPkg.dsc
@@ -28,6 +28,7 @@ [Defines]
[LibraryClasses.common]
# Phytium Platform library
ArmPlatformLib|Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf
+ LogoLib|Silicon/Phytium/Library/LogoLib/LogoLib.inf
TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Durian/DurianPkg.fdf
index d50b2116b99a..d39d1a660102 100644
--- a/Platform/Phytium/Durian/DurianPkg.fdf
+++ b/Platform/Phytium/Durian/DurianPkg.fdf
@@ -192,6 +192,14 @@ [FV.FvMain]
INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
INF MdeModulePkg/Application/UiApp/UiApp.inf
+ #
+ # Logo
+ #
+ INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
+ FILE FREEFORM = PCD(gPhytiumPlatformTokenSpaceGuid.PcdLogoFile) {
+ SECTION RAW = Silicon/Phytium/Logo/PhytiumLogo.bmp
+ }
+
[FV.FVMAIN_COMPACT]
FvAlignment = 16
ERASE_POLARITY = 1
diff --git a/Silicon/Phytium/Library/LogoLib/LogoLib.inf b/Silicon/Phytium/Library/LogoLib/LogoLib.inf
new file mode 100644
index 000000000000..48311ff4e320
--- /dev/null
+++ b/Silicon/Phytium/Library/LogoLib/LogoLib.inf
@@ -0,0 +1,58 @@
+#/** @file
+# General BDS defines and produce general interfaces for platform BDS driver including:
+# 1) BDS boot policy interface;
+# 2) BDS boot device connect interface;
+# 3) BDS Misc interfaces for mainting boot variable, ouput string, etc.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = LogoLib
+ FILE_GUID = e2a614da-40dc-11eb-a964-cfa221f53ad8
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = LogoLib|DXE_DRIVER UEFI_APPLICATION
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ Logo.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ UefiBootServicesTableLib
+ MemoryAllocationLib
+ UefiLib
+ BaseMemoryLib
+ DebugLib
+ PrintLib
+ PcdLib
+ DxeServicesLib
+ BmpSupportLib
+
+[Guids]
+ gEfiConsoleOutDeviceGuid
+
+[Protocols]
+ gEfiGraphicsOutputProtocolGuid # PROTOCOL SOMETIMES_CONSUMES
+ gEfiUgaDrawProtocolGuid |PcdUgaConsumeSupport # PROTOCOL SOMETIMES_CONSUMES
+ gEfiBootLogoProtocolGuid # PROTOCOL SOMETIMES_CONSUMES
+ gEfiUserManagerProtocolGuid # PROTOCOL CONSUMES
+
+[FeaturePcd]
+ gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport
+
+[Pcd]
diff --git a/Silicon/Phytium/Library/LogoLib/Logo.c b/Silicon/Phytium/Library/LogoLib/Logo.c
new file mode 100644
index 000000000000..c56c9c2671bf
--- /dev/null
+++ b/Silicon/Phytium/Library/LogoLib/Logo.c
@@ -0,0 +1,133 @@
+/** @file
+ Phytium Logo Library.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Protocol/SimpleTextOut.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/UgaDraw.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DxeServicesLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BmpSupportLib.h>
+#include <IndustryStandard/Bmp.h>
+#include <Protocol/BootLogo.h>
+
+
+/**
+ Enabled the quiet boot.
+
+ @param[in] LogoFile The guid of logofile.
+
+ @retval EFI_SUCCESS Fuction executed successfully.
+ @retval EFI_UNSUPPORTED Protocol or logofile not found.
+
+**/
+EFI_STATUS
+EFIAPI
+EnableQuietBoot (
+ IN EFI_GUID *LogoFile
+ )
+{
+ EFI_STATUS Status;
+ UINT32 SizeOfX;
+ UINT32 SizeOfY;
+ UINTN ImageSize;
+ UINTN BltSize;
+ UINTN Height;
+ UINTN Width;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt = NULL;
+ UINT8 *ImageData = NULL;
+ EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput;
+
+ DEBUG((DEBUG_INFO, "EnableQuietBoot()\n"));
+
+ Status = gBS->HandleProtocol (gST->ConsoleOutHandle, &gEfiGraphicsOutputProtocolGuid, (VOID **) &GraphicsOutput);
+ if (EFI_ERROR (Status)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ gST->ConOut->EnableCursor (gST->ConOut, FALSE);
+ SizeOfX = GraphicsOutput->Mode->Info->HorizontalResolution;
+ SizeOfY = GraphicsOutput->Mode->Info->VerticalResolution;
+ DEBUG((DEBUG_INFO, "Gop:%lX %d x %d\n", (UINT64)(UINTN)GraphicsOutput, SizeOfX, SizeOfY));
+
+ Status = GetSectionFromAnyFv (LogoFile, EFI_SECTION_RAW, 0, (VOID **) &ImageData, &ImageSize);
+ if (EFI_ERROR (Status)) {
+ DEBUG((DEBUG_INFO, "Logo File Not Found!\n"));
+ Status = EFI_UNSUPPORTED;
+ goto ProcExit;
+ }
+
+ Status = TranslateBmpToGopBlt (
+ ImageData,
+ ImageSize,
+ &Blt,
+ &BltSize,
+ &Height,
+ &Width
+ );
+ if (EFI_ERROR (Status)) {
+ Status = EFI_UNSUPPORTED;
+ goto ProcExit;
+ }
+
+ Status = GraphicsOutput->Blt (
+ GraphicsOutput,
+ Blt,
+ EfiBltBufferToVideo,
+ 0,
+ 0,
+ (UINTN) (SizeOfX - Width) / 2,
+ (UINTN) (SizeOfY - Height) / 2,
+ Width,
+ Height,
+ Width * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
+ );
+
+ DEBUG((DEBUG_INFO, "Draw %d x %d: %r\n", Width, Height, Status));
+
+ProcExit:
+ if(ImageData != NULL){
+ FreePool(ImageData);
+ }
+
+ if(Blt!=NULL){
+ FreePool(Blt);
+ }
+
+ return Status;
+}
+
+
+/**
+ Use SystemTable Conout to turn on video based Simple Text Out consoles. The
+ Simple Text Out screens will now be synced up with all non video output devices
+
+ @param[in] None.
+
+ @retval EFI_SUCCESS UGA devices are back in text mode and synced up.
+
+**/
+EFI_STATUS
+EFIAPI
+DisableQuietBoot (
+ VOID
+ )
+{
+ //
+ // Enable Cursor on Screen
+ //
+ gST->ConOut->EnableCursor (gST->ConOut, TRUE);
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Phytium/Logo/PhytiumLogo.bmp b/Silicon/Phytium/Logo/PhytiumLogo.bmp
new file mode 100644
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zslvI4D;#`<-BYuondwG@)tGEgwG|Han{}@%iTi0r$i6}`_Va9H6OkX5T|A#H5(<X8
z`){1j{@<UMyd3fU(~#fi7m*0#Lq58kIdp^r2VIE6IE}=B5SAXO=}D^5&HgMgF`@V}
zT%|lOhFzz>uu}ulx-@(9HTrT?yK96<gT?b%JMuwEz?Ojj&pXi~`U?H|U-#m=Y4LBJ
zt+J|GLbUHtd*YW@BYzkV`Fhav*?{lEGj0$1ICKQ?s6s3~V$$DgHlOX!6cZDr*P;U*
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zAZd_jc8h`abQH~75b3`5^TU*Yq_pCj*Od!VLO!B+=z297`Cs>9A51X*Km3=lEoo8q
zUtRK?Zoneh5j5DT!ATlCX#u;;CdtOf{7gPfp{>p8T_oV{V)y2Y3<y2*u(Y`H{bb0S
z=cUD|_Uf9DzrE7Wo_&YX!m&S0#XsoALoPkyFhb%D3o+@zVFdPaf@(Z|8t7S38*HT)
zUhDtcO2Ea==>I%TeIXcw7FZ3rFdK{bx7nzFJWlz`6KWKsW#|~a{~R|*1-lNn$Ne-J
z{<Pl-?5?>k*r{QEqm|<@LUt2}j=0r`9c22y|KMvqK12z)Ia$B?rs&ng610P$`g%SV
z`Enxsms?SPyA%0;zo~ljbMIJp%+-#B(f-njLF)WOub-QFke4+SZzt3F@t(1Zq^n&S
zgN?y&Ua<b{X3V#j-9EpFWIMx74Tvyu5^n_4x@_*WSq;*cqc}c9*{#iKSqbb`JMeP8
z2CS*qQ;~olK{zd02dnHkJM{bMs2`wAg~3|+{Y3D;&qe>oZEpE~BIwmv;CJlc7o(xi
z1|hr{`1wE}!lR-wpfjHLk$phiof^Q>KkOk4u@*7#%g%Z2<nKiSuJ-27*ct!xAnC{H
zFfiKR1z<~}j&~4JanPheB;ol=Fp^7;#DIJ`=;H3wxZCUcwBP=ETg2~0N^A4{=Op0f
zVn5K8|Mhs<Kc1xj<wp4HsfcBKMjnKgsXS*#d^-|`WIJCC;pEaIJ2g1_fV>}_@q97t
zaj_ZV-D{seiUc$dX;CUu?hYM)^St&y??nCOX4I>RZ~=_HeYq3_+w;-zZ>~cwedt$L
zgTK7O*#~sd`|l5u<3fN`U;F$KC9qXOe*fOxwa5Mce5>-!pUQuk4g2@G7%;Ao46b)D
z#stt6$w3$BuHe^fzkhs5-o0nfA5oxd_q<2~>o;vrh>r<%*S&Q<<;`pAU*}`~*L3iY
zGg049M~fsj3&4p_x_&ni_0x3dn?ILU3hYW=bdj|Ke{>1By1J38GOu)`k9GRK`L+a9
z+4qx(tB5#^V_=wZ3OgKf2q7)!m)X$&xR=^NJ_a%CKf2)7?*Dxx5FQqCwI}zNr}URM
kbH1BO{%$4>HvYVt&Hw8ctS)k7c3RB)47S$x_a}k>2YH&B_W%F@
literal 0
HcmV?d00001
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v1 07/10] Silicon/Phytium: Added Spi driver support to Phytium2000-4
2021-01-15 8:47 added support for DurianPkg Ling Jia
` (5 preceding siblings ...)
2021-01-15 8:47 ` [PATCH v1 06/10] Silicon/Phytium: Added Logo support to Phytium Silicon Ling Jia
@ 2021-01-15 8:47 ` Ling Jia
2021-01-15 8:48 ` [PATCH v1 08/10] Silicon/Phytium: Added flash driver support to Phytium Silicon Ling Jia
` (4 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ling Jia @ 2021-01-15 8:47 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling, Peng Xie, Yiqi Shu
From: Ling <jialing@phytium.com.cn>
The PhytiumSpiDxe is to provide Spi bus read-write interface.
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Signed-off-by: Peng Xie <xiepeng@phytium.com.cn>
Reviewed-by: Yiqi Shu <shuyiqi@phytium.com.cn>
---
Platform/Phytium/Durian/DurianPkg.dsc | 5 +
Platform/Phytium/Durian/DurianPkg.fdf | 5 +
Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf | 52 ++++++
Silicon/Phytium/Include/Protocol/PhytiumSpi.h | 51 ++++++
Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.h | 73 ++++++++
Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.c | 189 ++++++++++++++++++++
6 files changed, 375 insertions(+)
diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
index 5c40d9fb5dce..a23c1d52cece 100644
--- a/Platform/Phytium/Durian/DurianPkg.dsc
+++ b/Platform/Phytium/Durian/DurianPkg.dsc
@@ -256,6 +256,11 @@ [Components.common]
#
ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+ #
+ # Spi driver
+ #
+ Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf
+
#
# Usb Support
#
diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Durian/DurianPkg.fdf
index d39d1a660102..ad0406b3133b 100644
--- a/Platform/Phytium/Durian/DurianPkg.fdf
+++ b/Platform/Phytium/Durian/DurianPkg.fdf
@@ -105,6 +105,11 @@ [FV.FvMain]
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+ #
+ # Spi driver
+ #
+ INF Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf
+
# Variable services
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf b/Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf
new file mode 100644
index 000000000000..522a633a23e6
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf
@@ -0,0 +1,52 @@
+#/** @file
+# Phytium Spi Master Drivers.
+#
+# Copyright (C) 2020, Phytium Technology Co,Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = PhytiumSpiDxe
+ FILE_GUID = 2ba95e5c-f7f5-11ea-bf18-67fdc5787495
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SpiMasterDrvEntryPoint
+
+[Sources.common]
+ PhytiumSpiDxe.c
+ PhytiumSpiDxe.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/Phytium/Phytium.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ PcdLib
+ IoLib
+ UefiBootServicesTableLib
+ DxeServicesTableLib
+ UefiRuntimeLib
+ UefiLib
+ UefiDriverEntryPoint
+
+[Guids]
+ gEfiEventVirtualAddressChangeGuid
+
+[Protocols]
+ gPhytiumSpiMasterProtocolGuid
+
+[FixedPcd]
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize
+
+[Depex]
+ TRUE
diff --git a/Silicon/Phytium/Include/Protocol/PhytiumSpi.h b/Silicon/Phytium/Include/Protocol/PhytiumSpi.h
new file mode 100644
index 000000000000..43a258924662
--- /dev/null
+++ b/Silicon/Phytium/Include/Protocol/PhytiumSpi.h
@@ -0,0 +1,51 @@
+/** @file
+ The Header of Protocol For SPI.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PHYTIUM_SPI_H__
+#define __PHYTIUM_SPI_H__
+
+extern EFI_GUID gPhytiumSpiMasterProtocolGuid;
+typedef struct _EFI_SPI_DRV_PROTOCOL EFI_SPI_DRV_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI *SPI_DRV_INIT_INTERFACE) (
+ VOID
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *SPI_DRV_SET_CONFIG_INTERFACE)(
+ IN UINT8 CmdId,
+ IN UINT32 Config,
+ IN UINTN RegAddr
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *SPI_DRV_GET_CONFIG_INTERFACE)(
+ IN UINT8 CmdId,
+ OUT UINT32 *Config,
+ IN UINTN RegAddr
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *SPI_DRV_CONFIG_MODE_INTERFACE)(
+ IN UINT32 Config
+ );
+
+struct _EFI_SPI_DRV_PROTOCOL{
+ SPI_DRV_INIT_INTERFACE SpiInit;
+ SPI_DRV_SET_CONFIG_INTERFACE SpiSetConfig;
+ SPI_DRV_GET_CONFIG_INTERFACE SpiGetConfig;
+ SPI_DRV_CONFIG_MODE_INTERFACE SpiSetMode;
+};
+
+#endif /* __PHYTIUM_SPI_H__ */
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.h b/Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.h
new file mode 100644
index 000000000000..1a5cbb6b5a33
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.h
@@ -0,0 +1,73 @@
+/** @file
+ Phytium Spi Drivers Header
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PHYTIUM_SPI_DXE_H__
+#define __PHYTIUM_SPI_DXE_H__
+
+#include <PiDxe.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Guid/EventGroup.h>
+#include <Protocol/PhytiumSpi.h>
+
+#define SPI_MASTER_SIGNATURE SIGNATURE_32 ('M', 'S', 'P', 'I')
+
+#define REG_MODE_REG 0x02C
+
+EFI_STATUS
+EFIAPI
+SpiMasterGetConfig (
+ IN UINT8 CmdId,
+ OUT UINT32 *Config,
+ IN UINTN RegAddr
+ );
+
+EFI_STATUS
+EFIAPI
+SpiMasterSetConfig (
+ IN UINT8 CmdId,
+ IN UINT32 Config,
+ IN UINTN RegAddr
+ );
+
+EFI_STATUS
+EFIAPI
+SpiMasterSetMode (
+ IN UINT32 Config
+ );
+
+EFI_STATUS
+EFIAPI
+SpiMasterInit (
+ VOID
+ );
+
+typedef struct {
+ EFI_SPI_DRV_PROTOCOL SpiMasterProtocol;
+ UINTN Signature;
+ EFI_HANDLE Handle;
+ } PHYT_SPI_MASTER;
+
+EFI_STATUS
+EFIAPI
+SpiMasterDrvEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+#endif /* __PHYTIUM_SPI_DXE_H__ */
diff --git a/Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.c b/Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.c
new file mode 100644
index 000000000000..ade1a2351d9f
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.c
@@ -0,0 +1,189 @@
+/** @file
+ Phytium Spi Master Drivers.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PhytiumSpiDxe.h"
+
+PHYT_SPI_MASTER *pSpiMasterInstance;
+static UINTN mSpiControlBase;
+
+/**
+ This function inited a spi driver.
+
+ @param None.
+
+ @retval None.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiMasterInit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function seted config to spi registers.
+
+ @param[in] CmdId The id of command.
+
+ @param[in] Config The value to be seted.
+
+ @param[in] RegAddr The address of spi registers.
+
+ @retval EFI_SUCCESS SpiMasterSetConfig() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiMasterSetConfig (
+ IN UINT8 CmdId,
+ IN UINT32 Config,
+ IN UINTN RegAddr
+ )
+{
+ UINTN SpiAddr = 0;
+ UINT32 Value = 0;
+
+ if(CmdId != 0)
+ Value =(CmdId << 24) | (Config & 0xffffff);
+ else
+ Value = Config;
+
+ SpiAddr = mSpiControlBase + RegAddr;
+ MmioWrite32 (SpiAddr, Value);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function geted config from spi registers.
+
+ @param[in] CmdId The id of command.
+
+ @param[out] Config The pointer of the config.
+
+ @param[in] RegAddr The address of spi registers.
+
+ @retval EFI_SUCCESS SpiMasterGetConfig() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiMasterGetConfig (
+ IN UINT8 CmdId,
+ OUT UINT32 *Config,
+ IN UINTN RegAddr
+ )
+{
+ UINTN SpiAddr = 0;
+ UINT32 Value = 0;
+
+ SpiAddr = mSpiControlBase + RegAddr;
+ Value = MmioRead32 (SpiAddr);
+ if(CmdId != 0)
+ *Config = Value & 0xffffff;
+ else
+ *Config = Value;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function seted spi mode.
+
+ @param[in] Config The value to seted.
+
+ @retval EFI_SUCCESS SpiMasterSetMode() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiMasterSetMode (
+ IN UINT32 Config
+ )
+{
+
+ SpiMasterSetConfig (0, Config, REG_MODE_REG);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function inited the spi driver protocol.
+
+ @param[in] SpiMasterProtocol A pointer to the master protocol struct.
+
+ @retval EFI_SUCCESS SpiMasterInitProtocol() is executed successfully.
+
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+SpiMasterInitProtocol (
+ IN EFI_SPI_DRV_PROTOCOL *SpiMasterProtocol
+ )
+{
+
+ SpiMasterProtocol->SpiInit = SpiMasterInit;
+ SpiMasterProtocol->SpiSetConfig = SpiMasterSetConfig;
+ SpiMasterProtocol->SpiGetConfig = SpiMasterGetConfig;
+ SpiMasterProtocol->SpiSetMode = SpiMasterSetMode;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function is the entrypoint of the spi driver.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiMasterDrvEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ pSpiMasterInstance = AllocateRuntimeZeroPool (sizeof (PHYT_SPI_MASTER));
+ if (pSpiMasterInstance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ mSpiControlBase = FixedPcdGet64 (PcdSpiControllerBase);
+
+ SpiMasterInitProtocol (&pSpiMasterInstance->SpiMasterProtocol);
+
+ pSpiMasterInstance->Signature = SPI_MASTER_SIGNATURE;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &(pSpiMasterInstance->Handle),
+ &gPhytiumSpiMasterProtocolGuid,
+ &(pSpiMasterInstance->SpiMasterProtocol),
+ NULL
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ return EFI_SUCCESS;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v1 08/10] Silicon/Phytium: Added flash driver support to Phytium Silicon
2021-01-15 8:47 added support for DurianPkg Ling Jia
` (6 preceding siblings ...)
2021-01-15 8:47 ` [PATCH v1 07/10] Silicon/Phytium: Added Spi driver support to Phytium2000-4 Ling Jia
@ 2021-01-15 8:48 ` Ling Jia
2021-01-15 8:48 ` [PATCH v1 09/10] Silicon/Phytium: Added fvb driver for norflash Ling Jia
` (3 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ling Jia @ 2021-01-15 8:48 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling, Peng Xie, Yiqi Shu
From: Ling <jialing@phytium.com.cn>
The PhytiumSpiNorFlashDxe provided norflash initialization,
read-write, erase and other interfaces.
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Signed-off-by: Peng Xie <xiepeng@phytium.com.cn>
Reviewed-by: Yiqi Shu <shuyiqi@phytium.com.cn>
---
Platform/Phytium/Durian/DurianPkg.dsc | 5 +
Platform/Phytium/Durian/DurianPkg.fdf | 5 +
Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf | 54 +++
Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.h | 106 +++++
Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h | 74 ++++
Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.c | 435 ++++++++++++++++++++
6 files changed, 679 insertions(+)
diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
index a23c1d52cece..d34432e95049 100644
--- a/Platform/Phytium/Durian/DurianPkg.dsc
+++ b/Platform/Phytium/Durian/DurianPkg.dsc
@@ -261,6 +261,11 @@ [Components.common]
#
Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf
+ #
+ # NOR Flash driver
+ #
+ Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf
+
#
# Usb Support
#
diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Durian/DurianPkg.fdf
index ad0406b3133b..703537033944 100644
--- a/Platform/Phytium/Durian/DurianPkg.fdf
+++ b/Platform/Phytium/Durian/DurianPkg.fdf
@@ -110,6 +110,11 @@ [FV.FvMain]
#
INF Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf
+ #
+ # NOR Flash driver
+ #
+ INF Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf
+
# Variable services
INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
diff --git a/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf
new file mode 100644
index 000000000000..2979dad60c1e
--- /dev/null
+++ b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf
@@ -0,0 +1,54 @@
+#/** @file
+# Phytium NorFlash Drivers.
+#
+# Copyright (C) 2020, Phytium Technology Co,Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = PhytiumSpiNorFlashDxe
+ FILE_GUID = f37ef706-187c-48fd-9102-ddbf86f551be
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = NorFlashPlatformEntryPoint
+
+[Sources.common]
+ PhytiumSpiNorFlashDxe.c
+ PhytiumSpiNorFlashDxe.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/Phytium/Phytium.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ PcdLib
+ IoLib
+ UefiBootServicesTableLib
+ DxeServicesTableLib
+ UefiRuntimeLib
+ UefiLib
+ UefiDriverEntryPoint
+
+[FixedPcd]
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerBase
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiControllerSize
+
+[Guids]
+ gEfiEventVirtualAddressChangeGuid
+
+[Protocols]
+ gPhytiumSpiMasterProtocolGuid
+ gPhytiumFlashProtocolGuid
+
+ [Depex]
+ TRUE
+ #gPhytiumSpiMasterProtocolGuid
diff --git a/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.h b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.h
new file mode 100644
index 000000000000..caee5591f3bd
--- /dev/null
+++ b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.h
@@ -0,0 +1,106 @@
+/** @file
+ Phytium NorFlash Drivers Header.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PHYTIUM_SPI_NORFALSH_DXE_H__
+#define __PHYTIUM_SPI_NORFALSH_DXE_H__
+
+#include <PiDxe.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Guid/EventGroup.h>
+
+#include <PhytiumSystemServiceInterface.h>
+#include <Protocol/PhytiumSpiNorFlash.h>
+#include <Protocol/PhytiumSpi.h>
+
+/**
+ Phytium Norflash registers
+**/
+#define REG_FLASH_CAP 0x000
+#define REG_RD_CFG 0x004
+#define REG_WR_CFG 0x008
+#define REG_FLUSH_REG 0x00C
+#define REG_CMD_PORT 0x010
+#define REG_ADDR_PORT 0x014
+#define REG_HD_PORT 0x018
+#define REG_LD_PORT 0x01C
+#define REG_CS_CFG 0x020
+#define REG_WIP_CFG 0x024
+#define REG_WP_REG 0x028
+
+#define NORFLASH_SIGNATURE SIGNATURE_32 ('P', 'T', 'Y', 'T')
+
+//
+// Platform Nor Flash Functions
+//
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformEraseSingleBlock (
+ IN UINTN BlockAddress
+ );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformErase (
+ IN UINT64 Offset,
+ IN UINT64 Length
+ );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformRead (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ OUT UINT32 Len
+ );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformWrite (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ IN UINT32 Len
+ );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformGetDevices (
+ OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices
+ );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformInitialization (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+NorFlashPlatformEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+typedef struct {
+ EFI_NORFLASH_DRV_PROTOCOL FlashProtocol;
+ UINTN Signature;
+ EFI_HANDLE Handle;
+} PHYT_NorFlash_Device;
+
+#endif /* __PHYTIUM_SPI_NORFALSH_DXE_H__ */
diff --git a/Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h b/Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h
new file mode 100644
index 000000000000..84c83dbd88eb
--- /dev/null
+++ b/Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h
@@ -0,0 +1,74 @@
+/** @file
+ The Header of Protocol For NorFlash.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PHYTIUM_SPI_NORFALSH_H__
+#define __PHYTIUM_SPI_NORFALSH_H__
+
+typedef struct _EFI_NORFLASH_DRV_PROTOCOL EFI_NORFLASH_DRV_PROTOCOL;
+extern EFI_GUID gPhytiumFlashProtocolGuid;
+
+typedef struct {
+ UINTN DeviceBaseAddress; // Start address of the Device Base Address (DBA)
+ UINTN RegionBaseAddress; // Start address of one single region
+ UINTN Size;
+ UINTN BlockSize;
+ EFI_GUID Guid;
+} NOR_FLASH_DEVICE_DESCRIPTION;
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_ERASE_INTERFACE) (
+ IN UINT64 Offset,
+ IN UINT64 Length
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE) (
+ IN UINTN BlockAddress
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_READ_INTERFACE) (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ OUT UINT32 Len
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_WRITE_INTERFACE) (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ IN UINT32 Len
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_GETDEVICE_INTERFACE) (
+ OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *NORFLASH_PLATFORM_INIT_INTERFACE) (
+ VOID
+ );
+
+struct _EFI_NORFLASH_DRV_PROTOCOL{
+ NORFLASH_PLATFORM_INIT_INTERFACE Initialization;
+ NORFLASH_PLATFORM_GETDEVICE_INTERFACE GetDevices;
+ NORFLASH_PLATFORM_ERASE_INTERFACE Erase;
+ NORFLASH_PLATFORM_ERASESIGLEBLOCK_INTERFACE EraseSingleBlock;
+ NORFLASH_PLATFORM_READ_INTERFACE Read;
+ NORFLASH_PLATFORM_WRITE_INTERFACE Write;
+};
+
+#endif /* __PHYTIUM_SPI_NORFALSH_H__*/
diff --git a/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.c b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.c
new file mode 100644
index 000000000000..2614035e0714
--- /dev/null
+++ b/Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.c
@@ -0,0 +1,435 @@
+/** @file
+ Phytium NorFlash Drivers.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PhytiumSpiNorFlashDxe.h"
+
+typedef struct {
+ UINT32 Flash_Index;
+ UINT32 Flash_Write;
+ UINT32 Flash_Erase;
+ UINT32 Flash_Pp;
+}FLASH_CMD_INFO;
+
+STATIC EFI_EVENT mSpiNorFlashVirtualAddrChangeEvent;
+STATIC UINTN mNorFlashControlBase;
+STATIC UINT32 mCmd_Write;
+STATIC UINT32 mCmd_Eares;
+STATIC UINT32 mCmd_Pp;
+
+#define SPI_FLASH_BASE FixedPcdGet64 (PcdSpiFlashBase)
+#define SPI_FLASH_SIZE FixedPcdGet64 (PcdSpiFlashSize)
+
+EFI_SPI_DRV_PROTOCOL *pSpiMasterProtocol;
+extern EFI_GUID gPhytiumSpiMasterProtocolGuid;
+PHYT_NorFlash_Device *flash_Instance;
+extern EFI_GUID gPhytiumFlashProtocolGuid;
+
+NOR_FLASH_DEVICE_DESCRIPTION mNorFlashDevices = {
+ SPI_FLASH_BASE, /* Device Base Address */
+ SPI_FLASH_BASE, /* Region Base Address */
+ SIZE_1MB * 16, /* Size */
+ SIZE_64KB, /* Block Size */
+ {0xE7223039, 0x5836, 0x41E1, { 0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5E, 0x59 } }
+};
+
+
+/**
+ This function writed up to 256 bytes to flash through spi driver.
+
+ @param[in] Address The address of the flash.
+ @param[in] Buffer The pointer of buffer to be writed.
+ @param[in] BufferSizeInBytes The bytes to be writed.
+
+ @retval EFI_SUCCESS NorFlashWrite256() is executed successfully.
+
+**/
+STATIC
+EFI_STATUS
+NorFlashWrite256 (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ IN UINT32 BufferSizeInBytes
+ )
+{
+ UINT32 Index;
+ UINT8 Cmd_id;
+ UINT32 *TemBuffer;
+
+ TemBuffer= Buffer;
+
+ if(BufferSizeInBytes > 256) {
+ DEBUG((DEBUG_ERROR, "The max length is 256 bytes.\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(BufferSizeInBytes % 4 != 0) {
+ DEBUG((DEBUG_ERROR, "The length must four bytes aligned.\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if(Address % 4 != 0) {
+ DEBUG((DEBUG_ERROR, "The address must four bytes aligned.\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Cmd_id = (UINT8)(mCmd_Pp & 0xff);
+ pSpiMasterProtocol->SpiSetConfig (Cmd_id, 0x400000, REG_CMD_PORT);
+ pSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);
+
+ asm volatile ("isb sy":::"cc");
+
+ Cmd_id = (UINT8)(mCmd_Write & 0xff);
+ pSpiMasterProtocol->SpiSetConfig (Cmd_id, 0x000208, REG_WR_CFG);
+
+ for(Index = 0; Index < BufferSizeInBytes / 4; Index++) {
+ MmioWrite32(Address + Index * 4, TemBuffer[Index]);
+ }
+
+ asm volatile ("isb sy":::"cc");
+
+ pSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_FLUSH_REG);
+
+ asm volatile ("isb sy":::"cc");
+
+ pSpiMasterProtocol->SpiSetConfig (0, 0x0, REG_WR_CFG);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function erased a sector of flash through spi driver.
+
+ @param[in] BlockAddress The sector address to be erased.
+
+ @retval None.
+
+**/
+STATIC
+inline void
+NorFlashPlatformEraseSector (
+ IN UINTN BlockAddress
+ )
+{
+ UINT8 Cmd_id = 0;
+
+ Cmd_id = (UINT8)(mCmd_Pp & 0xff);
+ pSpiMasterProtocol->SpiSetConfig (Cmd_id, 0x400000, REG_CMD_PORT);
+ pSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);
+
+ asm volatile ("isb sy":::"cc");
+
+ Cmd_id = (UINT8)(mCmd_Eares & 0xff);
+ pSpiMasterProtocol->SpiSetConfig (Cmd_id, 0x408000, REG_CMD_PORT);
+ pSpiMasterProtocol->SpiSetConfig (0, BlockAddress, REG_ADDR_PORT);
+ pSpiMasterProtocol->SpiSetConfig (0, 0x1, REG_LD_PORT);
+
+ asm volatile ("isb sy":::"cc");
+}
+
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed.
+
+ @param[in] Context Event Context.
+
+ @retval None.
+
+**/
+VOID
+EFIAPI
+PlatformNorFlashVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EfiConvertPointer (0x0, (VOID **)&mNorFlashControlBase);
+ EfiConvertPointer (0x0, (VOID**)&pSpiMasterProtocol->SpiGetConfig);
+ EfiConvertPointer (0x0, (VOID**)&pSpiMasterProtocol->SpiSetConfig);
+ EfiConvertPointer (0x0, (VOID**)&pSpiMasterProtocol);
+}
+
+
+/**
+ This function inited the flash platform.
+
+ @param None.
+
+ @retval EFI_SUCCESS NorFlashPlatformInitialization() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformInitialization (
+ VOID
+ )
+{
+
+ mCmd_Write = 0x2;
+ mCmd_Eares = 0xD8;
+ mCmd_Pp = 0x6;
+
+ mNorFlashControlBase = FixedPcdGet64 (PcdSpiControllerBase);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function geted the flash device information.
+
+ @param[out] NorFlashDevices the pointer to store flash device information.
+ @param[out] Count the number of the flash device.
+
+ @retval EFI_SUCCESS NorFlashPlatformGetDevices() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformGetDevices (
+ OUT NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevices
+ )
+{
+
+ *NorFlashDevices = mNorFlashDevices;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function readed flash content form the specified area of flash.
+
+ @param[in] Address The address of the flash.
+ @param[in] Buffer The pointer of the Buffer to be stored.
+ @param[out] Len The bytes readed form flash.
+
+ @retval EFI_SUCCESS NorFlashPlatformRead() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformRead (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ OUT UINT32 Len
+ )
+{
+
+ DEBUG((DEBUG_BLKIO, "NorFlashPlatformRead: Address: 0x%lx Buffer:0x%p Len:0x%x\n", Address, Buffer, Len));
+
+ CopyMem ((VOID *)Buffer, (VOID *)Address, Len);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function erased one block flash content.
+
+ @param[in] BlockAddress the BlockAddress to be erased.
+
+ @retval EFI_SUCCESS NorFlashPlatformEraseSingleBlock() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformEraseSingleBlock (
+ IN UINTN BlockAddress
+ )
+{
+
+ NorFlashPlatformEraseSector (BlockAddress);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function erased the flash content of the specified area.
+
+ @param[in] Offset the offset of the flash.
+ @param[in] Length length to be erased.
+
+ @retval EFI_SUCCESS NorFlashPlatformErase() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformErase (
+ IN UINT64 Offset,
+ IN UINT64 Length
+ )
+{
+ EFI_STATUS Status;
+ UINT64 Index;
+ UINT64 Count;
+
+ Status = EFI_SUCCESS;
+ if ((Length % SIZE_64KB) == 0) {
+ Count = Length / SIZE_64KB;
+ for (Index = 0; Index < Count; Index++) {
+ NorFlashPlatformEraseSingleBlock (Offset);
+ Offset += SIZE_64KB;
+ }
+ } else {
+ Status = EFI_INVALID_PARAMETER;
+ }
+
+ return Status;
+}
+
+
+/**
+ This function writed data to flash.
+
+ @param[in] Address the address of the flash.
+
+ @param[in] Buffer the pointer of the Buffer to be writed.
+
+ @param[in] BufferSizeInBytes the bytes of the Buffer.
+
+ @retval EFI_SUCCESS NorFlashPlatformWrite() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformWrite (
+ IN UINTN Address,
+ IN VOID *Buffer,
+ IN UINT32 BufferSizeInBytes
+ )
+{
+ UINT32 Index;
+ UINT32 Remainder;
+ UINT32 Quotient;
+ EFI_STATUS Status;
+ UINTN TmpAddress;
+
+ DEBUG((DEBUG_BLKIO, "NorFlashPlatformWrite: Address: 0x%x Len:0x%x.\n", Address, BufferSizeInBytes));
+
+ Index = 0;
+ Remainder = 0;
+ Quotient = 0;
+ TmpAddress = Address;
+ Remainder = BufferSizeInBytes % 256;
+ Quotient = BufferSizeInBytes / 256;
+
+ if(BufferSizeInBytes <= 256) {
+ Status = NorFlashWrite256 (TmpAddress, Buffer, BufferSizeInBytes);
+ } else {
+ for(Index = 0; Index < Quotient; Index++) {
+ Status = NorFlashWrite256 (TmpAddress, Buffer, 256);
+ TmpAddress += 256;
+ Buffer += 256;
+ }
+
+ if(Remainder != 0) {
+ Status = NorFlashWrite256 (TmpAddress, Buffer, Remainder);
+ }
+ }
+
+ if(EFI_ERROR(Status)) {
+ ASSERT_EFI_ERROR(Status);
+ }
+
+ return EFI_SUCCESS;
+
+}
+
+
+/**
+ This function inited the flash driver protocol.
+
+ @param[in] NorFlashProtocol A pointer to the norflash protocol struct.
+
+ @retval EFI_SUCCESS NorFlashPlatformInitProtocol() is executed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformInitProtocol (
+ IN EFI_NORFLASH_DRV_PROTOCOL *NorFlashProtocol
+ )
+{
+ NorFlashProtocol->Initialization = NorFlashPlatformInitialization;
+ NorFlashProtocol->GetDevices = NorFlashPlatformGetDevices;
+ NorFlashProtocol->Erase = NorFlashPlatformErase;
+ NorFlashProtocol->EraseSingleBlock = NorFlashPlatformEraseSingleBlock;
+ NorFlashProtocol->Read = NorFlashPlatformRead;
+ NorFlashProtocol->Write = NorFlashPlatformWrite;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function is the entrypoint of the norflash driver.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+NorFlashPlatformEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->LocateProtocol (
+ &gPhytiumSpiMasterProtocolGuid,
+ NULL,
+ (VOID **)&pSpiMasterProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ flash_Instance = AllocateRuntimeZeroPool (sizeof (PHYT_NorFlash_Device));
+ if (flash_Instance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ NorFlashPlatformInitProtocol (&flash_Instance->FlashProtocol);
+
+ flash_Instance->Signature = NORFLASH_SIGNATURE;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &(flash_Instance->Handle),
+ &gPhytiumFlashProtocolGuid,
+ &(flash_Instance->FlashProtocol),
+ NULL
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ //Register for the virtual address change event
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ PlatformNorFlashVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mSpiNorFlashVirtualAddrChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v1 09/10] Silicon/Phytium: Added fvb driver for norflash
2021-01-15 8:47 added support for DurianPkg Ling Jia
` (7 preceding siblings ...)
2021-01-15 8:48 ` [PATCH v1 08/10] Silicon/Phytium: Added flash driver support to Phytium Silicon Ling Jia
@ 2021-01-15 8:48 ` Ling Jia
2021-01-15 8:48 ` [PATCH v1 10/10] Silicon/Phytium: Added Rtc driver to Phytium2000-4 Ling Jia
` (2 subsequent siblings)
11 siblings, 0 replies; 15+ messages in thread
From: Ling Jia @ 2021-01-15 8:48 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling, Peng Xie, Yiqi Shu
From: Ling <jialing@phytium.com.cn>
The PhytiumFlashFvbDxe provided the fvb protocol,
which requested by the flah operators.
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Signed-off-by: Peng Xie <xiepeng@phytium.com.cn>
Reviewed-by: Yiqi Shu <shuyiqi@phytium.com.cn>
---
Platform/Phytium/Durian/DurianPkg.dsc | 1 +
Platform/Phytium/Durian/DurianPkg.fdf | 1 +
Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.inf | 72 ++
Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.h | 106 ++
Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.c | 1235 ++++++++++++++++++++
5 files changed, 1415 insertions(+)
diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
index d34432e95049..df43c3d5d23a 100644
--- a/Platform/Phytium/Durian/DurianPkg.dsc
+++ b/Platform/Phytium/Durian/DurianPkg.dsc
@@ -265,6 +265,7 @@ [Components.common]
# NOR Flash driver
#
Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf
+ Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.inf
#
# Usb Support
diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Durian/DurianPkg.fdf
index 703537033944..1a1dde1c64f6 100644
--- a/Platform/Phytium/Durian/DurianPkg.fdf
+++ b/Platform/Phytium/Durian/DurianPkg.fdf
@@ -102,6 +102,7 @@ [FV.FvMain]
INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.inf
INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
diff --git a/Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.inf b/Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.inf
new file mode 100644
index 000000000000..3d177dd92c7e
--- /dev/null
+++ b/Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.inf
@@ -0,0 +1,72 @@
+#/** @file
+# Phytium NorFlash Fvb Drivers.
+#
+# Copyright (C) 2020, Phytium Technology Co,Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = PhytiumFlashFvbDxe
+ FILE_GUID = b8923820-3e7c-11eb-b12c-17525e90ecc8
+ MODULE_TYPE = DXE_RUNTIME_DRIVER
+ VERSION_STRING = 0.1
+ ENTRY_POINT = PhytiumFvbEntryPoint
+
+[Sources]
+ PhytiumFlashFvbDxe.c
+ PhytiumFlashFvbDxe.h
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/Phytium/Phytium.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ DevicePathLib
+ MemoryAllocationLib
+ UefiRuntimeServicesTableLib
+ IoLib
+ BaseLib
+ DebugLib
+ HobLib
+ UefiLib
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiRuntimeLib
+ DxeServicesTableLib
+ PcdLib
+
+[Guids]
+ gEfiSystemNvDataFvGuid
+ gEfiVariableGuid
+ gEfiEventVirtualAddressChangeGuid
+ gEfiAuthenticatedVariableGuid
+
+[Protocols]
+ gEfiDevicePathProtocolGuid
+ gEfiFirmwareVolumeBlockProtocolGuid
+ gPhytiumFlashProtocolGuid
+
+[Pcd.common]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashBase
+ gPhytiumPlatformTokenSpaceGuid.PcdSpiFlashSize
+
+[Depex]
+ #TRUE
+ gPhytiumFlashProtocolGuid
+ #gEfiCpuArchProtocolGuid AND
+ #gPhytiumSpiMasterProtocolGuid AND
+ #gPhytiumFlashProtocolGuid
diff --git a/Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.h b/Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.h
new file mode 100644
index 000000000000..6d7fe18e0137
--- /dev/null
+++ b/Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.h
@@ -0,0 +1,106 @@
+/** @file
+ Phytium NorFlash Fvb Drivers Header.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __FVB_FLASH_DXE_H__
+#define __FVB_FLASH_DXE_H__
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+#include <Protocol/PhytiumSpiNorFlash.h>
+
+#define GET_DATA_OFFSET(BaseAddr, Lba, LbaSize) ((BaseAddr) + (UINTN)((Lba) * (LbaSize)))
+#define FVB_FLASH_SIGNATURE SIGNATURE_32('S', 'n', 'o', 'r')
+#define INSTANCE_FROM_FVB_THIS(a) CR(a, FT_FVB_DEVICE, FvbProtocol, FVB_FLASH_SIGNATURE)
+
+typedef struct _FT_FVB_DEVICE FT_FVB_DEVICE;
+
+#define NOR_FLASH_ERASE_RETRY 10
+
+typedef struct {
+ VENDOR_DEVICE_PATH Vendor;
+ EFI_DEVICE_PATH_PROTOCOL End;
+ } FT_FVB_DEVICE_PATH;
+
+struct _FT_FVB_DEVICE {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+
+ UINTN DeviceBaseAddress;
+ UINTN RegionBaseAddress;
+ UINTN Size;
+ EFI_LBA StartLba;
+ EFI_BLOCK_IO_MEDIA Media;
+
+ EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
+
+ FT_FVB_DEVICE_PATH DevicePath;
+ EFI_NORFLASH_DRV_PROTOCOL *SpiFlashProtocol;
+ VOID *ShadowBuffer;
+ UINTN FvbSize;
+ };
+
+extern CONST EFI_GUID* CONST NorFlashVariableGuid;
+
+EFI_STATUS
+EFIAPI
+PhytiumFvbGetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ OUT EFI_FVB_ATTRIBUTES_2* Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+PhytiumFvbSetAttributes(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ IN OUT EFI_FVB_ATTRIBUTES_2* Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+PhytiumFvbGetPhysicalAddress(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ OUT EFI_PHYSICAL_ADDRESS* Address
+ );
+
+EFI_STATUS
+EFIAPI
+PhytiumFvbGetBlockSize(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ IN EFI_LBA Lba,
+ OUT UINTN* BlockSize,
+ OUT UINTN* NumberOfBlocks
+ );
+
+EFI_STATUS
+EFIAPI
+PhytiumFvbRead(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN* NumBytes,
+ IN OUT UINT8* Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PhytiumFvbWrite(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN* NumBytes,
+ IN UINT8* Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PhytiumFvbEraseBlocks(
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL* This,
+ ...
+ );
+
+#endif /* __FVB_FLASH_DXE_H__ */
diff --git a/Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.c b/Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.c
new file mode 100644
index 000000000000..a2ac7abe09ad
--- /dev/null
+++ b/Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.c
@@ -0,0 +1,1235 @@
+/** @file
+ Phytium NorFlash Fvb Drivers.
+
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeLib.h>
+
+#include <Guid/NvVarStoreFormatted.h>
+#include <Guid/SystemNvDataGuid.h>
+#include <Guid/VariableFormat.h>
+
+#include "PhytiumFlashFvbDxe.h"
+
+STATIC EFI_EVENT FvbVirtualAddrChangeEvent;
+STATIC FT_FVB_DEVICE *PhytiumFvbDevice;
+STATIC UINTN mFlashNvStorageVariableBase;
+CONST EFI_GUID* CONST NorFlashVariableGuid = &gEfiAuthenticatedVariableGuid;
+
+STATIC CONST FT_FVB_DEVICE PhytiumFvbFlashInstanceTemplate = {
+ FVB_FLASH_SIGNATURE, // Signature
+ NULL, // Handle ... NEED TO BE FILLED
+ 0, // DeviceBaseAddress ... NEED TO BE FILLED
+ 0, // RegionBaseAddress ... NEED TO BE FILLED
+ 0, // Size ... NEED TO BE FILLED
+ 0, // StartLba
+ {
+ 0, // MediaId ... NEED TO BE FILLED
+ FALSE, // RemovableMedia
+ TRUE, // MediaPresent
+ FALSE, // LogicalPartition
+ FALSE, // ReadOnly
+ FALSE, // WriteCaching;
+ 0, // BlockSize ... NEED TO BE FILLED
+ 4, // IoAlign
+ 0, // LastBlock ... NEED TO BE FILLED
+ 0, // LowestAlignedLba
+ 1, // LogicalBlocksPerPhysicalBlock
+ }, //Media;
+ {
+ PhytiumFvbGetAttributes, // GetAttributes
+ PhytiumFvbSetAttributes, // SetAttributes
+ PhytiumFvbGetPhysicalAddress, // GetPhysicalAddress
+ PhytiumFvbGetBlockSize, // GetBlockSize
+ PhytiumFvbRead, // Read
+ PhytiumFvbWrite, // Write
+ PhytiumFvbEraseBlocks, // EraseBlocks
+ NULL, // ParentHandle
+ }, // FvbProtoccol;
+
+ {
+ {
+ {
+ HARDWARE_DEVICE_PATH,
+ HW_VENDOR_DP,
+ { (UINT8)sizeof(VENDOR_DEVICE_PATH), (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8) }
+ },
+ { 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } }, // GUID ... NEED TO BE FILLED
+ },
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
+ }
+ }, // DevicePath
+
+ NULL, // SpiFlashProtocol ... NEED TO BE FILLED
+ NULL, // ShadowBuffer ... NEED TO BE FILLED
+ 0, // Fvb Size
+};
+
+
+/**
+ Erases a single block of flash.
+
+ @param[in] FlashInstance The poiter of the fvb device sturct.
+
+ @param[in] BlockAddress Physical address of Lba to be erased.
+
+ @retval EFI_SUCCESS The erase single block request successfully completed.
+
+**/
+STATIC
+EFI_STATUS
+FvbFlashEraseSingleBlock (
+ IN FT_FVB_DEVICE *FlashInstance,
+ IN UINTN BlockAddress
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ EFI_TPL OriginalTPL;
+
+ if (!EfiAtRuntime ()) {
+ // Raise TPL to TPL_HIGH to stop anyone from interrupting us.
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ } else {
+ // This initialization is only to prevent the compiler to complain about the
+ // use of uninitialized variables
+ OriginalTPL = TPL_HIGH_LEVEL;
+ }
+
+ Index = 0;
+ // The block erase might fail a first time (SW bug ?). Retry it ...
+ do {
+ Status = FlashInstance->SpiFlashProtocol->EraseSingleBlock(BlockAddress);
+ Index++;
+ } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED));
+
+ if (Index == NOR_FLASH_ERASE_RETRY) {
+ DEBUG((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n", BlockAddress,Index));
+ }
+
+ if (!EfiAtRuntime ()) {
+ // Interruptions can resume.
+ gBS->RestoreTPL (OriginalTPL);
+ }
+
+ return Status;
+}
+
+
+/**
+ Readed the specified number of bytes from the form the block to output buffer.
+
+ @param[in] FlashInstance The pointer of FT_FVB_DEVICE instance.
+
+ @param[in] Lba The starting logical block index to write to.
+
+ @param[in] Offset Offset into the block at which to begin writing.
+
+ @param[in] BufferSizeInBytes The number of bytes to be writed.
+
+ @param[out] Buffer The pointer to a caller-allocated buffer that
+ contains the source for the write.
+
+ @retval EFI_SUCCESS PhytiumFvbFlashRead() is executed successfully.
+
+**/
+STATIC
+EFI_STATUS
+PhytiumFvbFlashRead (
+ IN FT_FVB_DEVICE *FlashInstance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN BufferSizeInBytes,
+ OUT VOID *Buffer
+ )
+{
+ UINTN Address = GET_DATA_OFFSET(FlashInstance->RegionBaseAddress, Lba, FlashInstance->Media.BlockSize) + Offset;
+
+ if (BufferSizeInBytes == 0) {
+ return EFI_SUCCESS;
+ }
+
+ // The buffer must be valid
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ return FlashInstance->SpiFlashProtocol->Read (Address, Buffer, BufferSizeInBytes);
+}
+
+
+/**
+ Write a full or portion of a block. It must not span block boundaries; that is,
+ Offset + *NumBytes <= FlashInstance->Media.BlockSize.
+
+ @param[in] FlashInstance The pointer of FT_FVB_DEVICE instance.
+
+ @param[in] Lba The starting logical block index to write to.
+
+ @param[in] Offset Offset into the block at which to begin writing.
+
+ @param[in] BufferSizeInBytes The number of bytes to be writed.
+
+ @param[out] Buffer The pointer to a caller-allocated buffer that
+ contains the source for the write.
+
+ @retval EFI_SUCCESS PhytiumFvbWriteBlock() is executed successfully.
+
+ @retval EFI_BAD_BUFFER_SIZE The write spaned block boundaries.
+
+**/
+STATIC
+EFI_STATUS
+PhytiumFvbWriteBlock (
+ IN FT_FVB_DEVICE *FlashInstance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN BufferSizeInBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINTN BlockSize;
+ UINTN BlockAddress;
+
+ // Detect WriteDisabled state
+ if (FlashInstance->Media.ReadOnly == TRUE) {
+ DEBUG ((DEBUG_ERROR, "PhytiumFvbWriteBlock: ERROR - Can not write: Device is in WriteDisabled state.\n"));
+ // It is in WriteDisabled state, return an error right away
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = FlashInstance->Media.BlockSize;
+
+ // The write must not span block boundaries.
+ // We need to check each variable individually because adding two large values together overflows.
+ if ((Offset >= BlockSize) ||
+ (BufferSizeInBytes > BlockSize) ||
+ ((Offset + BufferSizeInBytes) > BlockSize)) {
+ DEBUG ((DEBUG_ERROR, "PhytiumFvbWriteBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, BufferSizeInBytes, BlockSize ));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // We must have some bytes to write
+ if (BufferSizeInBytes == 0) {
+ DEBUG ((DEBUG_ERROR, "PhytiumFvbWriteBlock: ERROR - EFI_BAD_BUFFER_SIZE: NumBytes == 0\n"));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // Check we did get some memory. Buffer is BlockSize.
+ if (FlashInstance->ShadowBuffer == NULL) {
+ DEBUG ((DEBUG_ERROR, "PhytiumFvbWriteBlock: ERROR - ShadowBuffer is NULL!\n"));
+ return EFI_DEVICE_ERROR;
+ }
+
+ //
+ // Write the word to NOR.
+ //
+ BlockAddress = GET_DATA_OFFSET(FlashInstance->RegionBaseAddress, Lba, FlashInstance->Media.BlockSize);
+
+ // Read NOR Flash data into shadow buffer
+ Status = FlashInstance->SpiFlashProtocol->Read (BlockAddress, FlashInstance->ShadowBuffer, BlockSize);
+ if (EFI_ERROR (Status)) {
+ // Return one of the pre-approved error statuses
+ return EFI_DEVICE_ERROR;
+ }
+
+ // Put the data at the appropriate location inside the buffer area
+ CopyMem ((VOID*)((UINTN)FlashInstance->ShadowBuffer + Offset), Buffer, BufferSizeInBytes);
+
+ Status = FlashInstance->SpiFlashProtocol->EraseSingleBlock (BlockAddress);
+ if (EFI_ERROR (Status)) {
+ // Return one of the pre-approved error statuses
+ return EFI_DEVICE_ERROR;
+ }
+
+ // Write the modified buffer back to the NorFlash
+ Status = FlashInstance->SpiFlashProtocol->Write(BlockAddress, FlashInstance->ShadowBuffer, BlockSize);
+ if (EFI_ERROR (Status)) {
+ // Return one of the pre-approved error statuses
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Writes the specified number of bytes from the input buffer to the block.
+
+ @param[in] FlashInstance The pointer of FT_FVB_DEVICE instance.
+
+ @param[in] Lba The starting logical block index to write to.
+
+ @param[in] Offset Offset into the block at which to begin writing.
+
+ @param[in] BufferSizeInBytes The number of bytes to be writed.
+
+ @param[in] Buffer The pointer to a caller-allocated buffer that
+ contains the source for the write.
+
+ @retval EFI_SUCCESS PhytiumFvbFlashWrite() is executed successfully.
+
+ @retval EFI_WRITE_PROTECTED Flash state is in the WriteDisabled state.
+
+ @retval EFI_INVALID_PARAMETER The pointer of Buffer is NULL.
+
+**/
+STATIC
+EFI_STATUS
+PhytiumFvbFlashWrite (
+ IN FT_FVB_DEVICE *FlashInstance,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN UINTN BufferSizeInBytes,
+ IN VOID *Buffer
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT32 BlockSize;
+ UINT32 BlockOffset;
+ UINTN RemainingBytes;
+ UINTN WriteSize;
+
+ if (FlashInstance->Media.ReadOnly == TRUE) {
+ return EFI_WRITE_PROTECTED;
+ }
+
+ if (BufferSizeInBytes == 0) {
+ return EFI_SUCCESS;
+ }
+
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ BlockSize = FlashInstance->Media.BlockSize;
+ BlockOffset = Offset;
+ RemainingBytes = BufferSizeInBytes;
+
+ // The write must not span block boundaries.
+ // We need to check each variable individually because adding two large values together overflows.
+ if (Offset >= BlockSize) {
+ DEBUG ((DEBUG_ERROR, "FvbFlashWrite: ERROR - EFI_BAD_BUFFER_SIZE: Offset=0x%x > BlockSize=0x%x\n", Offset, BlockSize));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // We must have some bytes to read
+ // Write either all the remaining bytes, or the number of bytes that bring
+ // us up to a block boundary, whichever is less.
+ // (DiskOffset | (BlockSize - 1)) + 1) rounds DiskOffset up to the next
+ // block boundary (even if it is already on one).
+ WriteSize = MIN (RemainingBytes, BlockSize - BlockOffset);
+
+ do {
+ Status = PhytiumFvbWriteBlock (FlashInstance, Lba, BlockOffset, WriteSize, Buffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Now continue writing either all the remaining bytes or single blocks.
+ RemainingBytes -= WriteSize;
+ Buffer = (UINT8 *) Buffer + WriteSize;
+ Lba++;
+ BlockOffset = 0;
+ WriteSize = MIN (RemainingBytes, BlockSize);
+ } while (RemainingBytes);
+
+ return Status;
+}
+
+
+/**
+ Initialises the FV Header and Variable Store Header
+ to support variable operations.
+
+ @param[in] Ptr Location to initialise the headers.
+
+ @retval EFI_SUCCESS PhytiumFvbInitFvAndVariableStoreHeaders()
+ is executed successfully.
+
+**/
+STATIC
+EFI_STATUS
+PhytiumFvbInitFvAndVariableStoreHeaders (
+ IN FT_FVB_DEVICE *FlashInstance
+ )
+{
+ EFI_STATUS Status;
+ VOID* Headers;
+ UINTN HeadersLength;
+ EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader;
+ VARIABLE_STORE_HEADER *VariableStoreHeader;
+
+ HeadersLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY) + sizeof(VARIABLE_STORE_HEADER);
+ Headers = AllocateZeroPool (HeadersLength);
+
+ // FirmwareVolumeHeader->FvLength is declared to have the Variable area AND the FTW working area AND the FTW Spare contiguous.
+ ASSERT(PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize) == PcdGet64(PcdFlashNvStorageFtwWorkingBase64));
+ ASSERT(PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) == PcdGet64(PcdFlashNvStorageFtwSpareBase64));
+
+ // Check if the size of the area is at least one block size
+ ASSERT((PcdGet32 (PcdFlashNvStorageVariableSize) > 0) && (PcdGet32 (PcdFlashNvStorageVariableSize) / FlashInstance->Media.BlockSize > 0));
+ ASSERT((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) > 0) && (PcdGet32 (PcdFlashNvStorageFtwWorkingSize) / FlashInstance->Media.BlockSize > 0));
+ ASSERT((PcdGet32 (PcdFlashNvStorageFtwSpareSize) > 0) && (PcdGet32 (PcdFlashNvStorageFtwSpareSize) / FlashInstance->Media.BlockSize > 0));
+
+ // Ensure the Variable area Base Addresses are aligned on a block size boundaries
+ ASSERT(PcdGet64 (PcdFlashNvStorageVariableBase64) % FlashInstance->Media.BlockSize == 0);
+ ASSERT(PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) % FlashInstance->Media.BlockSize == 0);
+ ASSERT(PcdGet64 (PcdFlashNvStorageFtwSpareBase64) % FlashInstance->Media.BlockSize == 0);
+
+ //
+ // EFI_FIRMWARE_VOLUME_HEADER
+ //
+ FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers;
+ CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid);
+ FirmwareVolumeHeader->FvLength = FlashInstance->FvbSize;
+
+ FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
+ FirmwareVolumeHeader->Attributes = (EFI_FVB_ATTRIBUTES_2) (
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
+ EFI_FVB2_ERASE_POLARITY | // After erasure all bits take this value (i.e. '1')
+ EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
+ EFI_FVB2_WRITE_ENABLED_CAP // Writes may be enabled
+ );
+
+ FirmwareVolumeHeader->HeaderLength = sizeof(EFI_FIRMWARE_VOLUME_HEADER) + sizeof(EFI_FV_BLOCK_MAP_ENTRY);
+ FirmwareVolumeHeader->Revision = EFI_FVH_REVISION;
+ FirmwareVolumeHeader->BlockMap[0].NumBlocks = FlashInstance->Media.LastBlock + 1;
+ FirmwareVolumeHeader->BlockMap[0].Length = FlashInstance->Media.BlockSize;
+ FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
+ FirmwareVolumeHeader->BlockMap[1].Length = 0;
+ FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ((UINT16*)FirmwareVolumeHeader, FirmwareVolumeHeader->HeaderLength);
+
+ //
+ // VARIABLE_STORE_HEADER
+ //
+ VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)Headers + FirmwareVolumeHeader->HeaderLength);
+ CopyGuid (&VariableStoreHeader->Signature, NorFlashVariableGuid);
+ VariableStoreHeader->Size = PcdGet32 (PcdFlashNvStorageVariableSize) - FirmwareVolumeHeader->HeaderLength;
+ VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED;
+ VariableStoreHeader->State = VARIABLE_STORE_HEALTHY;
+
+ // Install the combined super-header in the NorFlash
+ Status = PhytiumFvbWrite (&FlashInstance->FvbProtocol, 0, 0, &HeadersLength, Headers);
+
+ FreePool (Headers);
+
+ return Status;
+}
+
+
+/**
+ Check the integrity of firmware volume header.
+
+ @param[in] FwVolHeader A pointer to a firmware volume header
+
+ @retval EFI_SUCCESS The firmware volume is consistent
+
+ @retval EFI_NOT_FOUND The firmware volume has been corrupted.
+
+**/
+STATIC
+EFI_STATUS
+PhytiumFvbValidateFvHeader (
+ IN FT_FVB_DEVICE *FlashInstance
+ )
+{
+ UINT16 Checksum;
+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
+ VARIABLE_STORE_HEADER *VariableStoreHeader;
+ UINTN VariableStoreLength;
+ UINTN FvLength;
+
+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)GET_DATA_OFFSET(FlashInstance->RegionBaseAddress, FlashInstance->StartLba, FlashInstance->Media.BlockSize);
+ FvLength = FlashInstance->FvbSize;
+
+ //
+ // Verify the header revision, header signature, length
+ // Length of FvBlock cannot be 2**64-1
+ // HeaderLength cannot be an odd number
+ //
+ if ((FwVolHeader->Revision != EFI_FVH_REVISION) ||
+ (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ||
+ (FwVolHeader->FvLength != FvLength))
+ {
+ DEBUG ((DEBUG_ERROR, "ValidateFvHeader: No Firmware Volume header present\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ // Check the Firmware Volume Guid
+ if( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid) == FALSE ) {
+ DEBUG ((DEBUG_ERROR, "ValidateFvHeader: Firmware Volume Guid non-compatible\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ // Verify the header checksum
+ Checksum = CalculateSum16 ((UINT16*)FwVolHeader, FwVolHeader->HeaderLength);
+ if (Checksum != 0) {
+ DEBUG ((DEBUG_ERROR, "ValidateFvHeader: FV checksum is invalid (Checksum:0x%X)\n",Checksum));
+ return EFI_NOT_FOUND;
+ }
+
+ VariableStoreHeader = (VARIABLE_STORE_HEADER*)((UINTN)FwVolHeader + FwVolHeader->HeaderLength);
+
+ // Check the Variable Store Guid
+ if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) &&
+ !CompareGuid (&VariableStoreHeader->Signature,
+ &gEfiAuthenticatedVariableGuid)) {
+ DEBUG ((DEBUG_ERROR, "%a: Variable Store Guid non-compatible\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - FwVolHeader->HeaderLength;
+ if (VariableStoreHeader->Size != VariableStoreLength) {
+ DEBUG ((DEBUG_ERROR, "ValidateFvHeader: Variable Store Length does not match\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ The PhytiumFvbGetAttributes() function retrieves the attributes and
+ current settings of the block.
+
+ @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and
+ current settings are returned.
+ Type EFI_FVB_ATTRIBUTES_2 is defined in
+ EFI_FIRMWARE_VOLUME_HEADER.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+**/
+EFI_STATUS
+EFIAPI
+PhytiumFvbGetAttributes (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;
+ CONST FT_FVB_DEVICE *FlashInstance;
+
+ FlashInstance = INSTANCE_FROM_FVB_THIS(This);
+
+ FlashFvbAttributes = (EFI_FVB_ATTRIBUTES_2) (
+
+ EFI_FVB2_READ_ENABLED_CAP | // Reads may be enabled
+ EFI_FVB2_READ_STATUS | // Reads are currently enabled
+ EFI_FVB2_STICKY_WRITE | // A block erase is required to flip bits into EFI_FVB2_ERASE_POLARITY
+ EFI_FVB2_MEMORY_MAPPED | // It is memory mapped
+ EFI_FVB2_ERASE_POLARITY // After erasure all bits take this value (i.e. '1')
+
+ );
+
+ // Check if it is write protected
+ if (FlashInstance->Media.ReadOnly != TRUE) {
+
+ FlashFvbAttributes = FlashFvbAttributes |
+ EFI_FVB2_WRITE_STATUS | // Writes are currently enabled
+ EFI_FVB2_WRITE_ENABLED_CAP; // Writes may be enabled
+ }
+
+ *Attributes = FlashFvbAttributes;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ The PhytiumFvbSetAttributes() function sets configurable firmware volume attributes
+ and returns the new settings of the firmware volume.
+
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Attributes On input, Attributes is a pointer to
+ EFI_FVB_ATTRIBUTES_2 that contains the desired
+ firmware volume settings.
+ On successful return, it contains the new
+ settings of the firmware volume.
+
+ @retval EFI_SUCCESS The firmware volume attributes were returned.
+
+ @retval EFI_INVALID_PARAMETER The attributes requested are in conflict with
+ the capabilities as declared in the firmware
+ volume header.
+
+**/
+EFI_STATUS
+EFIAPI
+PhytiumFvbSetAttributes (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ The PhytiumFvbGetPhysicalAddress() function retrieves the base address of
+ a memory-mapped firmware volume. This function should be called
+ only for memory-mapped firmware volumes.
+
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Address Pointer to a caller-allocated
+ EFI_PHYSICAL_ADDRESS that, on successful
+ return from GetPhysicalAddress(), contains the
+ base address of the firmware volume.
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.
+
+**/
+EFI_STATUS
+EFIAPI
+PhytiumFvbGetPhysicalAddress (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
+ )
+{
+ FT_FVB_DEVICE *FlashInstance;
+
+ ASSERT (Address != NULL);
+
+ FlashInstance = INSTANCE_FROM_FVB_THIS (This);
+
+ *Address = mFlashNvStorageVariableBase;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ The PhytiumFvbGetBlockSize() function retrieves the size of the requested
+ block. It also returns the number of additional blocks with
+ the identical size. The PhytiumFvbGetBlockSize() function is used to
+ retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
+
+
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba Indicates the block whose size to return.
+
+ @param BlockSize Pointer to a caller-allocated UINTN in which
+ the size of the block is returned.
+
+ @param NumberOfBlocks Pointer to a caller-allocated UINTN in
+ which the number of consecutive blocks,
+ starting with Lba, is returned. All
+ blocks in this range have a size of
+ BlockSize.
+
+
+ @retval EFI_SUCCESS The firmware volume base address was returned.
+
+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
+
+**/
+EFI_STATUS
+EFIAPI
+PhytiumFvbGetBlockSize (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
+ )
+{
+ EFI_STATUS Status;
+ FT_FVB_DEVICE *FlashInstance;
+
+ FlashInstance = INSTANCE_FROM_FVB_THIS(This);
+
+ if (Lba > FlashInstance->Media.LastBlock) {
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ // This is easy because in this platform each NorFlash device has equal sized blocks.
+ *BlockSize = (UINTN) FlashInstance->Media.BlockSize;
+ *NumberOfBlocks = (UINTN) (FlashInstance->Media.LastBlock - Lba + 1);
+ Status = EFI_SUCCESS;
+ }
+
+ return Status;
+}
+
+
+/**
+ Reads the specified number of bytes into a buffer from the specified block.
+
+ The PhytiumFvbRead() function reads the requested number of bytes from the
+ requested block and stores them in the provided buffer.
+ Implementations should be mindful that the firmware volume
+ might be in the ReadDisabled state. If it is in this state,
+ the PhytiumFvbRead() function must return the status code
+ EFI_ACCESS_DENIED without modifying the contents of the
+ buffer. The PhytiumFvbRead() function must also prevent spanning block
+ boundaries. If a read is requested that would span a block
+ boundary, the read must read up to the boundary but not
+ beyond. The output parameter NumBytes must be set to correctly
+ indicate the number of bytes actually read. The caller must be
+ aware that a read may be partially completed.
+
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index from which to read.
+
+ @param Offset Offset into the block at which to begin reading.
+
+ @param NumBytes Pointer to a UINTN.
+ At entry, *NumBytes contains the total size of the
+ buffer.
+ At exit, *NumBytes contains the total number of
+ bytes read.
+
+ @param Buffer Pointer to a caller-allocated buffer that will be
+ used to hold the data that is read.
+
+ @retval EFI_SUCCESS The firmware volume was read successfully, and
+ contents are in Buffer.
+
+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.
+ On output, NumBytes contains the total number of
+ bytes returned in Buffer.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and
+ could not be read.
+**/
+EFI_STATUS
+EFIAPI
+PhytiumFvbRead (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
+ )
+{
+ UINTN BlockSize;
+ FT_FVB_DEVICE *FlashInstance;
+ EFI_STATUS Status;
+
+ FlashInstance = INSTANCE_FROM_FVB_THIS(This);
+
+ // Cache the block size to avoid de-referencing pointers all the time
+ BlockSize = FlashInstance->Media.BlockSize;
+
+ // The read must not span block boundaries.
+ // We need to check each variable individually because adding two large values together overflows.
+ if ((Offset >= BlockSize) ||
+ (*NumBytes > BlockSize) ||
+ ((Offset + *NumBytes) > BlockSize)) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ // We must have some bytes to read
+ if (*NumBytes == 0) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ Status = PhytiumFvbFlashRead (FlashInstance, FlashInstance->StartLba + Lba, Offset, *NumBytes, Buffer);
+ if (EFI_ERROR (Status)) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Writes the specified number of bytes from the input buffer to the block.
+
+ The PhytiumFvbWrite() function writes the specified number of bytes from
+ the provided buffer to the specified block and offset. If the
+ firmware volume is sticky write, the caller must ensure that
+ all the bits of the specified range to write are in the
+ EFI_FVB_ERASE_POLARITY state before calling the PhytiumFvbWrite()
+ function, or else the result will be unpredictable. This
+ unpredictability arises because, for a sticky-write firmware
+ volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
+ state but cannot flip it back again. Before calling the
+ PhytiumFvbWrite() function, it is recommended for the caller to
+ first call the PhytiumFvbEraseBlocks() function to erase the specified
+ block to write. A block erase cycle will transition bits from
+ the (NOT)EFI_FVB_ERASE_POLARITY state back to the
+ EFI_FVB_ERASE_POLARITY state. Implementations should be
+ mindful that the firmware volume might be in the WriteDisabled
+ state. If it is in this state, the PhytiumFvbWrite() function must
+ return the status code EFI_ACCESS_DENIED without modifying the
+ contents of the firmware volume. The PhytiumFvbWrite() function must
+ also prevent spanning block boundaries. If a write is
+ requested that spans a block boundary, the write must store up
+ to the boundary but not beyond. The output parameter NumBytes
+ must be set to correctly indicate the number of bytes actually
+ written. The caller must be aware that a write may be
+ partially completed. All writes, partial or otherwise, must be
+ fully flushed to the hardware before the PhytiumFvbWrite() service
+ returns.
+
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
+
+ @param Lba The starting logical block index to write to.
+
+ @param Offset Offset into the block at which to begin writing.
+
+ @param NumBytes The pointer to a UINTN.
+ At entry, *NumBytes contains the total size of the
+ buffer.
+ At exit, *NumBytes contains the total number of
+ bytes actually written.
+
+ @param Buffer The pointer to a caller-allocated buffer that
+ contains the source for the write.
+
+ @retval EFI_SUCCESS The firmware volume was written successfully.
+
+ @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA boundary.
+ On output, NumBytes contains the total number of
+ bytes actually written.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled state.
+
+ @retval EFI_DEVICE_ERROR The block device is malfunctioning and could not be
+ written.
+
+**/
+EFI_STATUS
+EFIAPI
+PhytiumFvbWrite (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ FT_FVB_DEVICE *FlashInstance;
+
+ FlashInstance = INSTANCE_FROM_FVB_THIS (This);
+
+ return PhytiumFvbFlashWrite (FlashInstance, FlashInstance->StartLba + Lba, Offset, *NumBytes, Buffer);
+}
+
+
+/**
+ Erases and initialises a firmware volume block.
+
+ The PhytiumFvbEraseBlocks() function erases one or more blocks as denoted
+ by the variable argument list. The entire parameter list of
+ blocks must be verified before erasing any blocks. If a block is
+ requested that does not exist within the associated firmware
+ volume (it has a larger index than the last block of the
+ firmware volume), the PhytiumFvbEraseBlocks() function must return the
+ status code EFI_INVALID_PARAMETER without modifying the contents
+ of the firmware volume. Implementations should be mindful that
+ the firmware volume might be in the WriteDisabled state. If it
+ is in this state, the PhytiumFvbEraseBlocks() function must return the
+ status code EFI_ACCESS_DENIED without modifying the contents of
+ the firmware volume. All calls to PhytiumFvbEraseBlocks() must be fully
+ flushed to the hardware before the PhytiumFvbEraseBlocks() service
+ returns.
+
+ @param This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
+ instance.
+
+ @param ... The variable argument list is a list of tuples.
+ Each tuple describes a range of LBAs to erase
+ and consists of the following:
+ An EFI_LBA that indicates the starting LBA
+ A UINTN that indicates the number of blocks
+ to erase.
+
+ The list is terminated with an
+ EFI_LBA_LIST_TERMINATOR.
+
+ @retval EFI_SUCCESS The erase request successfully completed.
+
+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled
+ state.
+
+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly
+ and could not be written.
+ The firmware device may have been partially
+ erased.
+
+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable
+ argument list do not exist in the firmware
+ volume.
+
+**/
+EFI_STATUS
+EFIAPI
+PhytiumFvbEraseBlocks (
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ ...
+ )
+{
+ EFI_STATUS Status;
+ VA_LIST Args;
+ UINTN BlockAddress; // Physical address of Lba to erase
+ EFI_LBA StartingLba; // Lba from which we start erasing
+ UINTN NumOfLba; // Number of Lba blocks to erase
+ FT_FVB_DEVICE *Instance;
+
+ Instance = INSTANCE_FROM_FVB_THIS(This);
+
+ Status = EFI_SUCCESS;
+
+ // Detect WriteDisabled state
+ if (Instance->Media.ReadOnly == TRUE) {
+ // Firmware volume is in WriteDisabled state
+ DEBUG ((DEBUG_ERROR, "FvbEraseBlocks: ERROR - Device is in WriteDisabled state.\n"));
+ return EFI_ACCESS_DENIED;
+ }
+
+ // Before erasing, check the entire list of parameters to ensure all specified blocks are valid
+
+ VA_START (Args, This);
+ do {
+ // Get the Lba from which we start erasing
+ StartingLba = VA_ARG (Args, EFI_LBA);
+
+ // Have we reached the end of the list?
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
+ //Exit the while loop
+ break;
+ }
+
+ // How many Lba blocks are we requested to erase?
+ NumOfLba = VA_ARG (Args, UINT32);
+
+ // All blocks must be within range
+ if ((NumOfLba == 0) || ((Instance->StartLba + StartingLba + NumOfLba - 1) > Instance->Media.LastBlock)) {
+ VA_END (Args);
+ DEBUG ((DEBUG_ERROR, "FvbEraseBlocks: ERROR - Lba range goes past the last Lba.\n"));
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
+ } while (TRUE);
+ VA_END (Args);
+
+ //
+ // To get here, all must be ok, so start erasing
+ //
+ VA_START (Args, This);
+ do {
+ // Get the Lba from which we start erasing
+ StartingLba = VA_ARG (Args, EFI_LBA);
+
+ // Have we reached the end of the list?
+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
+ // Exit the while loop
+ break;
+ }
+
+ // How many Lba blocks are we requested to erase?
+ NumOfLba = VA_ARG (Args, UINT32);
+
+ // Go through each one and erase it
+ while (NumOfLba > 0) {
+
+ // Get the physical address of Lba to erase
+ BlockAddress = GET_DATA_OFFSET (
+ Instance->RegionBaseAddress,
+ Instance->StartLba + StartingLba,
+ Instance->Media.BlockSize
+ );
+
+ // Erase it
+ Status = FvbFlashEraseSingleBlock (Instance, BlockAddress);
+ if (EFI_ERROR(Status)) {
+ VA_END (Args);
+ Status = EFI_DEVICE_ERROR;
+ goto EXIT;
+ }
+
+ // Move to the next Lba
+ StartingLba++;
+ NumOfLba--;
+ }
+ } while (TRUE);
+
+ VA_END (Args);
+
+EXIT:
+ return Status;
+}
+
+
+//extern const UINT64 _gPcd_FixedAtBuild_PcdSpiControllerBase;
+//extern const UINT64 _gPcd_FixedAtBuild_PcdSpiControllerSize;
+//#define SPI_CONTROLLER_BASE _gPcd_FixedAtBuild_PcdSpiControllerBase
+//#define SPI_CONTROLLER_SIZE _gPcd_FixedAtBuild_PcdSpiControllerSize
+
+/**
+ This function inited the NorFlash instance.
+
+ @param[in][out] FlashInstance The pointer of FT_FVB_DEVICE instance.
+
+ @retval EFI_SUCCESS PhytNorFlashFvbInitialize() is executed successfully.
+
+**/
+STATIC
+EFI_STATUS
+PhytNorFlashFvbInitialize (
+ IN OUT FT_FVB_DEVICE *FlashInstance
+ )
+{
+ EFI_STATUS Status;
+ UINT32 FvbNumLba;
+ EFI_BOOT_MODE BootMode;
+ UINTN TotalFvbSize;
+
+ mFlashNvStorageVariableBase = FixedPcdGet64 (PcdFlashNvStorageVariableBase64);
+
+ // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME
+
+ // Note: all the NOR Flash region needs to be reserved into the UEFI Runtime memory;
+ // even if we only use the small block region at the top of the NOR Flash.
+ // The reason is when the NOR Flash memory is set into program mode, the command
+ // is written as the base of the flash region (ie: FlashInstance->DeviceBaseAddress)
+ // Todo: SPI control block should be remapped, otherwise ...
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeMemoryMappedIo,
+ mFlashNvStorageVariableBase, FlashInstance->FvbSize,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gDS->SetMemorySpaceAttributes (
+ mFlashNvStorageVariableBase, FlashInstance->FvbSize,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ TotalFvbSize = FlashInstance->FvbSize;
+
+ // Set the index of the first LBA for the FVB
+ FlashInstance->StartLba = (PcdGet64 (PcdFlashNvStorageVariableBase64) - FlashInstance->RegionBaseAddress) / FlashInstance->Media.BlockSize;
+
+ BootMode = GetBootModeHob ();
+ if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) {
+ Status = EFI_INVALID_PARAMETER;
+ } else {
+ // Determine if there is a valid header at the beginning of the NorFlash
+ Status = PhytiumFvbValidateFvHeader (FlashInstance);
+ }
+
+ // Install the Default FVB header if required
+ if (EFI_ERROR(Status)) {
+ // There is no valid header, so time to install one.
+ DEBUG((DEBUG_ERROR,"NorFlashFvbInitialize: ERROR - The FVB Header is invalid. Installing a correct one for this volume.\n"));
+
+ // Erase all the NorFlash that is reserved for variable storage
+ FvbNumLba = TotalFvbSize / FlashInstance->Media.BlockSize;
+
+ Status = PhytiumFvbEraseBlocks (&FlashInstance->FvbProtocol, (EFI_LBA)0, FvbNumLba, EFI_LBA_LIST_TERMINATOR);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // Install all appropriate headers
+ Status = PhytiumFvbInitFvAndVariableStoreHeaders (FlashInstance);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ }
+
+ return Status;
+}
+
+
+/**
+ The CreateInstance() function Create Fvb Instance.
+
+ @retval EFI_SUCCESS Create Instance successfully.
+
+ @retval other Create Instance failed.
+
+**/
+STATIC
+EFI_STATUS
+CreateInstance (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ NOR_FLASH_DEVICE_DESCRIPTION *NorFlashDevice;
+
+ // Locate flash protocols
+ Status = gBS->LocateProtocol (&gPhytiumFlashProtocolGuid,
+ NULL,
+ (VOID **)&PhytiumFvbDevice->SpiFlashProtocol);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Cannot locate NorFlash protocol.\n"));
+ return Status;
+ }
+
+ NorFlashDevice = AllocateRuntimePool(sizeof(NOR_FLASH_DEVICE_DESCRIPTION));
+ if (NorFlashDevice == NULL) {
+ DEBUG ((DEBUG_ERROR, "Cannot Allocate NorFlashDevice Pool.\n"));
+ return Status;
+ }
+
+ Status = PhytiumFvbDevice->SpiFlashProtocol->GetDevices (NorFlashDevice);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = PhytiumFvbDevice->SpiFlashProtocol->Initialization();
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ PhytiumFvbDevice->DeviceBaseAddress = NorFlashDevice->DeviceBaseAddress;
+ PhytiumFvbDevice->RegionBaseAddress = NorFlashDevice->RegionBaseAddress;
+ PhytiumFvbDevice->Size = NorFlashDevice->Size;
+
+ PhytiumFvbDevice->Media.MediaId = 0;
+ PhytiumFvbDevice->Media.BlockSize = NorFlashDevice->BlockSize;
+ PhytiumFvbDevice->Media.LastBlock = (PhytiumFvbDevice->Size / PhytiumFvbDevice->Media.BlockSize) - 1;
+ PhytiumFvbDevice->FvbSize = PcdGet32 (PcdFlashNvStorageVariableSize) +
+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ PcdGet32 (PcdFlashNvStorageFtwSpareSize);
+ DEBUG ((DEBUG_INFO, "%a: line at %d, DeviceBaseAddress=%x,PhytiumFvbDevice->Size=%x\n", __FUNCTION__, __LINE__, PhytiumFvbDevice->DeviceBaseAddress, PhytiumFvbDevice->Size));
+
+ CopyGuid (&PhytiumFvbDevice->DevicePath.Vendor.Guid, &NorFlashDevice->Guid);
+
+ PhytiumFvbDevice->ShadowBuffer = AllocateRuntimePool (PhytiumFvbDevice->Media.BlockSize);
+ if (PhytiumFvbDevice->ShadowBuffer == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &PhytiumFvbDevice->Handle,
+ &gEfiDevicePathProtocolGuid, &PhytiumFvbDevice->DevicePath,
+ &gEfiFirmwareVolumeBlockProtocolGuid, &PhytiumFvbDevice->FvbProtocol,
+ NULL
+ );
+ if (EFI_ERROR(Status)) {
+ FreePool (PhytiumFvbDevice);
+ return Status;
+ }
+
+ Status = PhytNorFlashFvbInitialize(PhytiumFvbDevice);
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "PhytNorFlashFvbInitialize: Fail to init NorFlash devices\n"));
+ return Status;
+ }
+
+ FreePool(NorFlashDevice);
+
+ return Status;
+}
+
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in lib to virtual mode.
+
+ @param[in] Event The Event that is being processed.
+
+ @param[in] Context Event Context.
+
+ @retval None.
+
+**/
+STATIC
+VOID
+EFIAPI
+PhytiumFvbVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ // Convert SpiFlashProtocol
+ EfiConvertPointer (0x0, (VOID**)&PhytiumFvbDevice->SpiFlashProtocol->Erase);
+ EfiConvertPointer (0x0, (VOID**)&PhytiumFvbDevice->SpiFlashProtocol->Write);
+ EfiConvertPointer (0x0, (VOID**)&PhytiumFvbDevice->SpiFlashProtocol->Read);
+ EfiConvertPointer (0x0, (VOID**)&PhytiumFvbDevice->SpiFlashProtocol->GetDevices);
+ EfiConvertPointer (0x0, (VOID**)&PhytiumFvbDevice->SpiFlashProtocol->Initialization);
+ EfiConvertPointer (0x0, (VOID**)&PhytiumFvbDevice->SpiFlashProtocol->EraseSingleBlock);
+ EfiConvertPointer (0x0, (VOID**)&PhytiumFvbDevice->SpiFlashProtocol);
+
+ EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase);
+ EfiConvertPointer (0x0, (VOID**)&PhytiumFvbDevice);
+
+ return;
+}
+
+
+/**
+ This function is the entrypoint of the fvb driver.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The entry point is executed successfully.
+
+ @retval other Some error occurs when executing this entry point.
+
+**/
+EFI_STATUS
+EFIAPI
+PhytiumFvbEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ PhytiumFvbDevice = AllocateRuntimeCopyPool (sizeof(PhytiumFvbFlashInstanceTemplate), &PhytiumFvbFlashInstanceTemplate);
+ if (PhytiumFvbDevice == NULL) {
+ DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Status = CreateInstance ();
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "CreateInstance: Fail to create instance for NorFlash\n"));
+ }
+
+//
+// Register for the virtual address change event
+//
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ PhytiumFvbVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &FvbVirtualAddrChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v1 10/10] Silicon/Phytium: Added Rtc driver to Phytium2000-4
2021-01-15 8:47 added support for DurianPkg Ling Jia
` (8 preceding siblings ...)
2021-01-15 8:48 ` [PATCH v1 09/10] Silicon/Phytium: Added fvb driver for norflash Ling Jia
@ 2021-01-15 8:48 ` Ling Jia
2021-01-22 12:04 ` added support for DurianPkg Leif Lindholm
2021-03-12 20:50 ` [edk2-devel] " Laszlo Ersek
11 siblings, 0 replies; 15+ messages in thread
From: Ling Jia @ 2021-01-15 8:48 UTC (permalink / raw)
To: devel; +Cc: Leif Lindholm, Ling, Peng Xie, Yiqi Shu
From: Ling <jialing@phytium.com.cn>
The PhytiumRealTimeClockLib implemented EFI RealTimeClock
runtime services via RTC Lib.
Cc: Leif Lindholm <leif@nuviainc.com>
Signed-off-by: Ling Jia <jialing@phytium.com.cn>
Signed-off-by: Peng Xie <xiepeng@phytium.com.cn>
Reviewed-by: Yiqi Shu <shuyiqi@phytium.com.cn>
---
Platform/Phytium/Durian/DurianPkg.dsc | 3 +
Platform/Phytium/Durian/DurianPkg.fdf | 1 +
Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.inf | 44 ++
Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.h | 24 +
Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.c | 468 ++++++++++++++++++++
5 files changed, 540 insertions(+)
diff --git a/Platform/Phytium/Durian/DurianPkg.dsc b/Platform/Phytium/Durian/DurianPkg.dsc
index df43c3d5d23a..dae2ca512a26 100644
--- a/Platform/Phytium/Durian/DurianPkg.dsc
+++ b/Platform/Phytium/Durian/DurianPkg.dsc
@@ -30,6 +30,8 @@ [LibraryClasses.common]
ArmPlatformLib|Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf
LogoLib|Silicon/Phytium/Library/LogoLib/LogoLib.inf
+ #Phytium2000-4 RTC Driver
+ RealTimeClockLib|Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.inf
TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
# PL011 UART Driver and Dependency Libraries
@@ -180,6 +182,7 @@ [Components.common]
}
MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
#
# Common Arm Timer and Gic Components
diff --git a/Platform/Phytium/Durian/DurianPkg.fdf b/Platform/Phytium/Durian/DurianPkg.fdf
index 1a1dde1c64f6..82b2723a8490 100644
--- a/Platform/Phytium/Durian/DurianPkg.fdf
+++ b/Platform/Phytium/Durian/DurianPkg.fdf
@@ -94,6 +94,7 @@ [FV.FvMain]
#INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.inf b/Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.inf
new file mode 100644
index 000000000000..8919cbf55a06
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.inf
@@ -0,0 +1,44 @@
+#/** @file
+# Phytium RealTime Clock Library file.
+#
+# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010019
+ BASE_NAME = PhytiumRealTimeClockLib
+ FILE_GUID = fb320c94-40fe-11eb-b990-171865af292c
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ PhytiumRealTimeClockLib.c
+ PhytiumRealTimeClockLib.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/Phytium/Phytium.dec
+
+[LibraryClasses]
+ IoLib
+ UefiLib
+ DebugLib
+ PcdLib
+ DxeServicesTableLib
+ TimeBaseLib
+ UefiRuntimeLib
+
+[Guids]
+ gEfiEventVirtualAddressChangeGuid
+
+[Pcd]
+ gPhytiumPlatformTokenSpaceGuid.PcdRtcBaseAddress
+
+[Depex.common.DXE_RUNTIME_DRIVER]
+ gEfiCpuArchProtocolGuid
diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.h b/Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.h
new file mode 100644
index 000000000000..1015d7bb08bf
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.h
@@ -0,0 +1,24 @@
+/** @file
+ Phytium RealTime Clock Header.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __XGENE_REAL_TIME_CLOCK_H__
+#define __XGENE_REAL_TIME_CLOCK_H__
+
+#define RTC_CMR 0x4
+#define RTC_AES_SEL 0x8
+#define RTC_CCR 0xC
+#define RTC_STAT 0x10
+#define RTC_RSTAT 0x14
+#define RTC_EOI 0x18
+#define RTC_CDR_LOW 0x20
+#define RTC_CCVR 0x24
+#define RTC_CLR_LOW 0x28
+#define RTC_CLR 0x2C
+
+#endif
diff --git a/Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.c b/Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.c
new file mode 100644
index 000000000000..606dd565a64a
--- /dev/null
+++ b/Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.c
@@ -0,0 +1,468 @@
+/** @file
+ Implement EFI RealTimeClock runtime services via RTC Lib.
+
+ Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+
+#include <Guid/EventGroup.h>
+#include <Guid/GlobalVariable.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/TimeBaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiRuntimeLib.h>
+#include <Protocol/RealTimeClock.h>
+#include "PhytiumRealTimeClockLib.h"
+
+
+STATIC EFI_EVENT mRtcVirtualAddrChangeEvent;
+STATIC UINTN mRtcBase;
+STATIC CONST CHAR16 mTimeZoneVariableName[] = L"RtcTimeZone";
+STATIC CONST CHAR16 mDaylightVariableName[] = L"RtcDaylight";
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+ @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ UINT32 EpochSeconds;
+ INT16 TimeZone;
+ UINT8 Daylight;
+ UINTN Size;
+ EFI_STATUS Status;
+
+ // Ensure Time is a valid pointer
+ if (Time == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ MmioWrite32(mRtcBase + RTC_AES_SEL, 0x100);
+ //
+ //read cdr high 32bit
+ //
+ EpochSeconds = MmioRead32 (mRtcBase + RTC_CCVR);
+ MmioRead32(mRtcBase + RTC_CDR_LOW);
+ //
+ // Get the current time zone information from non-volatile storage
+ //
+ Size = sizeof (TimeZone);
+ Status = EfiGetVariable (
+ (CHAR16 *)mTimeZoneVariableName,
+ &gEfiCallerIdGuid,
+ NULL,
+ &Size,
+ (VOID *)&TimeZone
+ );
+
+ if (EFI_ERROR (Status)) {
+ ASSERT(Status != EFI_INVALID_PARAMETER);
+ ASSERT(Status != EFI_BUFFER_TOO_SMALL);
+ //
+ // The time zone variable does not exist in non-volatile storage, so create it.
+ //UTC+8:00
+ //
+ Time->TimeZone = -480;
+ //
+ // Store it
+ //
+ Status = EfiSetVariable (
+ (CHAR16 *)mTimeZoneVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ Size,
+ (VOID *)&(Time->TimeZone)
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ } else {
+ //
+ // Got the time zone
+ //
+ Time->TimeZone = TimeZone;
+ //
+ // Check TimeZone bounds: -1440 to 1440 or 2047
+ //
+ if (((Time->TimeZone < -1440) || (Time->TimeZone > 1440))
+ && (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE)) {
+ Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
+ }
+ //
+ // Adjust for the correct time zone
+ //
+ if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) {
+ EpochSeconds -= Time->TimeZone * SEC_PER_MIN;
+ }
+ }
+ //
+ // Get the current daylight information from non-volatile storage
+ //
+ Size = sizeof (Daylight);
+ Status = EfiGetVariable (
+ (CHAR16 *)mDaylightVariableName,
+ &gEfiCallerIdGuid,
+ NULL,
+ &Size,
+ (VOID *)&Daylight
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT(Status != EFI_INVALID_PARAMETER);
+ ASSERT(Status != EFI_BUFFER_TOO_SMALL);
+ //
+ // The daylight variable does not exist in non-volatile storage, so create it.
+ //
+ Time->Daylight = 0;
+ //
+ // Store it
+ //
+ Status = EfiSetVariable (
+ (CHAR16 *)mDaylightVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ Size,
+ (VOID *)&(Time->Daylight)
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ } else {
+ //
+ // Got the daylight information
+ //
+ Time->Daylight = Daylight;
+ //
+ // Adjust for the correct period
+ //
+ if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) {
+ //
+ // Convert to adjusted time, i.e. spring forwards one hour
+ //
+ EpochSeconds += SEC_PER_HOUR;
+ }
+ }
+
+ //
+ // Convert from internal 32-bit time to UEFI time
+ //
+ EpochToEfiTime (EpochSeconds, Time);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Sets the current local time and date information.
+
+ @param[in] Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ UINTN EpochSeconds;
+ EFI_STATUS Status;
+ //
+ // the maximum time span is just over 136 years.
+ // Time is stored in Unix Epoch format, so it starts in 1970,
+ // Therefore it can not exceed the year 2106.
+ //
+ if ((Time->Year < 1970) || (Time->Year >= 2106)) {
+ return EFI_UNSUPPORTED;
+ }
+ EpochSeconds = EfiTimeToEpoch (Time);
+ //
+ // Adjust for the correct time zone, i.e. convert to UTC time zone
+ //
+ if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) {
+ EpochSeconds += Time->TimeZone * SEC_PER_MIN;
+ }
+ //
+ // Adjust for the correct period
+ //
+ if (((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT)
+ && (EpochSeconds > SEC_PER_HOUR)) {
+ //
+ // Convert to un-adjusted time, i.e. fall back one hour
+ //
+ EpochSeconds -= SEC_PER_HOUR;
+ }
+ //
+ // Set the Rtc
+ //
+ MmioWrite32(mRtcBase + RTC_AES_SEL, 0x100);
+ MmioWrite32 (mRtcBase + RTC_CLR_LOW, 0x0);
+ MmioWrite32 (mRtcBase + RTC_CLR, (UINT32)EpochSeconds);
+ //
+ // Save the current time zone information into non-volatile storage
+ //
+ Status = EfiSetVariable (
+ (CHAR16 *)mTimeZoneVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof (Time->TimeZone),
+ (VOID *)&(Time->TimeZone)
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Save the current daylight information into non-volatile storage
+ //
+ Status = EfiSetVariable (
+ (CHAR16 *)mDaylightVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof(Time->Daylight),
+ (VOID *)&(Time->Daylight)
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param[out] Enabled Indicates if the alarm is currently enabled or disabled.
+ @param[out] Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param[out] Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param[in] Enabled Enable or disable the wakeup alarm.
+ @param[out] Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ //
+ // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+ // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+ // to virtual address. After the OS transitions to calling in virtual mode, all future
+ // runtime calls will be made in virtual mode.
+ //
+ EfiConvertPointer (0x0, (VOID**)&mRtcBase);
+
+ return;
+}
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param[in] ImageHandle Handle that identifies the loaded image.
+ @param[in] SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ INT16 TimeZone;
+ UINTN Size;
+ EFI_TIME Time;
+ UINT8 Daylight;
+ //
+ // Initialize RTC Base Address
+ //
+ mRtcBase = PcdGet32(PcdRtcBaseAddress);
+ //
+ // Declare the controller as EFI_MEMORY_RUNTIME
+ //
+ Status = gDS->AddMemorySpace (
+ EfiGcdMemoryTypeMemoryMappedIo,
+ mRtcBase, SIZE_4KB,
+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ //init timezone
+ //
+ Size = sizeof (TimeZone);
+ Status = EfiGetVariable (
+ (CHAR16 *)mTimeZoneVariableName,
+ &gEfiCallerIdGuid,
+ NULL,
+ &Size,
+ (VOID *)&TimeZone
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT(Status != EFI_INVALID_PARAMETER);
+ ASSERT(Status != EFI_BUFFER_TOO_SMALL);
+ //
+ // The time zone variable does not exist in non-volatile storage, so create it.
+ //UTC 8:00
+ //
+ Time.TimeZone = -480;
+ //
+ // Store it
+ //
+ Status = EfiSetVariable (
+ (CHAR16 *)mTimeZoneVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ Size,
+ (VOID *)&(Time.TimeZone)
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+ //
+ //daylight init
+ //
+ Size = sizeof (Daylight);
+ Status = EfiGetVariable (
+ (CHAR16 *)mDaylightVariableName,
+ &gEfiCallerIdGuid,
+ NULL,
+ &Size,
+ (VOID *)&Daylight
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT(Status != EFI_INVALID_PARAMETER);
+ ASSERT(Status != EFI_BUFFER_TOO_SMALL);
+ //
+ // The daylight variable does not exist in non-volatile storage, so create it.
+ //
+ Time.Daylight = 0;
+ //
+ // Store it
+ //
+ Status = EfiSetVariable (
+ (CHAR16 *)mDaylightVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ Size,
+ (VOID *)&(Time.Daylight)
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ Status = gDS->SetMemorySpaceAttributes (mRtcBase, SIZE_4KB, EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Install the protocol
+ //
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiRealTimeClockArchProtocolGuid, NULL,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Register for the virtual address change event
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_NOTIFY,
+ LibRtcVirtualNotifyEvent,
+ NULL,
+ &gEfiEventVirtualAddressChangeGuid,
+ &mRtcVirtualAddrChangeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: added support for DurianPkg.
2021-01-15 8:47 added support for DurianPkg Ling Jia
` (9 preceding siblings ...)
2021-01-15 8:48 ` [PATCH v1 10/10] Silicon/Phytium: Added Rtc driver to Phytium2000-4 Ling Jia
@ 2021-01-22 12:04 ` Leif Lindholm
2021-03-12 20:50 ` [edk2-devel] " Laszlo Ersek
11 siblings, 0 replies; 15+ messages in thread
From: Leif Lindholm @ 2021-01-22 12:04 UTC (permalink / raw)
To: Ling Jia; +Cc: devel
Hi Ling,
Apologies for not responding sooner. As you can imagine, the news last
week that NUVIA was being acquired by Qualcomm has caused some
distractions.
I will get on with reviewing the individual patches, but I will start
by proposing some name changes and structure changes to better fit
with tianocore design principles.
First of all - the concept of "packages" is fairly central to edk2.
Any directory that contains a .dec file is a package, and this can be
more strongly indicated by giving the directory a name ending in Pkg.
Personally, I also tend to see directories containing .dsc/.fdf as
packages, even if they don't currently hold a .dec.
Platform
Phytium
DurianPkg
DurianPkg.dsc
DurianPkg.fdf
Silicon
Phytium
Phytium2000-4Pkg
Drivers
Include
Library
Protocol
Library
PhytiumCommonPkg
PhytiumCommon.dec
PhytiumCommon.dsc.inc
Drivers
Include
Library
Protocol
Library
Logo
You could then have a new Phytium2000-4Pkg.dec, to provide the
[Include] statement for that package.
Does this make sense?
On Fri, Jan 15, 2021 at 08:47:52 +0000, Ling Jia wrote:
> From: Ling <jialing@phytium.com.cn>
>
> The modules could be runed at the silicon of Phytium2000-4.
> They supported Acpi parameter configuration, Pci bus scaning,
> flash read-write and erase abd operating system boot function.
> Maintainers.txt: Added maintainers and reviewers for the DurianPkg.
>
> The public git repository is :
> https://github.com/jialing2020/edk2-platforms/tree/phytium_opensource_for_2004_v1
>
> *** BLURB HERE ***
You can delete this line - it's just there to remind you to write a
message :)
Best Regards,
Leif
>
> Ling (10):
> Silicon/Phytium/: added PhytiumPlatformLib to Phytium2000-4
> Silicon/Phytium: Added Acpi support to Phytium2000-4
> Silicon/Phytium: Added SMBIOS support to Phytium2000-4
> Silicon/Phytium/Phytium2000-4/Library: Added PciSegmentLib to
> Phytium2000-4
> Silicon/Phytium: Added PciHostBridgeLib to Phytium2000-4
> Silicon/Phytium: Added Logo support to Phytium Silicon
> Silicon/Phytium: Added Spi driver support to Phytium2000-4
> Silicon/Phytium: Added flash driver support to Phytium Silicon
> Silicon/Phytium: Added fvb driver for norflash
> Silicon/Phytium: Added Rtc driver to Phytium2000-4
>
> Silicon/Phytium/Phytium.dec | 60 +
> Silicon/Phytium/Phytium.dsc.inc | 388 ++++++
> Platform/Phytium/Durian/DurianPkg.dsc | 340 +++++
> Platform/Phytium/Durian/DurianPkg.fdf | 241 ++++
> Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.inf | 72 +
> Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf | 54 +
> Silicon/Phytium/Library/LogoLib/LogoLib.inf | 58 +
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf | 58 +
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf | 61 +
> Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf | 52 +
> Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 55 +
> Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 55 +
> Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.inf | 28 +
> Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf | 66 +
> Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.inf | 44 +
> Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.h | 106 ++
> Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.h | 106 ++
> Silicon/Phytium/Include/PhytiumPlatform.h | 93 ++
> Silicon/Phytium/Include/PhytiumSystemServiceInterface.h | 112 ++
> Silicon/Phytium/Include/Protocol/PhytiumSpi.h | 51 +
> Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h | 74 +
> Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.h | 73 +
> Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.h | 24 +
> Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.c | 1235 +++++++++++++++++
> Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.c | 435 ++++++
> Silicon/Phytium/Library/LogoLib/Logo.c | 133 ++
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatform.c | 254 ++++
> Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.c | 189 +++
> Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 959 +++++++++++++
> Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.c | 182 +++
> Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.c | 1440 ++++++++++++++++++++
> Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c | 135 ++
> Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c | 148 ++
> Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.c | 468 +++++++
> Maintainers.txt | 7 +
> Silicon/Phytium/Logo/PhytiumLogo.bmp | Bin 0 -> 32454 bytes
> Silicon/Phytium/Phytium.fdf.inc | 119 ++
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiSsdtRootPci.asl | 234 ++++
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dbg2.aslc | 85 ++
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Cpu.asl | 85 ++
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Dsdt.asl | 15 +
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Uart.asl | 65 +
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Fadt.aslc | 81 ++
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Gtdt.aslc | 87 ++
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Iort.aslc | 89 ++
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Madt.aslc | 66 +
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Mcfg.aslc | 69 +
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Pptt.aslc | 219 +++
> Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Spcr.aslc | 83 ++
> Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S | 76 ++
> 50 files changed, 9229 insertions(+)
> create mode 100644 Silicon/Phytium/Phytium.dec
> create mode 100644 Silicon/Phytium/Phytium.dsc.inc
> create mode 100644 Platform/Phytium/Durian/DurianPkg.dsc
> create mode 100644 Platform/Phytium/Durian/DurianPkg.fdf
> create mode 100644 Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.inf
> create mode 100644 Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.inf
> create mode 100644 Silicon/Phytium/Library/LogoLib/LogoLib.inf
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiTables.inf
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.inf
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
> create mode 100644 Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> create mode 100644 Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.inf
> create mode 100644 Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.inf
> create mode 100644 Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.inf
> create mode 100644 Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.h
> create mode 100644 Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.h
> create mode 100644 Silicon/Phytium/Include/PhytiumPlatform.h
> create mode 100644 Silicon/Phytium/Include/PhytiumSystemServiceInterface.h
> create mode 100644 Silicon/Phytium/Include/Protocol/PhytiumSpi.h
> create mode 100644 Silicon/Phytium/Include/Protocol/PhytiumSpiNorFlash.h
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.h
> create mode 100644 Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.h
> create mode 100644 Silicon/Phytium/CommonDrivers/PhytiumFlashFvbDxe/PhytiumFlashFvbDxe.c
> create mode 100644 Silicon/Phytium/CommonDrivers/PhytiumSpiNorFlashDxe/PhytiumSpiNorFlashDxe.c
> create mode 100644 Silicon/Phytium/Library/LogoLib/Logo.c
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiPlatformDxe/AcpiPlatform.c
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/PhytiumSpiDxe/PhytiumSpiDxe.c
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
> create mode 100644 Silicon/Phytium/Phytium2000-4/Library/PciHostBridgeLib/PciHostBridgeLib.c
> create mode 100644 Silicon/Phytium/Phytium2000-4/Library/PciSegmentLib/PciSegmentLib.c
> create mode 100644 Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLib.c
> create mode 100644 Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/PhytiumPlatformLibMem.c
> create mode 100644 Silicon/Phytium/Phytium2000-4/Library/PhytiumRealTimeClockLib/PhytiumRealTimeClockLib.c
> create mode 100644 Silicon/Phytium/Logo/PhytiumLogo.bmp
> create mode 100644 Silicon/Phytium/Phytium.fdf.inc
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/AcpiSsdtRootPci.asl
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dbg2.aslc
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Cpu.asl
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Dsdt.asl
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Dsdt/Uart.asl
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Fadt.aslc
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Gtdt.aslc
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Iort.aslc
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Madt.aslc
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Mcfg.aslc
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Pptt.aslc
> create mode 100644 Silicon/Phytium/Phytium2000-4/Drivers/AcpiTables/Spcr.aslc
> create mode 100644 Silicon/Phytium/Phytium2000-4/Library/PhytiumPlatformLib/AArch64/PhytiumPlatformHelper.S
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [edk2-devel] added support for DurianPkg.
2021-01-15 8:47 added support for DurianPkg Ling Jia
` (10 preceding siblings ...)
2021-01-22 12:04 ` added support for DurianPkg Leif Lindholm
@ 2021-03-12 20:50 ` Laszlo Ersek
11 siblings, 0 replies; 15+ messages in thread
From: Laszlo Ersek @ 2021-03-12 20:50 UTC (permalink / raw)
To: jialing; +Cc: devel, Leif Lindholm
Hi,
On 01/15/21 09:47, Ling Jia wrote:
> From: Ling <jialing@phytium.com.cn>
>
> The modules could be runed at the silicon of Phytium2000-4.
> They supported Acpi parameter configuration, Pci bus scaning,
> flash read-write and erase abd operating system boot function.
> Maintainers.txt: Added maintainers and reviewers for the DurianPkg.
>
> The public git repository is :
> https://github.com/jialing2020/edk2-platforms/tree/phytium_opensource_for_2004_v1
>
> *** BLURB HERE ***
when you posted this series (on Jan 15), an invitation was sent to you,
to join the edk2-devel mailing list.
You haven't subscribed yet, but I can see ~31 fresh patch emails pending
for you, in the moderation queue.
I'm not going to approve them until you subscribe. If you don't
subscribe, I cannot permanently un-moderate you, and everything you post
needs individual approval. That's a waste of the moderators' time, in
case the sender is a recurrent contributor. So please subscribe first.
I would be happy to add you directly (without you taking action) to the
subscriber list; however, gropus.io restricted the Direct Add feature to
higher level ($$$) service tiers, and so this admin feature is not
available on edk2-devel, unfortunately.
Thanks
Laszlo
^ permalink raw reply [flat|nested] 15+ messages in thread
