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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id 12sm11809361qkg.39.2021.01.31.15.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 31 Jan 2021 15:25:38 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 11/21] ArmPkg: Add Library/OemMiscLib.h Date: Sun, 31 Jan 2021 16:25:01 -0700 Message-Id: <20210131232511.18340-12-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210131232511.18340-1-rebecca@nuviainc.com> References: <20210131232511.18340-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit OemMiscLib.h provides the interface which platforms should implement to interact with the SmbiosMiscDxe and ProcessorSubClassDxe drivers to update SMBIOS tables. Signed-off-by: Rebecca Cran Acked-by: Leif Lindholm --- ArmPkg/Include/Library/OemMiscLib.h | 166 ++++++++++++++++++++ 1 file changed, 166 insertions(+) diff --git a/ArmPkg/Include/Library/OemMiscLib.h b/ArmPkg/Include/Library/OemMiscLib.h new file mode 100644 index 000000000000..a14eb36a60e3 --- /dev/null +++ b/ArmPkg/Include/Library/OemMiscLib.h @@ -0,0 +1,166 @@ +/** @file +* +* Copyright (c) 2021, NUVIA Inc. All rights reserved. +* Copyright (c) 2015, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015, Linaro Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +**/ + + +#ifndef OEM_MISC_LIB_H_ +#define OEM_MISC_LIB_H_ + +#include +#include + +typedef enum +{ + CpuCacheL1 = 0, + CpuCacheL2, + CpuCacheL3, + CpuCacheL4, + CpuCacheL5, + CpuCacheL6, + CpuCacheL7, + CpuCacheLevelMax +} OEM_MISC_CPU_CACHE_LEVEL; + +typedef struct +{ + UINT8 Voltage; ///< Processor voltage + UINT16 CurrentSpeed; ///< Current clock speed in MHz + UINT16 MaxSpeed; ///< Maximum clock speed in MHz + UINT16 ExternalClock; ///< External clock speed in MHz + UINT16 CoreCount; ///< Number of cores available + UINT16 CoresEnabled; ///< Number of cores enabled + UINT16 ThreadCount; ///< Number of threads per processor +} OEM_MISC_PROCESSOR_DATA; + +typedef enum +{ + ProductNameType01, + SerialNumType01, + UuidType01, + SystemManufacturerType01, + SkuNumberType01, + FamilyType01, + AssertTagType02, + SerialNumberType02, + BoardManufacturerType02, + SkuNumberType02, + ChassisLocationType02, + AssetTagType03, + SerialNumberType03, + VersionType03, + ChassisTypeType03, + ManufacturerType03, + SkuNumberType03, + SmbiosHiiStringFieldMax +} OEM_MISC_SMBIOS_HII_STRING_FIELD; + +/* + * The following are functions that the each platform needs to + * implement in its OemMiscLib library. + */ + +/** Gets the CPU frequency of the specified processor. + + @param ProcessorIndex Index of the processor to get the frequency for. + + @return CPU frequency in Hz +**/ +EFIAPI +UINTN +OemGetCpuFreq ( + IN UINT8 ProcessorIndex + ); + +/** Gets information about the specified processor and stores it in + the structures provided. + + @param ProcessorIndex Index of the processor to get the information for. + @param ProcessorStatus Processor status. + @param ProcessorCharacteristics Processor characteritics. + @param MiscProcessorData Miscellaneous processor information. + + @return TRUE on success, FALSE on failure. +**/ +EFIAPI +BOOLEAN +OemGetProcessorInformation ( + IN UINTN ProcessorIndex, + IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus, + IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics, + IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData + ); + +/** Gets information about the cache at the specified cache level. + + @param ProcessorIndex The processor to get information for. + @param CacheLevel The cache level to get information for. + @param InstructionOrUnifiedCache Whether the cache is instruction or + unified, not data. + @param SmbiosCacheTable The SMBIOS Type7 cache information structure. + + @return TRUE on success, FALSE on failure. +**/ +EFIAPI +BOOLEAN +OemGetCacheInformation ( + IN UINT8 ProcessorIndex, + IN UINT8 CacheLevel, + IN BOOLEAN InstructionOrUnifiedCache, + IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable + ); + +/** Gets the maximum number of sockets supported by the platform. + + @return The maximum number of sockets. +**/ +EFIAPI +UINT8 +OemGetProcessorMaxSockets ( + VOID + ); + +/** Gets the type of chassis for the system. + + @param ChassisType The type of the chassis. + + @retval EFI_SUCCESS The chassis type was fetched successfully. +**/ +EFIAPI +EFI_STATUS +OemGetChassisType ( + OUT UINT8 *ChassisType + ); + +/** Returns whether the specified processor is present or not. + + @param ProcessIndex The processor index to check. + + @return TRUE is the processor is present, FALSE otherwise. +**/ +EFIAPI +BOOLEAN +OemIsSocketPresent ( + IN UINTN ProcessorIndex + ); + +/** Updates the HII string for the specified field. + + @param mHiiHandle The HII handle. + @param TokenToUpdate The string to update. + @param Offset The field to get information about. +**/ +EFIAPI +VOID +OemUpdateSmbiosInfo ( + IN EFI_HII_HANDLE HiiHandle, + IN EFI_STRING_ID TokenToUpdate, + IN OEM_MISC_SMBIOS_HII_STRING_FIELD Offset + ); + +#endif // OEM_MISC_LIB_H_ -- 2.26.2