From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web08.27712.1612143430402429223 for ; Sun, 31 Jan 2021 17:37:26 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: n9KIKH7LTQFUFSAs3maxxDK6ACVG8804LpPyTiIIQs4USxv8YZwTW7HD10U2djEJ4E4QpmV9by iD3W4XQNkj9g== X-IronPort-AV: E=McAfee;i="6000,8403,9881"; a="177113885" X-IronPort-AV: E=Sophos;i="5.79,391,1602572400"; d="scan'208";a="177113885" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2021 17:37:19 -0800 IronPort-SDR: aYP3p4o5TEGjU7sdHZeALHrq91gFERDDPTzPgG5eegS6R0mJxlhrXIxWFC3D5XiN1LZySsoGiZ nXuVb3x9VYmQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,391,1602572400"; d="scan'208";a="368718600" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 31 Jan 2021 17:37:18 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [PATCH 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers Date: Mon, 1 Feb 2021 09:36:27 +0800 Message-Id: <20210201013657.1833-10-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210201013657.1833-1-heng.luo@intel.com> References: <20210201013657.1833-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following header files: * Fru/TglCpu/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/VtdIni= tFruLib.h | 18 ++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/CpuPc= ieRegs.h | 24 ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IgdRe= gs.h | 42 ++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/IpuRe= gs.h | 31 +++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/VtdRe= gs.h | 22 ++++++++++++++++++++++ 5 files changed, 137 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Li= brary/VtdInitFruLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Includ= ePrivate/Library/VtdInitFruLib.h new file mode 100644 index 0000000000..a46b29cbbe --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Library/V= tdInitFruLib.h @@ -0,0 +1,18 @@ +/** @file=0D + Vtd Initialization Fru Library header file=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _VTD_INIT_FRU_LIB_H_=0D +#define _VTD_INIT_FRU_LIB_H_=0D +=0D +///=0D +/// TCSS DMA controller RMRR buffer 4MB for each DMA controller=0D +///=0D +#define RMRR_TCSS_DMA_SIZE 0x400000=0D +=0D +extern UINT16 mDevEnMap[][2];=0D +extern UINTN mDevEnMapSize;=0D +=0D +#endif // _VTD_INIT_FRU_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Re= gister/CpuPcieRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include= Private/Register/CpuPcieRegs.h new file mode 100644 index 0000000000..a571381202 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/= CpuPcieRegs.h @@ -0,0 +1,24 @@ +/** @file=0D + This file contains definitions of PCIe Configuration=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _CPU_PCIE_REGS_H_=0D +#define _CPU_PCIE_REGS_H_=0D +=0D +#define R_PCIE_LCAP 0x4C=0D +#define R_PCIE_LCTL 0x50=0D +#define R_PCIE_LSTS 0x52=0D +#define R_PCIE_SLCAP 0x54=0D +#define R_PCIE_SLSTS 0x5A=0D +#define R_PCIE_LCTL2 0x70=0D +#define R_PCIE_MPC 0xD8=0D +#define B_PCIE_MPC_HPME BIT1=0D +#define R_PCIE_PGTHRES 0x5C0=0D +#define B_PCIE_PGTHRES_L1PGLTREN BIT0=0D +#define R_PCIE_LCTL3 0xA34=0D +#define B_PCIE_LCTL3_PE BIT0=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Re= gister/IgdRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePriv= ate/Register/IgdRegs.h new file mode 100644 index 0000000000..f0b30107f4 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/= IgdRegs.h @@ -0,0 +1,42 @@ +/** @file=0D + Register names for IGD block=0D + Conventions:=0D + - Prefixes:=0D + - Definitions beginning with "R_" are registers=0D + - Definitions beginning with "B_" are bits within registers=0D + - Definitions beginning with "V_" are meaningful values of bits within= the registers=0D + - Definitions beginning with "S_" are register sizes=0D + - Definitions beginning with "N_" are the bit position=0D + - In general, SA registers are denoted by "_SA_" in register names=0D + - Registers / bits that are different between SA generations are denoted= by=0D + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"=0D + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]"=0D + at the end of the register/bit names=0D + - Registers / bits of new devices introduced in a SA generation will be = just named=0D + as "_SA_" without [generation_name] inserted.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _IGD_REGS_H_=0D +#define _IGD_REGS_H_=0D +=0D +///=0D +/// Device 2 Register Equates=0D +///=0D +//=0D +// The following equates must be reviewed and revised when the specificati= on is ready.=0D +//=0D +#define IGD_BUS_NUM 0x00=0D +#define IGD_DEV_NUM 0x02=0D +#define IGD_FUN_NUM 0x00=0D +=0D +///=0D +/// GTTMMADR aligned to 16MB (Base address =3D [38:24])=0D +///=0D +#define R_SA_IGD_GTTMMADR 0x10=0D +=0D +#define R_SA_IGD_SWSCI_OFFSET 0x00E8=0D +#define R_SA_IGD_ASLS_OFFSET 0x00FC ///< ASL Storage=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Re= gister/IpuRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePriv= ate/Register/IpuRegs.h new file mode 100644 index 0000000000..afc72e8db0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/= IpuRegs.h @@ -0,0 +1,31 @@ +/** @file=0D + Register names for IPU block=0D + Conventions:=0D + - Prefixes:=0D + - Definitions beginning with "R_" are registers=0D + - Definitions beginning with "B_" are bits within registers=0D + - Definitions beginning with "V_" are meaningful values of bits within= the registers=0D + - Definitions beginning with "S_" are register sizes=0D + - Definitions beginning with "N_" are the bit position=0D + - IPU registers are denoted by "_IPU_" in register names=0D + - Registers / bits that are different between IPU generations are denote= d by=0D + "_IPU_[generation_name]_" in register/bit names. e.g., "_IPU_TGL_"=0D + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]"=0D + at the end of the register/bit names=0D + - Registers / bits of new devices introduced in a IPU generation will be= just named=0D + as "_IPU_" without [generation_name] inserted.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _IPU_REGS_H_=0D +#define _IPU_REGS_H_=0D +=0D +//=0D +// Device 5 Equates=0D +//=0D +#define IPU_BUS_NUM 0x00=0D +#define IPU_DEV_NUM 0x05=0D +#define IPU_FUN_NUM 0x00=0D +=0D +#endif // _IPU_REGS_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Re= gister/VtdRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePriv= ate/Register/VtdRegs.h new file mode 100644 index 0000000000..d796a44afc --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/IncludePrivate/Register/= VtdRegs.h @@ -0,0 +1,22 @@ +/** @file=0D + Register names for VTD block=0D + Conventions:=0D + - Prefixes:=0D + - Definitions beginning with "R_" are registers=0D + - Definitions beginning with "B_" are bits within registers=0D + - Definitions beginning with "V_" are meaningful values of bits within= the registers=0D + - Definitions beginning with "S_" are register sizes=0D + - Definitions beginning with "N_" are the bit position=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _VTD_REGS_H_=0D +#define _VTD_REGS_H_=0D +=0D +///=0D +/// Vt-d Engine base address.=0D +///=0D +#define R_MCHBAR_VTD1_OFFSET 0x5400 ///< HW UNIT1 for IGD= =0D +#define R_MCHBAR_VTD3_OFFSET 0x5410 ///< HW UNIT3 for all= other - PEG, USB, SATA etc=0D +=0D +#endif=0D --=20 2.24.0.windows.2