From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web08.27712.1612143430402429223 for ; Sun, 31 Jan 2021 17:37:33 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: H5INfATkkOqbE3pJQ9d+zFm80Z4B55RIbGa+gSdZt2/R9J98e+LxwNn1/iXwEaYRfwD6qAgwSG oT/l/Uqmbj6g== X-IronPort-AV: E=McAfee;i="6000,8403,9881"; a="177113915" X-IronPort-AV: E=Sophos;i="5.79,391,1602572400"; d="scan'208";a="177113915" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2021 17:37:25 -0800 IronPort-SDR: XMacQebRUJsnyR4GufJxkQ9VCjrH0ADcjiB9u21uBgI7Sg4LKArPysk9sti/qqtO7+napg7VL2 XHfGaMXGOicw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,391,1602572400"; d="scan'208";a="368718631" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 31 Jan 2021 17:37:24 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [PATCH 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp component Date: Mon, 1 Feb 2021 09:36:31 +0800 Message-Id: <20210201013657.1833-14-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210201013657.1833-1-heng.luo@intel.com> References: <20210201013657.1833-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * IpBlock/CpuPcieRp/Include * IpBlock/CpuPcieRp/IncludePrivate * IpBlock/CpuPcieRp/Library * IpBlock/CpuPcieRp/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h = | 31 +++++++++++++++++++= ++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPci= eInitCommon.h | 353 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/CpuPci= eRpLib.h | 47 +++++++++++++++++++= ++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Library= /DxeCpuPcieRpLib.h | 18 ++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPc= ieInitCommonLib/CpuPcieInitCommon.c | 445 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPc= ieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf | 33 +++++++++++++++++++= ++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPc= ieRpLib/CpuPcieRpLib.c | 48 +++++++++++++++++++= +++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPc= ieRpLib/PeiDxeSmmCpuPcieRpLib.inf | 32 +++++++++++++++++++= +++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuP= cieRpLib/DxeCpuPcieRpLib.c | 62 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuP= cieRpLib/DxeCpuPcieRpLib.inf | 40 +++++++++++++++++++= +++++++++++++++++++++ 10 files changed, 1109 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Cp= uPcieInfo.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/C= puPcieInfo.h new file mode 100644 index 0000000000..15eeab0ecf --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieIn= fo.h @@ -0,0 +1,31 @@ +/** @file=0D + This file contains definitions of PCIe controller information=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_PCIE_INFO_H_=0D +#define _CPU_PCIE_INFO_H_=0D +=0D +#define PCIE_HWEQ_COEFFS_MAX 5=0D +=0D +//=0D +// Device 1 Memory Mapped IO Register Offset Equates=0D +//=0D +#define SA_PEG_DEV_NUM 0x01=0D +#define SA_PEG0_DEV_NUM SA_PEG_DEV_NUM=0D +#define SA_PEG3_DEV_NUM 0x06=0D +=0D +//=0D +// SA PCI Express* Port configuration=0D +//=0D +=0D +#define CPU_PCIE_MAX_ROOT_PORTS 4=0D +=0D +#define SA_PEG_MAX_FUN 0x04=0D +#define SA_PEG_MAX_LANE 0x14=0D +#define SA_PEG_MAX_FUN_GEN3 0x03=0D +#define SA_PEG_MAX_LANE_GEN3 0x10=0D +#define SA_PEG_MAX_BUNDLE_GEN3 0x08=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Li= brary/CpuPcieInitCommon.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPc= ieRp/Include/Library/CpuPcieInitCommon.h new file mode 100644 index 0000000000..79b255c273 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/C= puPcieInitCommon.h @@ -0,0 +1,353 @@ +/** @file=0D +Header file for CpuPcieInitCommonLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_PCIE_INIT_COMMON_H_=0D +#define _CPU_PCIE_INIT_COMMON_H_=0D +=0D +#include =0D +=0D +/**=0D + Print registers value=0D +=0D + @param[in] PrintMmioBase Mmio base address=0D + @param[in] PrintSize Number of registers=0D + @param[in] OffsetFromBase Offset from mmio base address=0D +=0D + @retval None=0D +**/=0D +VOID=0D +SaPrintRegisters (=0D + IN UINTN PrintMmioBase,=0D + IN UINT32 PrintSize,=0D + IN UINT32 OffsetFromBase=0D + );=0D +=0D +/**=0D + Print registers value=0D +=0D + @param[in] PrintPciSegmentBase Pci segment base address=0D + @param[in] PrintSize Number of registers=0D + @param[in] OffsetFromBase Offset from mmio base address=0D +=0D + @retval None=0D +**/=0D +VOID=0D +SaPrintPciRegisters (=0D + IN UINT64 PrintPciSegmentBase,=0D + IN UINT32 PrintSize,=0D + IN UINT32 OffsetFromBase=0D + );=0D +=0D +//=0D +// 2LM: PegPcie APIs for Sideband Access Mechanism in 2LM mode=0D +//=0D +/**=0D +Reads an 8-bit PCI configuration register.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentRead8 functi= on.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Funct= ion, and Register.=0D +=0D +@return The 8-bit PCI configuration register specified by Address.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PegPciSegmentRead8 (=0D + IN UINT64 Address=0D + );=0D +=0D +/**=0D +Writes an 8-bit PCI configuration register.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentWrite8 funct= ion.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D +@param Value The value to write.=0D +=0D +@return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PegPciSegmentWrite8 (=0D + IN UINT64 Address,=0D + IN UINT8 Value=0D + );=0D +=0D +/**=0D +Reads a 16-bit PCI configuration register.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentRead16 funct= ion.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Funct= ion, and Register.=0D +=0D +@return The 16-bit PCI configuration register specified by Address.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PegPciSegmentRead16 (=0D + IN UINT64 Address=0D + );=0D +=0D +/**=0D +Writes a 16-bit PCI configuration register.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentWrite16 func= tion.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D +@param Value The value to write.=0D +=0D +@return The parameter of Value.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PegPciSegmentWrite16 (=0D + IN UINT64 Address,=0D + IN UINT16 Value=0D + );=0D +=0D +/**=0D +Reads a 32-bit PCI configuration register.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentRead32 funct= ion.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Funct= ion, and Register.=0D +=0D +@return The 32-bit PCI configuration register specified by Address.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PegPciSegmentRead32 (=0D + IN UINT64 Address=0D + );=0D +=0D +/**=0D +Writes a 32-bit PCI configuration register.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentWrite32 func= tion.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D +@param Value The value to write.=0D +=0D +@return The parameter of Value.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PegPciSegmentWrite32 (=0D + IN UINT64 Address,=0D + IN UINT32 Value=0D + );=0D +=0D +/**=0D +Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit= value.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentOr16 functio= n.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Funct= ion, and Register.=0D +@param OrData The value to OR with the PCI configuration register.=0D +=0D +@return The value written to the PCI configuration register.=0D +**/=0D +UINT16=0D +EFIAPI=0D +PegPciSegmentOr16 (=0D + IN UINT64 Address,=0D + IN UINT16 OrData=0D + );=0D +=0D +/**=0D +Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bi= t value.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentAnd32 functi= on.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Funct= ion, and Register.=0D +@param AndData The value to AND with the PCI configuration register.=0D +=0D +@return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PegPciSegmentAnd16 (=0D + IN UINT64 Address,=0D + IN UINT16 AndData=0D + );=0D +=0D +/**=0D +Performs a bitwise AND of a 8-bit PCI configuration register with a 8-bit = value.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentAnd8 functio= n.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Funct= ion, and Register.=0D +@param AndData The value to AND with the PCI configuration register.=0D +=0D +@return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PegPciSegmentAnd8 (=0D + IN UINT64 Address,=0D + IN UINT8 AndData=0D + );=0D +=0D +/**=0D +Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit= value.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentOr32 functio= n.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Funct= ion, and Register.=0D +@param OrData The value to OR with the PCI configuration register.=0D +=0D +@return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PegPciSegmentOr32 (=0D + IN UINT64 Address,=0D + IN UINT32 OrData=0D + );=0D +=0D +/**=0D +Performs a bitwise OR of a 8-bit PCI configuration register with a 8-bit v= alue.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentOr8 function= .=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Funct= ion, and Register.=0D +@param OrData The value to OR with the PCI configuration register.=0D +=0D +@return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PegPciSegmentOr8 (=0D + IN UINT64 Address,=0D + IN UINT8 OrData=0D + );=0D +=0D +/**=0D +Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bi= t value.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentAnd32 functi= on.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Funct= ion, and Register.=0D +@param AndData The value to AND with the PCI configuration register.=0D +=0D +@return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PegPciSegmentAnd32 (=0D + IN UINT64 Address,=0D + IN UINT32 AndData=0D + );=0D +=0D +/**=0D +Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bi= t value,=0D +followed a bitwise OR with another 32-bit value.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentAndThenOr32 = function.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Funct= ion, and Register.=0D +@param AndData The value to AND with the PCI configuration register.=0D +@param OrData The value to OR with the PCI configuration register.=0D +=0D +@return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PegPciSegmentAndThenOr32 (=0D + IN UINT64 Address,=0D + IN UINT32 AndData,=0D + IN UINT32 OrData=0D + );=0D +=0D +/**=0D +Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bi= t value,=0D +followed a bitwise OR with another 16-bit value.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentAndThenOr16 = function.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Funct= ion, and Register.=0D +@param AndData The value to AND with the PCI configuration register.=0D +@param OrData The value to OR with the PCI configuration register.=0D +=0D +@return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PegPciSegmentAndThenOr16 (=0D + IN UINT64 Address,=0D + IN UINT16 AndData,=0D + IN UINT16 OrData=0D + );=0D +=0D +/**=0D +Performs a bitwise AND of a 8-bit PCI configuration register with a 8-bit = value,=0D +followed a bitwise OR with another 8-bit value.=0D +=0D +Its a wrapper library function. This function uses side band access for PE= G60 when 2LM mode is enabled.=0D +Other calls to this function will be routed to core PciSegmentAndThenOr8 f= unction.=0D +=0D +@param Address Address that encodes the PCI Segment, Bus, Device, Funct= ion, and Register.=0D +@param AndData The value to AND with the PCI configuration register.=0D +@param OrData The value to OR with the PCI configuration register.=0D +=0D +@return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PegPciSegmentAndThenOr8 (=0D + IN UINT64 Address,=0D + IN UINT8 AndData,=0D + IN UINT8 OrData=0D + );=0D +=0D +/**=0D +Find the Offset to a Capabilities ID=0D +@param[in] Segment Pci Segment Number=0D +@param[in] Bus Pci Bus Number=0D +@param[in] Device Pci Device Number=0D +@param[in] Function Pci Function Number=0D +@param[in] CapId CAPID to search for=0D +=0D +@retval 0 CAPID not found=0D +@retval Other CAPID found, Offset of desired CAPID=0D +**/=0D +UINT8=0D +PegPcieFindCapId (=0D + IN UINT8 Segment,=0D + IN UINT8 Bus,=0D + IN UINT8 Device,=0D + IN UINT8 Function,=0D + IN UINT8 CapId=0D + );=0D +#endif // _CPU_PCIE_INIT_COMMON_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Li= brary/CpuPcieRpLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/= Include/Library/CpuPcieRpLib.h new file mode 100644 index 0000000000..ebb568193a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Include/Library/C= puPcieRpLib.h @@ -0,0 +1,47 @@ +/** @file=0D + Header file for CpuPcieRpLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_PCIERP_LIB_H_=0D +#define _CPU_PCIERP_LIB_H_=0D +=0D +#include =0D +#include =0D +=0D +#pragma pack(1)=0D +=0D +typedef struct {=0D + UINT8 Segment;=0D + UINT8 Bus;=0D + UINT8 Device;=0D + UINT8 Function;=0D + BOOLEAN Enable;=0D +} CPU_PCIE_RP_INFO;=0D +=0D +#pragma pack()=0D +=0D +/**=0D + Determines whether PCIe link is active=0D +=0D + @param[in] RpBase Root Port base address=0D + @retval Link Active state=0D +**/=0D +BOOLEAN=0D +CpuPcieIsLinkActive (=0D + UINT64 RpBase=0D + );=0D +=0D +/**=0D + Get max PCIe link speed supported by the root port.=0D +=0D + @param[in] RpBase Root Port pci segment base address=0D + @return Max link speed=0D +**/=0D +UINT32=0D +CpuPcieGetMaxLinkSpeed (=0D + UINT64 RpBase=0D + );=0D +=0D +#endif // _CPU_PCIERP_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePri= vate/Library/DxeCpuPcieRpLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/= CpuPcieRp/IncludePrivate/Library/DxeCpuPcieRpLib.h new file mode 100644 index 0000000000..593e1893bb --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/IncludePrivate/Li= brary/DxeCpuPcieRpLib.h @@ -0,0 +1,18 @@ +/** @file=0D + Header file for private DxeCpuPcieRpLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _DXE_PCIE_RP_INIT_LIB_H_=0D +#define _DXE_PCIE_RP_INIT_LIB_H_=0D +=0D +/**=0D + Update CPU PCIE RP NVS AREA tables=0D +=0D +**/=0D +VOID=0D +UpdateCpuPcieNVS (=0D + VOID=0D + );=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/Pe= iDxeSmmCpuPcieInitCommonLib/CpuPcieInitCommon.c b/Silicon/Intel/TigerlakeSi= liconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommonLib/CpuPcieIni= tCommon.c new file mode 100644 index 0000000000..28032e5b24 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmm= CpuPcieInitCommonLib/CpuPcieInitCommon.c @@ -0,0 +1,445 @@ +/** @file=0D + common library for CPU PCIe INIT PEI/DXE/SMM modules=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Print registers value=0D +=0D + @param[in] PrintMmioBase Mmio base address=0D + @param[in] PrintSize Number of registers=0D + @param[in] OffsetFromBase Offset from mmio base address=0D +=0D + @retval None=0D +**/=0D +VOID=0D +SaPrintRegisters (=0D + IN UINTN PrintMmioBase,=0D + IN UINT32 PrintSize,=0D + IN UINT32 OffsetFromBase=0D + )=0D +{=0D + UINT32 Offset;=0D + DEBUG ((DEBUG_VERBOSE, " 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D= 0E 0F"));=0D + for (Offset =3D 0; Offset < PrintSize; Offset++) {=0D + if ((Offset % 16) =3D=3D 0) {=0D + DEBUG ((DEBUG_VERBOSE, "\n %04X: ", (Offset + OffsetFromBase) & 0xFF= F0));=0D + }=0D + DEBUG ((DEBUG_VERBOSE, "%02X ", MmioRead8 (PrintMmioBase + Offset)));= =0D + }=0D + DEBUG ((DEBUG_VERBOSE, "\n"));=0D +}=0D +=0D +/**=0D + Print registers value=0D +=0D + @param[in] PrintPciSegmentBase Pci segment base address=0D + @param[in] PrintSize Number of registers=0D + @param[in] OffsetFromBase Offset from mmio base address=0D +=0D + @retval None=0D +**/=0D +VOID=0D +SaPrintPciRegisters (=0D + IN UINT64 PrintPciSegmentBase,=0D + IN UINT32 PrintSize,=0D + IN UINT32 OffsetFromBase=0D + )=0D +{=0D + UINT32 Offset;=0D + DEBUG ((DEBUG_VERBOSE, " 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D= 0E 0F"));=0D + for (Offset =3D 0; Offset < PrintSize; Offset++) {=0D + if ((Offset % 16) =3D=3D 0) {=0D + DEBUG ((DEBUG_VERBOSE, "\n %04X: ", (Offset + OffsetFromBase) & 0xFF= F0));=0D + }=0D + DEBUG ((DEBUG_VERBOSE, "%02X ", PciSegmentRead8 (PrintPciSegmentBase += Offset)));=0D + }=0D + DEBUG ((DEBUG_VERBOSE, "\n"));=0D +}=0D +=0D +//=0D +// 2LM: PegPcie APIs using the Sideband Access Mechanism=0D +//=0D +/**=0D + Reads an 8-bit PCI configuration register.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentRead8 func= tion.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D +=0D + @return The 8-bit PCI configuration register specified by Address.=0D +**/=0D +UINT8=0D +EFIAPI=0D +PegPciSegmentRead8 (=0D + IN UINT64 Address=0D + )=0D +{=0D + return PciSegmentRead8 (Address);=0D +}=0D +=0D +/**=0D + Writes an 8-bit PCI configuration register.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentWrite8 fun= ction.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, F= unction, and Register.=0D + @param Value The value to write.=0D +=0D + @return The value written to the PCI configuration register.=0D +**/=0D +UINT8=0D +EFIAPI=0D +PegPciSegmentWrite8 (=0D + IN UINT64 Address,=0D + IN UINT8 Value=0D + )=0D +{=0D + return PciSegmentWrite8 (Address, Value);=0D +}=0D +=0D +/**=0D + Reads a 16-bit PCI configuration register.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentRead16 fun= ction.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D +=0D + @return The 16-bit PCI configuration register specified by Address.=0D +**/=0D +UINT16=0D +EFIAPI=0D +PegPciSegmentRead16 (=0D + IN UINT64 Address=0D + )=0D +{=0D + return PciSegmentRead16 (Address);=0D +}=0D +=0D +/**=0D + Writes a 16-bit PCI configuration register.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentWrite16 fu= nction.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, F= unction, and Register.=0D + @param Value The value to write.=0D +=0D + @return The parameter of Value.=0D +**/=0D +UINT16=0D +EFIAPI=0D +PegPciSegmentWrite16 (=0D + IN UINT64 Address,=0D + IN UINT16 Value=0D + )=0D +{=0D + return PciSegmentWrite16 (Address, Value);=0D +}=0D +=0D +/**=0D + Reads a 32-bit PCI configuration register.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentRead32 fun= ction.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D +=0D + @return The 32-bit PCI configuration register specified by Address.=0D +**/=0D +UINT32=0D +EFIAPI=0D +PegPciSegmentRead32 (=0D + IN UINT64 Address=0D + )=0D +{=0D + return PciSegmentRead32 (Address);=0D +}=0D +=0D +/**=0D + Writes a 32-bit PCI configuration register.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentWrite32 fu= nction.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, F= unction, and Register.=0D + @param Value The value to write.=0D +=0D + @return The parameter of Value.=0D +**/=0D +UINT32=0D +EFIAPI=0D +PegPciSegmentWrite32 (=0D + IN UINT64 Address,=0D + IN UINT32 Value=0D + )=0D +{=0D + return PciSegmentWrite32 (Address, Value);=0D +}=0D +=0D +/**=0D + Performs a bitwise OR of a 16-bit PCI configuration register with a 16-b= it value.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentOr16 funct= ion.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written to the PCI configuration register.=0D +**/=0D +UINT16=0D +EFIAPI=0D +PegPciSegmentOr16 (=0D + IN UINT64 Address,=0D + IN UINT16 OrData=0D + )=0D +{=0D + return PciSegmentOr16 (Address, OrData);=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit value.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentAnd32 func= tion.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PegPciSegmentAnd16 (=0D + IN UINT64 Address,=0D + IN UINT16 AndData=0D + )=0D +{=0D + return PciSegmentAnd16 (Address, AndData);=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 8-bit PCI configuration register with a 8-bi= t value.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentAnd8 funct= ion.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PegPciSegmentAnd8 (=0D + IN UINT64 Address,=0D + IN UINT8 AndData=0D + )=0D +{=0D + return PciSegmentAnd8 (Address, AndData);=0D +}=0D +=0D +/**=0D + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-b= it value.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentOr32 funct= ion.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written to the PCI configuration register.=0D +**/=0D +UINT32=0D +EFIAPI=0D +PegPciSegmentOr32 (=0D + IN UINT64 Address,=0D + IN UINT32 OrData=0D + )=0D +{=0D + return PciSegmentOr32 (Address, OrData);=0D +}=0D +=0D +/**=0D + Performs a bitwise OR of a 8-bit PCI configuration register with a 8-bit= value.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentOr8 functi= on.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written to the PCI configuration register.=0D +**/=0D +UINT8=0D +EFIAPI=0D +PegPciSegmentOr8 (=0D + IN UINT64 Address,=0D + IN UINT8 OrData=0D + )=0D +{=0D + return PciSegmentOr8 (Address, OrData);=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit value.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentAnd32 func= tion.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PegPciSegmentAnd32 (=0D + IN UINT64 Address,=0D + IN UINT32 AndData=0D + )=0D +{=0D + return PciSegmentAnd32 (Address, AndData);=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit value,=0D + followed a bitwise OR with another 32-bit value.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentAndThenOr3= 2 function.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written to the PCI configuration register.=0D +**/=0D +UINT32=0D +EFIAPI=0D +PegPciSegmentAndThenOr32 (=0D + IN UINT64 Address,=0D + IN UINT32 AndData,=0D + IN UINT32 OrData=0D + )=0D +{=0D + return PciSegmentAndThenOr32 (Address, AndData, OrData);=0D +}=0D +=0D +=0D +/**=0D + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit value,=0D + followed a bitwise OR with another 16-bit value.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentAndThenOr1= 6 function.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written to the PCI configuration register.=0D +**/=0D +UINT16=0D +EFIAPI=0D +PegPciSegmentAndThenOr16 (=0D + IN UINT64 Address,=0D + IN UINT16 AndData,=0D + IN UINT16 OrData=0D + )=0D +{=0D + return PciSegmentAndThenOr16 (Address, AndData, OrData);=0D +}=0D +=0D +=0D +/**=0D + Performs a bitwise AND of a 8-bit PCI configuration register with a 8-bi= t value,=0D + followed a bitwise OR with another 8-bit value.=0D +=0D + Its a wrapper library function. This function uses side band access for = PEG60 when 2LM mode is enabled.=0D + Other calls to this function will be routed to core PciSegmentAndThenOr8= function.=0D +=0D + @param Address Address that encodes the PCI Segment, Bus, Device, Fun= ction, and Register.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written to the PCI configuration register.=0D +**/=0D +UINT8=0D +EFIAPI=0D +PegPciSegmentAndThenOr8 (=0D + IN UINT64 Address,=0D + IN UINT8 AndData,=0D + IN UINT8 OrData=0D + )=0D +{=0D + return PciSegmentAndThenOr8 (Address, AndData, OrData);=0D +}=0D +=0D +=0D +/**=0D + Find the Offset to a Capabilities ID=0D + @param[in] Segment Pci Segment Number=0D + @param[in] Bus Pci Bus Number=0D + @param[in] Device Pci Device Number=0D + @param[in] Function Pci Function Number=0D + @param[in] CapId CAPID to search for=0D +=0D + @retval 0 CAPID not found=0D + @retval Other CAPID found, Offset of desired CAPID=0D +**/=0D +UINT8=0D +PegPcieFindCapId (=0D + IN UINT8 Segment,=0D + IN UINT8 Bus,=0D + IN UINT8 Device,=0D + IN UINT8 Function,=0D + IN UINT8 CapId=0D + )=0D +{=0D + return PcieFindCapId (Segment, Bus, Device, Function, CapId);=0D +}=0D +=0D +=0D +/**=0D + Search and return the offset of desired Pci Express extended Capability = ID=0D + @param[in] Segment Pci Segment Number=0D + @param[in] Bus Pci Bus Number=0D + @param[in] Device Pci Device Number=0D + @param[in] Function Pci Function Number=0D + @param[in] CapId Extended CAPID to search for=0D +=0D + @retval 0 CAPID not found=0D + @retval Other CAPID found, Offset of desired CAPID=0D +**/=0D +UINT16=0D +PegPcieFindExtendedCapId (=0D + IN UINT8 Segment,=0D + IN UINT8 Bus,=0D + IN UINT8 Device,=0D + IN UINT8 Function,=0D + IN UINT16 CapId=0D + )=0D +{=0D + return PcieFindExtendedCapId (Segment, Bus, Device, Function, CapId);=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/Pe= iDxeSmmCpuPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf b/Silicon/Int= el/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieInitCommon= Lib/PeiDxeSmmCpuPcieInitCommonLib.inf new file mode 100644 index 0000000000..2ad30ab7c9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmm= CpuPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf @@ -0,0 +1,33 @@ +## @file=0D +# Component description file for the CpuPcieInitCommonLib=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PeiDxeSmmCpuPcieInitCommonLib=0D + FILE_GUID =3D 68992CB0-A3A5-4f73-9370-93A3559F84C8= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D CpuPcieInitCommonLib=0D +=0D +[Sources]=0D + CpuPcieInitCommon.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[LibraryClasses]=0D + IoLib=0D + DebugLib=0D + PciSegmentLib=0D + CpuPcieRpLib=0D + CpuRegbarAccessLib=0D + BasePcieHelperLib=0D +=0D +[Pcd]=0D + gSiPkgTokenSpaceGuid.PcdCpuPcieEnable ## CONSUMES=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/Pe= iDxeSmmCpuPcieRpLib/CpuPcieRpLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBl= ock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/CpuPcieRpLib.c new file mode 100644 index 0000000000..02cd482b55 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmm= CpuPcieRpLib/CpuPcieRpLib.c @@ -0,0 +1,48 @@ +/** @file=0D + CPU PCIe root port library.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include "CpuPcieInfo.h"=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Determines whether PCIe link is active=0D +=0D + @param[in] RpBase Root Port base address=0D + @retval Link Active state=0D +**/=0D +BOOLEAN=0D +CpuPcieIsLinkActive (=0D + UINT64 RpBase=0D + )=0D +{=0D + return !! (PegPciSegmentRead16 (RpBase + R_PCIE_LSTS) & B_PCIE_LSTS_LA);= =0D +}=0D +=0D +/**=0D + Get max PCIe link speed supported by the root port.=0D +=0D + @param[in] RpBase Root Port base address=0D + @return Max link speed=0D +**/=0D +UINT32=0D +CpuPcieGetMaxLinkSpeed (=0D + UINT64 RpBase=0D + )=0D +{=0D + return PegPciSegmentRead32 (RpBase + R_PCIE_LCAP) & B_PCIE_LCAP_MLS;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/Pe= iDxeSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf b/Silicon/Intel/TigerlakeSili= conPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLi= b.inf new file mode 100644 index 0000000000..cea8bcbecd --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/Library/PeiDxeSmm= CpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf @@ -0,0 +1,32 @@ +## @file=0D +# CPU PCIE root port Library.=0D +#=0D +# All function in this library is available for PEI, DXE, and SMM,=0D +# But do not support UEFI RUNTIME environment call.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmCpuPcieRpLib=0D +FILE_GUID =3D 00199A03-41F4-43c7-B6D5-5A3AA1EE78D0=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D CpuPcieRpLib=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +PciLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D +CpuPcieRpLib.c=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPri= vate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.c b/Silicon/Intel/TigerlakeSiliconPkg/= IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.c new file mode 100644 index 0000000000..48ef8165de --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/Dx= eCpuPcieRpLib/DxeCpuPcieRpLib.c @@ -0,0 +1,62 @@ +/** @file=0D + The DXE CPU PCIE RP Library Implements After Memory PEIM=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D +Update CPU PCIE RP NVS AREA tables=0D +=0D +**/=0D +VOID=0D +UpdateCpuPcieNVS (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + PCIE_DXE_CONFIG *PcieDxeConfig;=0D + SA_POLICY_PROTOCOL *SaPolicy;=0D + SYSTEM_AGENT_NVS_AREA_PROTOCOL *SaNvsAreaProtocol;=0D +=0D + DEBUG ((DEBUG_INFO, "Update Cpu Pcie NVS Area.\n"));=0D +=0D + Status =3D gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **) = &SaPolicy);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gPcieDxeConfigGuid, (VOID = *)&PcieDxeConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D gBS->LocateProtocol (&gSaNvsAreaProtocolGuid, NULL, (VOID **)= &SaNvsAreaProtocol);=0D + if (Status !=3D EFI_SUCCESS) {=0D + DEBUG ((DEBUG_ERROR, "Locate SA NVS Area failed.\n"));=0D + return;=0D + }=0D +=0D + SaNvsAreaProtocol->Area->Peg0LtrEnable =3D PcieDxeConfig->PegPwrOpt[0].= LtrEnable;=0D + SaNvsAreaProtocol->Area->Peg0ObffEnable =3D PcieDxeConfig->PegPwrOpt[0].= ObffEnable;=0D + SaNvsAreaProtocol->Area->Peg1LtrEnable =3D PcieDxeConfig->PegPwrOpt[1].= LtrEnable;=0D + SaNvsAreaProtocol->Area->Peg1ObffEnable =3D PcieDxeConfig->PegPwrOpt[1].= ObffEnable;=0D + SaNvsAreaProtocol->Area->Peg2LtrEnable =3D PcieDxeConfig->PegPwrOpt[2].= LtrEnable;=0D + SaNvsAreaProtocol->Area->Peg2ObffEnable =3D PcieDxeConfig->PegPwrOpt[2].= ObffEnable;=0D + SaNvsAreaProtocol->Area->Peg3LtrEnable =3D PcieDxeConfig->PegPwrOpt[3].= LtrEnable;=0D + SaNvsAreaProtocol->Area->Peg3ObffEnable =3D PcieDxeConfig->PegPwrOpt[3].= ObffEnable;=0D + SaNvsAreaProtocol->Area->PegLtrMaxSnoopLatency =3D V_SA_LTR_MAX_SNOOP_LA= TENCY_VALUE;=0D + SaNvsAreaProtocol->Area->PegLtrMaxNoSnoopLatency =3D V_SA_LTR_MAX_NON_SN= OOP_LATENCY_VALUE;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPri= vate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf b/Silicon/Intel/TigerlakeSiliconPk= g/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf new file mode 100644 index 0000000000..dc9b893be3 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/CpuPcieRp/LibraryPrivate/Dx= eCpuPcieRpLib/DxeCpuPcieRpLib.inf @@ -0,0 +1,40 @@ +## @file=0D +# The DXE CPU PCIE RP Library Implements After Memory PEIM=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D DxeCpuPcieRpLib=0D +FILE_GUID =3D D563A22E-6A01-4EF7-84D1-78B6717E3402=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D DXE_DRIVER=0D +UEFI_SPECIFICATION_VERSION =3D 2.00=0D +LIBRARY_CLASS =3D DxeCpuPcieRpLib=0D +=0D +[LibraryClasses]=0D +IoLib=0D +BaseLib=0D +DebugLib=0D +BaseMemoryLib=0D +UefiBootServicesTableLib=0D +UefiLib=0D +HobLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D +DxeCpuPcieRpLib.c=0D +=0D +[Guids]=0D +gPcieDxeConfigGuid=0D +=0D +[Protocols]=0D +gSaPolicyProtocolGuid ## CONSUMES=0D +gSaNvsAreaProtocolGuid ## CONSUMES=0D --=20 2.24.0.windows.2