From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com []) by mx.groups.io with SMTP id smtpd.web09.27638.1612143460154346141 for ; Sun, 31 Jan 2021 17:37:40 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: j/jmfaavs7ITCJJSJE2h4kDXfE5GPmPme58/RchuDB8JSeX718p/MNtIKpDqPgE9+L3drp63tu tKtYFrpUwt4A== X-IronPort-AV: E=McAfee;i="6000,8403,9881"; a="177113987" X-IronPort-AV: E=Sophos;i="5.79,391,1602572400"; d="scan'208";a="177113987" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2021 17:37:35 -0800 IronPort-SDR: qMsIi08AoqD95NkjxSq0RJtRy9EW2cPAFWxli97B+nOPnqgFWO/NuCzKh4eeoE4T+zx0+Jn9Pw dswqDjJBy99A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,391,1602572400"; d="scan'208";a="368718703" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 31 Jan 2021 17:37:34 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [PATCH 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component Date: Mon, 1 Feb 2021 09:36:39 +0800 Message-Id: <20210201013657.1833-22-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210201013657.1833-1-heng.luo@intel.com> References: <20210201013657.1833-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * IpBlock/PchDmi/IncludePrivate * IpBlock/PchDmi/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/Pc= hDmiLib.h | 175 +++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmP= chDmiLib/PchDmi14.c | 50 +++++++++++++++++++++++++++++++= +++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmP= chDmiLib/PchDmi14.h | 34 +++++++++++++++++++++++++++++++= +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmP= chDmiLib/PchDmiLib.c | 269 +++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmP= chDmiLib/PchDmiWithS3Lib.c | 73 +++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmP= chDmiLib/PeiDxeSmmPchDmiLib.inf | 42 +++++++++++++++++++++++++++++++= +++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmP= chDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf | 41 +++++++++++++++++++++++++++++++= ++++++++++ 7 files changed, 684 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivat= e/Library/PchDmiLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/In= cludePrivate/Library/PchDmiLib.h new file mode 100644 index 0000000000..77db69c75a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Libra= ry/PchDmiLib.h @@ -0,0 +1,175 @@ +/** @file=0D + Header file for PchDmiLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_DMI_LIB_H_=0D +#define _PCH_DMI_LIB_H_=0D +=0D +/**=0D + This function checks if DMI Secured Register Lock (SRL) is set=0D +=0D + @retval SRL state=0D +**/=0D +BOOLEAN=0D +IsPchDmiLocked (=0D + VOID=0D + );=0D +=0D +/**=0D + Get PCH TCO base address.=0D +=0D + @retval Address Address of TCO base address.=0D +**/=0D +UINT16=0D +PchDmiGetTcoBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Set PCH LPC/eSPI generic IO range decoding in DMI=0D +=0D + @param[in] Address Address for generic IO range base = address.=0D + @param[in] Length Length of generic IO range.=0D + @param[in] RangeIndex Index of choosen range=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetLpcGenIoRange (=0D + IN UINT32 Address,=0D + IN UINT32 Length,=0D + IN UINT32 RangeIndex=0D + );=0D +=0D +/**=0D + Set PCH eSPI eSPI CS1# generic IO range decoding in DMI=0D +=0D + @param[in] Address Address for generic IO range base = address.=0D + @param[in] Length Length of generic IO range.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetEspiCs1GenIoRange (=0D + IN UINT32 Address,=0D + IN UINT32 Length=0D + );=0D +=0D +/**=0D + Set PCH LPC/eSPI memory range decoding in DMI=0D +=0D + @param[in] Address Address for memory base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetLpcMemRange (=0D + IN UINT32 Address=0D + );=0D +=0D +/**=0D + Set PCH eSPI CS1# memory range decoding in DMI=0D +=0D + @param[in] Address Address for memory base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetEspiCs1MemRange (=0D + IN UINT32 Address=0D + );=0D +=0D +/**=0D + Check if Boot BIOS Strap is set for SPI.=0D +=0D + @retval TRUE Boot BIOS Strap set for SPI=0D + @retval FALSE Boot BIOS Strap set for LPC/eSPI=0D +**/=0D +BOOLEAN=0D +PchDmiIsBootBiosStrapSetForSpi (=0D + VOID=0D + );=0D +=0D +/**=0D + Set PCH BIOS range decoding in DMI=0D + Please check EDS for detail of BiosDecodeEnable bit definition.=0D + bit 15: F8-FF Enable=0D + bit 14: F0-F8 Enable=0D + bit 13: E8-EF Enable=0D + bit 12: E0-E8 Enable=0D + bit 11: D8-DF Enable=0D + bit 10: D0-D7 Enable=0D + bit 9: C8-CF Enable=0D + bit 8: C0-C7 Enable=0D + bit 7: Legacy F Segment Enable=0D + bit 6: Legacy E Segment Enable=0D + bit 5: Reserved=0D + bit 4: Reserved=0D + bit 3: 70-7F Enable=0D + bit 2: 60-6F Enable=0D + bit 1: 50-5F Enable=0D + bit 0: 40-4F Enable=0D +=0D + @param[in] BiosDecodeEnable Bios decode enable setting.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetBiosDecodeEnable (=0D + IN UINT16 BiosDecodeEnable=0D + );=0D +=0D +/**=0D + Set PCH LPC/eSPI IO decode ranges in DMI=0D + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.= =0D + Bit 12: FDD range=0D + Bit 9:8: LPT range=0D + Bit 6:4: ComB range=0D + Bit 2:0: ComA range=0D +=0D + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit sett= ings.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetLpcIoDecodeRanges (=0D + IN UINT16 LpcIoDecodeRanges=0D + );=0D +=0D +/**=0D + Set PCH LPC/eSPI IO enable decoding in DMI=0D +=0D + @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit se= ttings.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetLpcIoEnable (=0D + IN UINT16 LpcIoEnableDecoding=0D + );=0D +=0D +/**=0D + Configure PCH DMI Lock=0D +**/=0D +VOID=0D +PchDmiSetLockWithS3BootScript (=0D + VOID=0D + );=0D +=0D +/**=0D + Set BIOS interface Lock-Down=0D +**/=0D +VOID=0D +PchDmiSetBiosLockDownWithS3BootScript (=0D + VOID=0D + );=0D +#endif // _PCH_DMI_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivat= e/PeiDxeSmmPchDmiLib/PchDmi14.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock= /PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c new file mode 100644 index 0000000000..60bc29c431 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDx= eSmmPchDmiLib/PchDmi14.c @@ -0,0 +1,50 @@ +/** @file=0D + This file contains functions for PCH DMI SIP14=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + This function checks if DMI SIP14 Secured Register Lock (SRL) is set=0D +=0D + @retval SRL state=0D +**/=0D +BOOLEAN=0D +IsPchDmi14Locked (=0D + VOID=0D + )=0D +{=0D + return ((PchPcrRead32 (PID_DMI, R_PCH_DMI14_PCR_DMIC) & B_PCH_DMI14_PCR_= DMIC_SRL) !=3D 0);=0D +}=0D +=0D +/**=0D + Secure Register Lock data=0D +=0D + @param[out] SrlRegOffset Register offset holding Secure Register L= ock setting=0D + @param[out] SrlRegMask Mask for Secure Register Lock setting=0D +**/=0D +VOID=0D +PchDmi14SrlRegData (=0D + OUT UINT16 *SrlRegOffset,=0D + OUT UINT32 *SrlRegMask=0D + )=0D +{=0D + *SrlRegMask =3D B_PCH_DMI14_PCR_DMIC_SRL;=0D + *SrlRegOffset =3D R_PCH_DMI14_PCR_DMIC;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivat= e/PeiDxeSmmPchDmiLib/PchDmi14.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock= /PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h new file mode 100644 index 0000000000..4c19ad82d7 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDx= eSmmPchDmiLib/PchDmi14.h @@ -0,0 +1,34 @@ +/** @file=0D + Internal header file for PCH DMI library for SIP14=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef __PCH_DMI_14_H__=0D +#define __PCH_DMI_14_H__=0D +=0D +#include =0D +=0D +/**=0D + This function checks if DMI SIP14 Secured Register Lock (SRL) is set=0D +=0D + @retval SRL state=0D +**/=0D +BOOLEAN=0D +IsPchDmi14Locked (=0D + VOID=0D + );=0D +=0D +/**=0D + Secure Register Lock data=0D +=0D + @param[out] SrlRegOffset Register offset holding Secure Register L= ock setting=0D + @param[out] SrlRegMask Mask for Secure Register Lock setting=0D +**/=0D +VOID=0D +PchDmi14SrlRegData (=0D + OUT UINT16 *SrlRegOffset,=0D + OUT UINT32 *SrlRegMask=0D + );=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivat= e/PeiDxeSmmPchDmiLib/PchDmiLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBloc= k/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c new file mode 100644 index 0000000000..972e5145aa --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDx= eSmmPchDmiLib/PchDmiLib.c @@ -0,0 +1,269 @@ +/** @file=0D + PCH DMI library.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "PchDmi14.h"=0D +=0D +/**=0D + This function checks if DMI Secured Register Lock (SRL) is set=0D +=0D + @retval SRL state=0D +**/=0D +BOOLEAN=0D +IsPchDmiLocked (=0D + VOID=0D + )=0D +{=0D + return IsPchDmi14Locked ();=0D +}=0D +=0D +/**=0D + Get PCH TCO base address.=0D +=0D + @retval Address Address of TCO base address.=0D +**/=0D +UINT16=0D +PchDmiGetTcoBase (=0D + VOID=0D + )=0D +{=0D + //=0D + // Read "TCO Base Address" PCR[DMI] + 2778h[15:5]=0D + //=0D + return (PchPcrRead16 (PID_DMI, R_PCH_DMI_PCR_TCOBASE) & B_PCH_DMI_PCR_TC= OBASE_TCOBA);=0D +}=0D +=0D +/**=0D + Set PCH LPC/eSPI generic IO range decoding in DMI=0D +=0D + @param[in] Address Address for generic IO range base = address.=0D + @param[in] Length Length of generic IO range.=0D + @param[in] RangeIndex Index of choosen range=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetLpcGenIoRange (=0D + IN UINT32 Address,=0D + IN UINT32 Length,=0D + IN UINT32 RangeIndex=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +/**=0D + Set PCH eSPI eSPI CS1# generic IO range decoding in DMI=0D +=0D + @param[in] Address Address for generic IO range base = address.=0D + @param[in] Length Length of generic IO range.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetEspiCs1GenIoRange (=0D + IN UINT32 Address,=0D + IN UINT32 Length=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +/**=0D + Set PCH LPC/eSPI memory range decoding in DMI=0D +=0D + @param[in] Address Address for memory base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetLpcMemRange (=0D + IN UINT32 Address=0D + )=0D +{=0D + if (IsPchDmiLocked ()) {=0D + DEBUG ((DEBUG_ERROR, "%a Error. DMI is locked.\n", __FUNCTION__));=0D + ASSERT (FALSE);=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + //=0D + // Program LPC Memory Range, PCR[DMI] + 2740h to the same value programm= ed in LPC/eSPI PCI Offset 98h.=0D + //=0D + PchPcrWrite32 (=0D + PID_DMI, R_PCH_DMI_PCR_LPCGMR,=0D + (Address | B_LPC_CFG_LGMR_LMRD_EN)=0D + );=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Set PCH eSPI CS1# memory range decoding in DMI=0D +=0D + @param[in] Address Address for memory base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetEspiCs1MemRange (=0D + IN UINT32 Address=0D + )=0D +{=0D + if (IsPchDmiLocked ()) {=0D + DEBUG ((DEBUG_ERROR, "%a Error. DMI is locked.\n", __FUNCTION__));=0D + ASSERT (FALSE);=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + //=0D + // Program LPC Memory Range, PCR[DMI] + 27C0h to the same value programm= ed in eSPI PCI Offset A8h.=0D + //=0D + PchPcrWrite32 (=0D + PID_DMI, R_PCH_DMI_PCR_SEGMR,=0D + (Address | B_LPC_CFG_LGMR_LMRD_EN)=0D + );=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Check if Boot BIOS Strap is set for SPI.=0D +=0D + @retval TRUE Boot BIOS Strap set for SPI=0D + @retval FALSE Boot BIOS Strap set for LPC/eSPI=0D +**/=0D +BOOLEAN=0D +PchDmiIsBootBiosStrapSetForSpi (=0D + VOID=0D + )=0D +{=0D + //=0D + // Check General Control and Status (GCS) [10]=0D + // '0': SPI=0D + // '1': LPC/eSPI=0D + //=0D + return ((PchPcrRead32 (PID_DMI, R_PCH_DMI_PCR_GCS) & B_PCH_DMI_PCR_BBS) = !=3D B_PCH_DMI_PCR_BBS);=0D +}=0D +=0D +/**=0D + Set PCH BIOS range decoding in DMI=0D + Please check EDS for detail of BiosDecodeEnable bit definition.=0D + bit 15: F8-FF Enable=0D + bit 14: F0-F8 Enable=0D + bit 13: E8-EF Enable=0D + bit 12: E0-E8 Enable=0D + bit 11: D8-DF Enable=0D + bit 10: D0-D7 Enable=0D + bit 9: C8-CF Enable=0D + bit 8: C0-C7 Enable=0D + bit 7: Legacy F Segment Enable=0D + bit 6: Legacy E Segment Enable=0D + bit 5: Reserved=0D + bit 4: Reserved=0D + bit 3: 70-7F Enable=0D + bit 2: 60-6F Enable=0D + bit 1: 50-5F Enable=0D + bit 0: 40-4F Enable=0D +=0D + @param[in] BiosDecodeEnable Bios decode enable setting.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetBiosDecodeEnable (=0D + IN UINT16 BiosDecodeEnable=0D + )=0D +{=0D + if (IsPchDmiLocked ()) {=0D + ASSERT (FALSE);=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + //=0D + // program LPC BIOS Decode Enable, PCR[DMI] + 2744h to the same value pr= ogrammed in LPC or SPI Offset D8h.=0D + //=0D + PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCBDE, BiosDecodeEnable);=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Set PCH LPC/eSPI IO decode ranges in DMI=0D + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.= =0D + Bit 12: FDD range=0D + Bit 9:8: LPT range=0D + Bit 6:4: ComB range=0D + Bit 2:0: ComA range=0D +=0D + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit sett= ings.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetLpcIoDecodeRanges (=0D + IN UINT16 LpcIoDecodeRanges=0D + )=0D +{=0D + //=0D + // This cycle decoding is only allowed to set when DMI is not locked.=0D + //=0D + if (IsPchDmiLocked ()) {=0D + ASSERT (FALSE);=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + //=0D + // program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same val= ue programmed in LPC/eSPI PCI offset 80h.=0D + //=0D + PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOD, LpcIoDecodeRanges);=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Set PCH LPC/eSPI IO enable decoding in DMI=0D +=0D + @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit se= ttings.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchDmiSetLpcIoEnable (=0D + IN UINT16 LpcIoEnableDecoding=0D + )=0D +{=0D + //=0D + // This cycle decoding is only allowed to set when DMI is not locked.=0D + //=0D + if (IsPchDmiLocked ()) {=0D + ASSERT (FALSE);=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + //=0D + // program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same val= ue programmed in LPC/eSPI PCI offset 82h.=0D + //=0D + PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOE, LpcIoEnableDecoding);=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivat= e/PeiDxeSmmPchDmiLib/PchDmiWithS3Lib.c b/Silicon/Intel/TigerlakeSiliconPkg/= IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiWithS3Lib.c new file mode 100644 index 0000000000..7d6801ee57 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDx= eSmmPchDmiLib/PchDmiWithS3Lib.c @@ -0,0 +1,73 @@ +/** @file=0D + PCH DMI library with S3 boot script support.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "PchDmi14.h"=0D +=0D +/**=0D + Configure DMI Lock=0D +**/=0D +VOID=0D +PchDmiSetLockWithS3BootScript (=0D + VOID=0D + )=0D +{=0D + UINT32 Data32Or;=0D + UINT32 Data32And;=0D + UINT16 Address;=0D +=0D + Data32And =3D 0xFFFFFFFF;=0D +=0D + PchDmi14SrlRegData (&Address, &Data32Or);=0D +=0D + PchPcrAndThenOr32 (=0D + PID_DMI, Address,=0D + Data32And,=0D + Data32Or=0D + );=0D + PCH_PCR_BOOT_SCRIPT_READ_WRITE (=0D + S3BootScriptWidthUint32,=0D + PID_DMI, Address,=0D + &Data32Or,=0D + &Data32And=0D + );=0D +}=0D +=0D +/**=0D + Set BIOS interface Lock-Down=0D +**/=0D +VOID=0D +PchDmiSetBiosLockDownWithS3BootScript (=0D + VOID=0D + )=0D +{=0D + UINT32 Data32Or;=0D + UINT32 Data32And;=0D +=0D + //=0D + // Set BIOS Lock-Down (BILD)=0D + // When set, prevents GCS.BBS from being changed=0D + //=0D + Data32And =3D 0xFFFFFFFF;=0D + Data32Or =3D B_PCH_DMI_PCR_BILD;=0D + PchPcrAndThenOr32 (PID_DMI, R_PCH_DMI_PCR_GCS, Data32And, Data32Or);=0D + PCH_PCR_BOOT_SCRIPT_READ_WRITE (=0D + S3BootScriptWidthUint32,=0D + PID_DMI, R_PCH_DMI_PCR_GCS,=0D + &Data32Or,=0D + &Data32And=0D + );=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivat= e/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf b/Silicon/Intel/TigerlakeSilico= nPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf new file mode 100644 index 0000000000..d33310dd76 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDx= eSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf @@ -0,0 +1,42 @@ +## @file=0D +# Component description file for the PeiDxeSmmPchDmiLib=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmPchDmiLib=0D +FILE_GUID =3D 067DC1C4-2668-4F06-9921-307514B66B34=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D PchDmiLib=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + IoLib=0D + DebugLib=0D + PchInfoLib=0D + PchPcrLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D + PchDmiLib.c=0D + PchDmi14.c=0D + PchDmi14.h=0D +=0D +[Guids]=0D + gPchDmiConfigGuid ## CONSUMES=0D +=0D +[Pcd]=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivat= e/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf b/Silicon/Intel/Tigerlake= SiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmi= WithS3Lib.inf new file mode 100644 index 0000000000..9381a7b5fd --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDx= eSmmPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf @@ -0,0 +1,41 @@ +## @file=0D +# Component description file for the PeiDxeSmmPchDmiWithS3Lib=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmPchDmiWithS3Lib=0D +FILE_GUID =3D 32CCA047-6AF0-46FF-83DA-32BA62484075=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D PchDmiWithS3Lib=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + IoLib=0D + DebugLib=0D + PchPcrLib=0D + PchInfoLib=0D + S3BootScriptLib=0D + PchDmiLib=0D +=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D + PchDmiWithS3Lib.c=0D + PchDmi14.h=0D +=0D +[pcd]=0D --=20 2.24.0.windows.2