From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.27865.1612143472735878000 for ; Sun, 31 Jan 2021 17:37:53 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: heng.luo@intel.com) IronPort-SDR: gRcnSl8aXHAnjxXAhUvdxWoz9HTw8bIawjSJM3I87HauXV7sD1KLTLpE3Kd5ylSPm+SWnvG7DX QxDutI4SEMqw== X-IronPort-AV: E=McAfee;i="6000,8403,9881"; a="160388116" X-IronPort-AV: E=Sophos;i="5.79,391,1602572400"; d="scan'208";a="160388116" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2021 17:37:52 -0800 IronPort-SDR: xFBzkOB+JXv2ScGOD2hs3MnyAm7qzhKriYP/YroxbgEVNeVIFyDDedX7t3f30ZKjjOT5getmg/ Ohpzpm4OFAvA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,391,1602572400"; d="scan'208";a="368718818" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 31 Jan 2021 17:37:51 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [PATCH 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and Vtd library instances Date: Mon, 1 Feb 2021 09:36:52 +0800 Message-Id: <20210201013657.1833-35-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210201013657.1833-1-heng.luo@intel.com> References: <20210201013657.1833-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib * Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCp= uPcieInfoFruLib/CpuPcieInfoFruLib.c | 81 +++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCp= uPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf | 36 +++++++++++++++++++++++= +++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInit= Lib/DxeVtdInitFruLib.c | 18 ++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInit= Lib/DxeVtdInitFruLib.inf | 39 +++++++++++++++++++++++= ++++++++++++++++ 4 files changed, 174 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library= /PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c b/Silicon/Intel/TigerlakeSi= liconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInf= oFruLib.c new file mode 100644 index 0000000000..6a9bc89ecf --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxe= SmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c @@ -0,0 +1,81 @@ +/** @file=0D + CPU PCIe information library.=0D +=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Get Maximum CPU Pcie Root Port Number=0D +=0D + @retval Maximum CPU Pcie Root Port Number=0D +**/=0D +UINT8=0D +GetMaxCpuPciePortNum (=0D + VOID=0D + )=0D +{=0D + return CPU_PCIE_ULT_ULX_MAX_ROOT_PORT;=0D +}=0D +=0D +/**=0D + Get CPU Pcie Root Port Device and Function Number by Root Port physical = Number=0D +=0D + @param[in] RpNumber Root port physical number. (0-based)=0D + @param[out] RpDev Return corresponding root port device = number.=0D + @param[out] RpFun Return corresponding root port functio= n number.=0D +=0D + @retval EFI_SUCCESS Root port device and function is retri= eved=0D + @retval EFI_INVALID_PARAMETER RpNumber is invalid=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetCpuPcieRpDevFun (=0D + IN UINTN RpNumber,=0D + OUT UINTN *RpDev,=0D + OUT UINTN *RpFun=0D + )=0D +{=0D + if (RpNumber > GetMaxCpuPciePortNum ()) {=0D + DEBUG ((DEBUG_ERROR, "GetCpuPcieRpDevFun invalid RpNumber %x", RpNumbe= r));=0D + ASSERT (FALSE);=0D + return EFI_INVALID_PARAMETER;=0D + }=0D + //=0D + // For TGL - U/Y only one CPU PCIE Root port is present=0D + //=0D + *RpDev =3D 6;=0D + *RpFun =3D 0;=0D + return EFI_SUCCESS;=0D +}=0D +/**=0D +=0D + Gets pci segment base address of PCIe root port.=0D +=0D + @param RpIndex Root Port Index (0 based)=0D +=0D + @return PCIe port base address.=0D +**/=0D +UINT64=0D +CpuPcieBase (=0D + IN UINT32 RpIndex=0D + )=0D +{=0D + UINTN RpDevice;=0D + UINTN RpFunction;=0D + GetCpuPcieRpDevFun (RpIndex, &RpDevice, &RpFunction);=0D + return PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, (UINT32) RpDevice= , (UINT32) RpFunction, 0);=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library= /PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf b/Silicon/Intel/= TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib= /PeiDxeSmmCpuPcieInfoFruLib.inf new file mode 100644 index 0000000000..b6a40b2f7c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CpuPcieRp/Library/PeiDxe= SmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf @@ -0,0 +1,36 @@ +## @file=0D +# CPU PCIe information library for TigerLake PCH.=0D +#=0D +# All function in this library is available for PEI, DXE, and SMM,=0D +# But do not support UEFI RUNTIME environment call.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmCpuPcieInfoFruLib=0D +FILE_GUID =3D 59CA5352-ED46-4449-BF1C-0D0074C4D5B1=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D CpuPcieInfoFruLib=0D +=0D +=0D +[LibraryClasses]=0D +IoLib=0D +BaseLib=0D +DebugLib=0D +PrintLib=0D +PcdLib=0D +ConfigBlockLib=0D +CpuPcieInitCommonLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D +CpuPcieInfoFruLib.c=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivat= e/DxeVtdInitLib/DxeVtdInitFruLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Fru/= TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.c new file mode 100644 index 0000000000..8a0a8b6335 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVt= dInitLib/DxeVtdInitFruLib.c @@ -0,0 +1,18 @@ +/** @file=0D + DXE Flu Library to initialize Vtd=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +=0D +/**=0D + For device that specified by Device Num and Function Num,=0D + mDevEnMap is used to check device presence.=0D + 0x80 means use Device ID to detemine presence=0D + 0x8F means force to update=0D +=0D + The structure is used to check if device scope is valid when update DMAR= table=0D +**/=0D +UINT16 mDevEnMap[][2] =3D {{0x0200, 0x80}, {0x0500, 0x80}, {0x1400, 0x80}= , {0x1401, 0x80}, {0x0700, 0x80}, {0x0701, 0x80}, {0x0702, 0x80}, {0x0703, = 0x80}, {0x1302, 0x8F}, {0x1303, 0x8F}};=0D +UINTN mDevEnMapSize =3D sizeof (mDevEnMap) / (sizeof (UINT16) * 2);=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivat= e/DxeVtdInitLib/DxeVtdInitFruLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/Fr= u/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.inf new file mode 100644 index 0000000000..e0aa88f68a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Vtd/LibraryPrivate/DxeVt= dInitLib/DxeVtdInitFruLib.inf @@ -0,0 +1,39 @@ +## @file=0D +# Library description file for DXE Phase Vtd Init=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D DxeVtdInitFruLib=0D +FILE_GUID =3D 18690D67-08A9-4DCE-B62D-CBE3AF7CFEE7=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D DXE_DRIVER=0D +LIBRARY_CLASS =3D DxeVtdFruLib=0D +=0D +=0D +[LibraryClasses]=0D +UefiLib=0D +UefiRuntimeServicesTableLib=0D +UefiBootServicesTableLib=0D +DebugLib=0D +DxeSaPolicyLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Protocols]=0D +gSaNvsAreaProtocolGuid ## CONSUMES=0D +=0D +[Sources]=0D +DxeVtdInitFruLib.c=0D +=0D +[FixedPcd]=0D +=0D +[Guids]=0D +gTcssHobGuid ## CONSUMES=0D --=20 2.24.0.windows.2